[PATCH 0/2] arm64: dts: ti: k3-j721e: Add DisplayPort

[PATCH 0/2] arm64: dts: ti: k3-j721e: Add DisplayPort

[Tomi Valkeinen]

Hi,

This is a preliminary series to add DisplayPort to J7 EVM dts files.
There are related binding patches that are not yet merged, but all
patches can be found from:

git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux.git 5.10/cdns-dp

I'm sending this series to show the actual use of all the bindings,
which should make it easier to spot issues with the bindings.

 Tomi

Tomi Valkeinen (2):
  arm64: dts: ti: k3-j721e-main: add DP & DP PHY
  arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm

 .../dts/ti/k3-j721e-common-proc-board.dts     |  72 ++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     | 104 ++++++++++++++++++
 2 files changed, 176 insertions(+)

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[PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY

[Tomi Valkeinen]

Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP
8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper.

A slight irregularity in the bindings is the DPTX PHY register block,
which is in the MHDP IP, but is needed and mapped by the PHY.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 104 ++++++++++++++++++++++
 1 file changed, 104 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 12ceea9b3c9a..82d89dd3faf5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -553,6 +553,82 @@ serdes3: serdes@5030000 {
 		};
 	};
 
+	serdes_wiz4: wiz@5050000 {
+		compatible = "ti,j721e-wiz-10g";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&dummy_cmn_refclk>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+		assigned-clocks = <&k3_clks 297 9>;
+		assigned-clock-parents = <&k3_clks 297 10>;
+		assigned-clock-rates = <19200000>;
+		num-lanes = <4>;
+		#reset-cells = <1>;
+		ranges = <0x5050000 0x0 0x5050000 0x10000>,
+			<0xa030a00 0x0 0xa030a00 0x40>;
+
+		wiz4_pll0_refclk: pll0-refclk {
+			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
+			clock-output-names = "wiz4_pll0_refclk";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz4_pll0_refclk>;
+			assigned-clock-parents = <&k3_clks 297 9>;
+		};
+
+		wiz4_pll1_refclk: pll1-refclk {
+			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
+			clock-output-names = "wiz4_pll1_refclk";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz4_pll1_refclk>;
+			assigned-clock-parents = <&k3_clks 297 9>;
+		};
+
+		wiz4_refclk_dig: refclk-dig {
+			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
+			clock-output-names = "wiz4_refclk_dig";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz4_refclk_dig>;
+			assigned-clock-parents = <&k3_clks 297 9>;
+		};
+
+		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
+			clocks = <&wiz4_refclk_dig>;
+			#clock-cells = <0>;
+		};
+
+		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+			clocks = <&wiz4_pll1_refclk>;
+			#clock-cells = <0>;
+		};
+
+		serdes4: serdes@5050000 {
+			/*
+			 * Note: we also map DPTX PHY registers as the Torrent
+			 * needs to manage those.
+			 */
+			compatible = "ti,j721e-serdes-10g";
+			reg = <0x5050000 0x10000>,
+			      <0xa030a00 0x40>; /* DPTX PHY */
+			reg-names = "torrent_phy", "dptx_phy";
+
+			resets = <&serdes_wiz4 0>;
+			reset-names = "torrent_reset";
+			clocks = <&wiz4_pll0_refclk>;
+			clock-names = "refclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			torrent_phy_dp: phy@0 {
+				reg = <0>;
+				resets = <&serdes_wiz4 1>;
+				cdns,phy-type = <PHY_TYPE_DP>;
+				cdns,num-lanes = <4>;
+				cdns,max-bit-rate = <5400>;
+				#phy-cells = <0>;
+			};
+		};
+	};
+
 	main_uart0: serial@2800000 {
 		compatible = "ti,j721e-uart", "ti,am654-uart";
 		reg = <0x00 0x02800000 0x00 0x100>;
@@ -1024,6 +1100,34 @@ ufs@4e84000 {
 		};
 	};
 
+	mhdp: dp-bridge@a000000 {
+		compatible = "ti,j721e-mhdp8546";
+		/*
+		 * Note: we do not map DPTX PHY area, as that is handled by
+		 * the PHY driver.
+		 */
+		reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
+		      <0x0 0x4f40000 0x0 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
+		reg-names = "mhdptx", "j721e-intg";
+
+		status = "disabled";
+
+		clocks = <&k3_clks 151 36>;
+
+		phys = <&torrent_phy_dp>;
+		phy-names = "dpphy";
+
+		interrupt-parent = <&gic500>;
+		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
+
+		dp0_ports: ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
 	dss: dss@04a00000 {
 		compatible = "ti,j721e-dss";
 		reg =
-- 
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[PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm

[Tomi Valkeinen]

Add DisplayPort support.

The DP PWR is currently set as 'regulator-always-on', as we don't have a
dp-connector driver that would handle the power. When we do get such a
driver, the 'regulator-always-on' can be dropped.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 .../dts/ti/k3-j721e-common-proc-board.dts     | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index e8fc01d97ada..158377fe6640 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -83,6 +83,31 @@ sound0: sound@0 {
 			      "cpb-codec-scki",
 			      "cpb-codec-scki-48000", "cpb-codec-scki-44100";
 	};
+
+	dp_pwr_3v3: fixedregulator-dp-prw {
+		compatible = "regulator-fixed";
+		regulator-name = "dp-pwr";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&exp4 0 0>;	/* P0 - DP0_PWR_SW_EN */
+		enable-active-high;
+
+		/* Always on for now, until dp-connector driver can handle this */
+		regulator-always-on;
+	};
+
+	dp0: connector {
+		compatible = "dp-connector";
+		label = "DP0";
+		type = "full-size";
+		dp-pwr-supply = <&dp_pwr_3v3>;
+
+		port {
+			dp_connector_in: endpoint {
+				remote-endpoint = <&dp0_out>;
+			};
+		};
+	};
 };
 
 &main_pmx0 {
@@ -119,6 +144,12 @@ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
 		>;
 	};
 
+	dp0_pins_default: dp0_pins_default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
+		>;
+	};
+
 	main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
 		pinctrl-single,pins = <
 			J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
@@ -630,6 +661,47 @@ &dss {
 				 <&k3_clks 152 6>,	/* PLL19_HSDIV0 */
 				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */
 				 <&k3_clks 152 18>;	/* PLL23_HSDIV0 */
+
+	status = "ok";
+};
+
+&dss_ports {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	port@0 {
+		reg = <0>;
+
+		dpi0_out: endpoint {
+			remote-endpoint = <&dp0_in>;
+		};
+	};
+};
+
+&mhdp {
+	status = "ok";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&dp0_pins_default>;
+};
+
+&dp0_ports {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	port@0 {
+		reg = <0>;
+		dp0_in: endpoint {
+			remote-endpoint = <&dpi0_out>;
+		};
+	};
+
+	port@4 {
+		reg = <4>;
+		dp0_out: endpoint {
+			remote-endpoint = <&dp_connector_in>;
+		};
+	};
 };
 
 &mcasp10 {
-- 
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Re: [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY

[Nishanth Menon]

On 10:12-20200917, Tomi Valkeinen wrote:
> Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP
> 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper.
> 
> A slight irregularity in the bindings is the DPTX PHY register block,
> which is in the MHDP IP, but is needed and mapped by the PHY.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

just quick notes below:

> ---
>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 104 ++++++++++++++++++++++
>  1 file changed, 104 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index 12ceea9b3c9a..82d89dd3faf5 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -553,6 +553,82 @@ serdes3: serdes@5030000 {
>  		};
>  	};
>  
> +	serdes_wiz4: wiz@5050000 {
serdes-mux ? - I think we might want to cleanup other similar usage
instead of "wiz" or maybe just "mux"?

> +		compatible = "ti,j721e-wiz-10g";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&dummy_cmn_refclk>;
> +		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> +		assigned-clocks = <&k3_clks 297 9>;
> +		assigned-clock-parents = <&k3_clks 297 10>;
> +		assigned-clock-rates = <19200000>;
> +		num-lanes = <4>;
> +		#reset-cells = <1>;
> +		ranges = <0x5050000 0x0 0x5050000 0x10000>,
> +			<0xa030a00 0x0 0xa030a00 0x40>;
> +
> +		wiz4_pll0_refclk: pll0-refclk {
	clock@ ?
> +			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
> +			clock-output-names = "wiz4_pll0_refclk";
> +			#clock-cells = <0>;
> +			assigned-clocks = <&wiz4_pll0_refclk>;
> +			assigned-clock-parents = <&k3_clks 297 9>;
> +		};
> +
> +		wiz4_pll1_refclk: pll1-refclk {
	same?
> +			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
> +			clock-output-names = "wiz4_pll1_refclk";
> +			#clock-cells = <0>;
> +			assigned-clocks = <&wiz4_pll1_refclk>;
> +			assigned-clock-parents = <&k3_clks 297 9>;
> +		};
> +
> +		wiz4_refclk_dig: refclk-dig {
	same?
> +			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
> +			clock-output-names = "wiz4_refclk_dig";
> +			#clock-cells = <0>;
> +			assigned-clocks = <&wiz4_refclk_dig>;
> +			assigned-clock-parents = <&k3_clks 297 9>;
> +		};
> +
> +		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
	same?
> +			clocks = <&wiz4_refclk_dig>;
> +			#clock-cells = <0>;
> +		};
> +
> +		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
	same?
> +			clocks = <&wiz4_pll1_refclk>;
> +			#clock-cells = <0>;
> +		};
> +
> +		serdes4: serdes@5050000 {
> +			/*
> +			 * Note: we also map DPTX PHY registers as the Torrent
> +			 * needs to manage those.
> +			 */
> +			compatible = "ti,j721e-serdes-10g";
> +			reg = <0x5050000 0x10000>,
> +			      <0xa030a00 0x40>; /* DPTX PHY */
> +			reg-names = "torrent_phy", "dptx_phy";
> +
> +			resets = <&serdes_wiz4 0>;
> +			reset-names = "torrent_reset";
> +			clocks = <&wiz4_pll0_refclk>;
> +			clock-names = "refclk";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			torrent_phy_dp: phy@0 {
> +				reg = <0>;
> +				resets = <&serdes_wiz4 1>;
> +				cdns,phy-type = <PHY_TYPE_DP>;
> +				cdns,num-lanes = <4>;
> +				cdns,max-bit-rate = <5400>;
> +				#phy-cells = <0>;
> +			};
> +		};
> +	};
> +
Do you see any impact of the discussions we are having at [1] ?

>  	main_uart0: serial@2800000 {
>  		compatible = "ti,j721e-uart", "ti,am654-uart";
>  		reg = <0x00 0x02800000 0x00 0x100>;
> @@ -1024,6 +1100,34 @@ ufs@4e84000 {
>  		};
>  	};
>  
> +	mhdp: dp-bridge@a000000 {
> +		compatible = "ti,j721e-mhdp8546";
> +		/*
> +		 * Note: we do not map DPTX PHY area, as that is handled by
> +		 * the PHY driver.
> +		 */
> +		reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
> +		      <0x0 0x4f40000 0x0 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
> +		reg-names = "mhdptx", "j721e-intg";
> +
> +		status = "disabled";
> +
> +		clocks = <&k3_clks 151 36>;
> +
> +		phys = <&torrent_phy_dp>;
> +		phy-names = "dpphy";
> +
> +		interrupt-parent = <&gic500>;
> +		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
> +
> +		dp0_ports: ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +
>  	dss: dss@04a00000 {
>  		compatible = "ti,j721e-dss";
>  		reg =
> -- 
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> 

[1] https://lore.kernel.org/linux-devicetree/8a27f8f3-20c4-f72c-b683-81153107d867@ti.com/
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY

[Tomi Valkeinen]

Hi Nishanth,

On 17/09/2020 16:07, Nishanth Menon wrote:
> On 10:12-20200917, Tomi Valkeinen wrote:
>> Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP
>> 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper.
>>
>> A slight irregularity in the bindings is the DPTX PHY register block,
>> which is in the MHDP IP, but is needed and mapped by the PHY.
>>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> 
> just quick notes below:
> 
>> ---
>>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 104 ++++++++++++++++++++++
>>  1 file changed, 104 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index 12ceea9b3c9a..82d89dd3faf5 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -553,6 +553,82 @@ serdes3: serdes@5030000 {
>>  		};
>>  	};
>>  
>> +	serdes_wiz4: wiz@5050000 {
> serdes-mux ? - I think we might want to cleanup other similar usage
> instead of "wiz" or maybe just "mux"?
> 
>> +		compatible = "ti,j721e-wiz-10g";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
>> +		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&dummy_cmn_refclk>;
>> +		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
>> +		assigned-clocks = <&k3_clks 297 9>;
>> +		assigned-clock-parents = <&k3_clks 297 10>;
>> +		assigned-clock-rates = <19200000>;
>> +		num-lanes = <4>;
>> +		#reset-cells = <1>;
>> +		ranges = <0x5050000 0x0 0x5050000 0x10000>,
>> +			<0xa030a00 0x0 0xa030a00 0x40>;
>> +
>> +		wiz4_pll0_refclk: pll0-refclk {
> 	clock@ ?
>> +			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
>> +			clock-output-names = "wiz4_pll0_refclk";
>> +			#clock-cells = <0>;
>> +			assigned-clocks = <&wiz4_pll0_refclk>;
>> +			assigned-clock-parents = <&k3_clks 297 9>;
>> +		};
>> +
>> +		wiz4_pll1_refclk: pll1-refclk {
> 	same?
>> +			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
>> +			clock-output-names = "wiz4_pll1_refclk";
>> +			#clock-cells = <0>;
>> +			assigned-clocks = <&wiz4_pll1_refclk>;
>> +			assigned-clock-parents = <&k3_clks 297 9>;
>> +		};
>> +
>> +		wiz4_refclk_dig: refclk-dig {
> 	same?
>> +			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
>> +			clock-output-names = "wiz4_refclk_dig";
>> +			#clock-cells = <0>;
>> +			assigned-clocks = <&wiz4_refclk_dig>;
>> +			assigned-clock-parents = <&k3_clks 297 9>;
>> +		};
>> +
>> +		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
> 	same?
>> +			clocks = <&wiz4_refclk_dig>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
> 	same?
>> +			clocks = <&wiz4_pll1_refclk>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		serdes4: serdes@5050000 {
>> +			/*
>> +			 * Note: we also map DPTX PHY registers as the Torrent
>> +			 * needs to manage those.
>> +			 */
>> +			compatible = "ti,j721e-serdes-10g";
>> +			reg = <0x5050000 0x10000>,
>> +			      <0xa030a00 0x40>; /* DPTX PHY */
>> +			reg-names = "torrent_phy", "dptx_phy";
>> +
>> +			resets = <&serdes_wiz4 0>;
>> +			reset-names = "torrent_reset";
>> +			clocks = <&wiz4_pll0_refclk>;
>> +			clock-names = "refclk";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			torrent_phy_dp: phy@0 {
>> +				reg = <0>;
>> +				resets = <&serdes_wiz4 1>;
>> +				cdns,phy-type = <PHY_TYPE_DP>;
>> +				cdns,num-lanes = <4>;
>> +				cdns,max-bit-rate = <5400>;
>> +				#phy-cells = <0>;
>> +			};
>> +		};
>> +	};
>> +
> Do you see any impact of the discussions we are having at [1] ?
You mean using wiz or serdes naming all around?

But I think the answer to all the comments is the same: I'm following what's already there for
serdes 0-3 in k3-j721e-main.dtsi, and what's defined in ti,phy-j721e-wiz.yaml.

Kishon is probably better person to answer about changes to the wiz naming.

 Tomi

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