From: Catalin Marinas <catalin.marinas@arm.com>
To: Orson Zhai <orsonzhai@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 0/4] arm: Privileged no-access for LPAE
Date: Mon, 28 Sep 2020 17:29:20 +0100 [thread overview]
Message-ID: <20200928162919.GD27500@gaia> (raw)
In-Reply-To: <20200928130907.GA5484@lenovo>
On Mon, Sep 28, 2020 at 09:09:07PM +0800, Orson Zhai wrote:
> On Fri, Dec 11, 2015 at 05:21:40PM +0000, Catalin Marinas wrote:
> > On Thu, Dec 10, 2015 at 11:40:44AM -0800, Kees Cook wrote:
> > > [thread necromancy]
> > >
> > > This series looks good to me. I'd love to see it accepted. At the very
> > > least the cleanups look like no-brainers. :)
> > >
> > > Please consider the series:
> > >
> > > Reviewed-by: Kees Cook <keescook@chromium.org>
> > >
> > > Thanks for working on it!
> >
> > Thanks for the review. After some more (internal) discussions around
> > these patches, I need to get clarification on the architecture whether
> > changing the TTBCR.A1 bit is enough to guarantee an ASID change (I do
>
> Did you check it after then? Now I have a real requirement for implementing
> LPAE and PAN at the same time. So I'd like to know if this patch could work.
> I had some talk with Will about it at other place. He thought this patch is
> not in correct state.
>
> May I have your latest opinions?
It may work on specific 32-bit CPU implementations but it's not
guaranteed since the TTBCR.A1 bit is allowed to be cached in the TLB. If
you have a CPU implementation in mind, you could check with the
microarchitects whether A1 is cached in the TLB. But since that's not
universally applicable, the patchset cannot be merged into mainline.
I haven't touched these patches for the past 5 years, so I can't tell
whether they still apply.
--
Catalin
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prev parent reply other threads:[~2020-09-28 16:30 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-23 14:24 [PATCH 0/4] arm: Privileged no-access for LPAE Catalin Marinas
2015-09-23 14:24 ` [PATCH 1/4] arm: kvm: Move TTBCR_* definitions from kvm_arm.h into pgtable-3level-hwdef.h Catalin Marinas
2015-09-23 14:24 ` [PATCH 2/4] arm: Move asm statements accessing TTBCR into dedicated functions Catalin Marinas
2015-09-23 14:24 ` [PATCH 3/4] arm: Reduce the number of #ifdef CONFIG_CPU_SW_DOMAIN_PAN Catalin Marinas
2015-09-23 14:24 ` [PATCH 4/4] arm: Implement privileged no-access using TTBR0 page table walks disabling Catalin Marinas
2015-12-10 19:40 ` [PATCH 0/4] arm: Privileged no-access for LPAE Kees Cook
2015-12-11 17:21 ` Catalin Marinas
2020-09-28 13:09 ` Orson Zhai
2020-09-28 16:29 ` Catalin Marinas [this message]
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