* [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform
@ 2020-09-14 16:22 Lokesh Vutla
2020-09-14 16:22 ` [PATCH v4 1/5] arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs Lokesh Vutla
` (6 more replies)
0 siblings, 7 replies; 22+ messages in thread
From: Lokesh Vutla @ 2020-09-14 16:22 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Lokesh Vutla,
Sekhar Nori, Kishon Vijay Abraham I, Linux ARM Mailing List
This series adds initial support for latest new SoC, J7200, from Texas Instruments.
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded products.
See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1
This series is based on the ti-k3-dts-next from Nishanth's tree[0].
Boot log: https://pastebin.ubuntu.com/p/sJ4Xh4J488/
Changes since v3:
- Update epoch in Makefile
- Updated ranges for cbass main and mcu_wakeup
- s/pinmux/pinctrl
- s/navss@/bus@
- Added intr and inta nodes
- Added chosen node
Changes since v2:
- Update Makefile to build dtbs using CONFIG_ARCH_K3
- use 0x00 in all places just to be consistent for all K3 devices
- Fixed upper case to lower case in reg property.
[0] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
Lokesh Vutla (5):
arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs
dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema
dt-bindings: arm: ti: Add bindings for J7200 SoC
arm64: dts: ti: Add support for J7200 SoC
arm64: dts: ti: Add support for J7200 Common Processor Board
.../devicetree/bindings/arm/ti/k3.txt | 26 --
.../devicetree/bindings/arm/ti/k3.yaml | 35 +++
MAINTAINERS | 2 +-
arch/arm64/boot/dts/ti/Makefile | 8 +-
.../dts/ti/k3-j7200-common-proc-board.dts | 64 +++++
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 236 ++++++++++++++++++
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 95 +++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 29 +++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 172 +++++++++++++
9 files changed, 637 insertions(+), 30 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/ti/k3.txt
create mode 100644 Documentation/devicetree/bindings/arm/ti/k3.yaml
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v4 1/5] arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs
2020-09-14 16:22 [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform Lokesh Vutla
@ 2020-09-14 16:22 ` Lokesh Vutla
2020-09-15 15:28 ` Suman Anna
2020-09-14 16:22 ` [PATCH v4 2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema Lokesh Vutla
` (5 subsequent siblings)
6 siblings, 1 reply; 22+ messages in thread
From: Lokesh Vutla @ 2020-09-14 16:22 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Lokesh Vutla,
Sekhar Nori, Kishon Vijay Abraham I, Linux ARM Mailing List
To allow lesser dependency and better maintainability use CONFIG_ARCH_K3
for building dtbs for all K3 based devices. This is as per the
discussion in [0].
[0] https://lore.kernel.org/linux-arm-kernel/20200908112534.t5bgrjf7y3a6l2ss@akan/
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 05c0bebf65d4..7f28be62b8da 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -3,9 +3,9 @@
# Make file to build device tree binaries for boards based on
# Texas Instruments Inc processors
#
-# Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
#
-dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
-dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v4 2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema
2020-09-14 16:22 [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform Lokesh Vutla
2020-09-14 16:22 ` [PATCH v4 1/5] arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs Lokesh Vutla
@ 2020-09-14 16:22 ` Lokesh Vutla
2020-09-15 15:31 ` Suman Anna
` (2 more replies)
2020-09-14 16:22 ` [PATCH v4 3/5] dt-bindings: arm: ti: Add bindings for J7200 SoC Lokesh Vutla
` (4 subsequent siblings)
6 siblings, 3 replies; 22+ messages in thread
From: Lokesh Vutla @ 2020-09-14 16:22 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Lokesh Vutla,
Sekhar Nori, Kishon Vijay Abraham I, Linux ARM Mailing List
Convert TI K3 Board/SoC bindings to DT schema format.
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
.../devicetree/bindings/arm/ti/k3.txt | 26 ----------------
.../devicetree/bindings/arm/ti/k3.yaml | 31 +++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 32 insertions(+), 27 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/ti/k3.txt
create mode 100644 Documentation/devicetree/bindings/arm/ti/k3.yaml
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt
deleted file mode 100644
index 333e7256126a..000000000000
--- a/Documentation/devicetree/bindings/arm/ti/k3.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Texas Instruments K3 Multicore SoC architecture device tree bindings
---------------------------------------------------------------------
-
-Platforms based on Texas Instruments K3 Multicore SoC architecture
-shall follow the following scheme:
-
-SoCs
-----
-
-Each device tree root node must specify which exact SoC in K3 Multicore SoC
-architecture it uses, using one of the following compatible values:
-
-- AM654
- compatible = "ti,am654";
-
-- J721E
- compatible = "ti,j721e";
-
-Boards
-------
-
-In addition, each device tree root node must specify which one or more
-of the following board-specific compatible values:
-
-- AM654 EVM
- compatible = "ti,am654-evm", "ti,am654";
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
new file mode 100644
index 000000000000..c5e3e4aeda8e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/ti/k3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 Multicore SoC architecture device tree bindings
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+description: |
+ Platforms based on Texas Instruments K3 Multicore SoC architecture
+ shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: K3 AM654 SoC
+ items:
+ - enum:
+ - ti,am654-evm
+ - const: ti,am654
+
+ - description: K3 J721E SoC
+ items:
+ - const: ti,j721e
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index e4647c84c987..076fae9aa75b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2636,7 +2636,7 @@ M: Tero Kristo <t-kristo@ti.com>
M: Nishanth Menon <nm@ti.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
-F: Documentation/devicetree/bindings/arm/ti/k3.txt
+F: Documentation/devicetree/bindings/arm/ti/k3.yaml
F: arch/arm64/boot/dts/ti/Makefile
F: arch/arm64/boot/dts/ti/k3-*
F: include/dt-bindings/pinctrl/k3.h
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v4 3/5] dt-bindings: arm: ti: Add bindings for J7200 SoC
2020-09-14 16:22 [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform Lokesh Vutla
2020-09-14 16:22 ` [PATCH v4 1/5] arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs Lokesh Vutla
2020-09-14 16:22 ` [PATCH v4 2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema Lokesh Vutla
@ 2020-09-14 16:22 ` Lokesh Vutla
2020-09-15 15:28 ` Suman Anna
2020-09-22 23:41 ` Rob Herring
2020-09-14 16:22 ` [PATCH v4 4/5] arm64: dts: ti: Add support " Lokesh Vutla
` (3 subsequent siblings)
6 siblings, 2 replies; 22+ messages in thread
From: Lokesh Vutla @ 2020-09-14 16:22 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Lokesh Vutla,
Sekhar Nori, Kishon Vijay Abraham I, Linux ARM Mailing List
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
capable dual Cortex-R5F MCUs and a Centralized Device Management and
Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
Documentation/devicetree/bindings/arm/ti/k3.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index c5e3e4aeda8e..829751209543 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -28,4 +28,8 @@ properties:
- description: K3 J721E SoC
items:
- const: ti,j721e
+
+ - description: K3 J7200 SoC
+ items:
+ - const: ti,j7200
...
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v4 4/5] arm64: dts: ti: Add support for J7200 SoC
2020-09-14 16:22 [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform Lokesh Vutla
` (2 preceding siblings ...)
2020-09-14 16:22 ` [PATCH v4 3/5] dt-bindings: arm: ti: Add bindings for J7200 SoC Lokesh Vutla
@ 2020-09-14 16:22 ` Lokesh Vutla
2020-09-15 5:09 ` Vignesh Raghavendra
2020-09-15 12:11 ` Kishon Vijay Abraham I
2020-09-14 16:22 ` [PATCH v4 5/5] arm64: dts: ti: Add support for J7200 Common Processor Board Lokesh Vutla
` (2 subsequent siblings)
6 siblings, 2 replies; 22+ messages in thread
From: Lokesh Vutla @ 2020-09-14 16:22 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Lokesh Vutla,
Sekhar Nori, Kishon Vijay Abraham I, Linux ARM Mailing List
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
capable dual Cortex-R5F MCUs and a Centralized Device Management and
Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C
and I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 236 ++++++++++++++++++
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 95 +++++++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 172 +++++++++++++
3 files changed, 503 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
new file mode 100644
index 000000000000..3df49577b06a
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J7200 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ msmc_ram: sram@70000000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x70000000 0x00 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x70000000 0x100000>;
+
+ atf-sram@0 {
+ reg = <0x00 0x20000>;
+ };
+ };
+
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01900000 0x00 0x100000>; /* GICR */
+
+ /* vcpumntirq: virtual CPU interface maintenance interrupt */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ main_gpio_intr: interrupt-controller0 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <131>;
+ ti,interrupt-ranges = <8 392 56>;
+ };
+
+ main_navss: bus@30000000 {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+ ti,sci-dev-id = <199>;
+
+ main_navss_intr: interrupt-controller1 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <4>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <213>;
+ ti,interrupt-ranges = <0 64 64>,
+ <64 448 64>,
+ <128 672 64>;
+ };
+
+ main_udmass_inta: msi-controller@33d00000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x33d00000 0x00 0x100000>;
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ interrupt-parent = <&main_navss_intr>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <209>;
+ ti,interrupt-ranges = <0 0 256>;
+ };
+
+ secure_proxy_main: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x32c00000 0x00 0x100000>,
+ <0x00 0x32400000 0x00 0x100000>,
+ <0x00 0x32800000 0x00 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ main_pmx0: pinctrl@11c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x11c000 0x00 0x2b4>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 146 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 278 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 279 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart3: serial@2830000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 280 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart4: serial@2840000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 281 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart5: serial@2850000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 282 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart6: serial@2860000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 283 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart7: serial@2870000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02870000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 284 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart8: serial@2880000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02880000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 285 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart9: serial@2890000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02890000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 286 2>;
+ clock-names = "fclk";
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
new file mode 100644
index 000000000000..ec2745e0768e
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu_wakeup {
+ dmsc: dmsc@44083000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+
+ mbox-names = "rx", "tx";
+
+ mboxes= <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
+
+ reg-names = "debug_messages";
+ reg = <0x00 0x44083000 0x00 0x1000>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ chipid@43000014 {
+ compatible = "ti,am654-chipid";
+ reg = <0x00 0x43000014 0x00 0x4>;
+ };
+
+ wkup_pmx0: pinctrl@4301c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c000 0x00 0x178>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ mcu_ram: sram@41c00000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x41c00000 0x00 0x100000>;
+ ranges = <0x00 0x00 0x41c00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ wkup_uart0: serial@42300000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x42300000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 287 2>;
+ clock-names = "fclk";
+ };
+
+ mcu_uart0: serial@40a00000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x40a00000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <96000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 149 2>;
+ clock-names = "fclk";
+ };
+
+ wkup_gpio_intr: interrupt-controller2 {
+ compatible = "ti,sci-intr";
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <137>;
+ ti,interrupt-ranges = <16 960 16>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
new file mode 100644
index 000000000000..66169bcf7c9a
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J7200 SoC Family
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+ model = "Texas Instruments K3 J7200 SoC";
+ compatible = "ti,j7200";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ serial4 = &main_uart2;
+ serial5 = &main_uart3;
+ serial6 = &main_uart4;
+ serial7 = &main_uart5;
+ serial8 = &main_uart6;
+ serial9 = &main_uart7;
+ serial10 = &main_uart8;
+ serial11 = &main_uart9;
+ };
+
+ chosen { };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a72";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a72";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ next-level-cache = <&msmc_l3>;
+ };
+
+ msmc_l3: l3-cache0 {
+ compatible = "cache";
+ cache-level = <3>;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a72_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: bus@100000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
+ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
+ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
+
+ /* MCUSS_WKUP Range */
+ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
+
+ cbass_mcu_wakeup: bus@28380000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
+ };
+ };
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-j7200-main.dtsi"
+#include "k3-j7200-mcu-wakeup.dtsi"
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v4 5/5] arm64: dts: ti: Add support for J7200 Common Processor Board
2020-09-14 16:22 [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform Lokesh Vutla
` (3 preceding siblings ...)
2020-09-14 16:22 ` [PATCH v4 4/5] arm64: dts: ti: Add support " Lokesh Vutla
@ 2020-09-14 16:22 ` Lokesh Vutla
2020-09-15 15:33 ` Suman Anna
2020-09-15 11:35 ` [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform Nishanth Menon
2020-09-23 14:24 ` Nishanth Menon
6 siblings, 1 reply; 22+ messages in thread
From: Lokesh Vutla @ 2020-09-14 16:22 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Lokesh Vutla,
Sekhar Nori, Kishon Vijay Abraham I, Linux ARM Mailing List
Add support for J7200 Common Processor Board.
The EVM architecture is very similar to J721E as follows:
+------------------------------------------------------+
| +-------------------------------------------+ |
| | | |
| | Add-on Card 1 Options | |
| | | |
| +-------------------------------------------+ |
| |
| |
| +-------------------+ |
| | | |
| | SOM | |
| +--------------+ | | |
| | | | | |
| | Add-on | +-------------------+ |
| | Card 2 | | Power Supply
| | Options | | |
| | | | |
| +--------------+ | <---
+------------------------------------------------------+
Common Processor Board
Common Processor board is the baseboard that has most of the actual
connectors, power supply etc. A SOM (System on Module) is plugged on
to the common processor board and this contains the SoC, PMIC, DDR and
basic high speed components necessary for functionality.
Note:
* The minimum configuration required to boot up the board is System On
Module(SOM) + Common Processor Board.
* Since there is just a single SOM and Common Processor Board, we are
maintaining common processor board as the base dts and SOM as the dtsi
that we include. In the future as more SOM's appear, we should move
common processor board as a dtsi and include configurations as dts.
* All daughter cards beyond the basic boards shall be maintained as
overlays.
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 2 +
.../dts/ti/k3-j7200-common-proc-board.dts | 64 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 29 +++++++++
3 files changed, 95 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 7f28be62b8da..65506f21ba30 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -9,3 +9,5 @@
dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
+
+dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
new file mode 100644
index 000000000000..e27069317c4e
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j7200-som-p0.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by System firmware */
+ status = "disabled";
+};
+
+&main_uart0 {
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_uart2 {
+ /* MAIN UART 2 is used by R5F firmware */
+ status = "disabled";
+};
+
+&main_uart3 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart4 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart5 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart6 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart7 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart8 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart9 {
+ /* UART not brought out */
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
new file mode 100644
index 000000000000..f7e271c442a0
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j7200.dtsi"
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ /* 4G RAM */
+ reg = <0x00 0x80000000 0x00 0x80000000>,
+ <0x08 0x80000000 0x00 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+};
--
2.28.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v4 4/5] arm64: dts: ti: Add support for J7200 SoC
2020-09-14 16:22 ` [PATCH v4 4/5] arm64: dts: ti: Add support " Lokesh Vutla
@ 2020-09-15 5:09 ` Vignesh Raghavendra
2020-09-15 11:34 ` Nishanth Menon
2020-09-15 12:11 ` Kishon Vijay Abraham I
1 sibling, 1 reply; 22+ messages in thread
From: Vignesh Raghavendra @ 2020-09-15 5:09 UTC (permalink / raw)
To: Lokesh Vutla, Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Sekhar Nori,
Linux ARM Mailing List, Kishon Vijay Abraham I
[...]
On 9/14/20 9:52 PM, Lokesh Vutla wrote:
> +
> + cbass_main: bus@100000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
> + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
> + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
> + <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
> + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
> + <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
> + <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
> + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
> +
> + /* MCUSS_WKUP Range */
> + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
> + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
> + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
> + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
> + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
> + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
> + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
> + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
> + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
> + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
> + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
> + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
> +
> + cbass_mcu_wakeup: bus@28380000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
> + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
> + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
> + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
> + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
> + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
> + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
> + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
> + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
> + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
> + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
> + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
> + };
> + };
> +};
OSPI ranges look good to me... Thanks for adding them!
[...]
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 4/5] arm64: dts: ti: Add support for J7200 SoC
2020-09-15 5:09 ` Vignesh Raghavendra
@ 2020-09-15 11:34 ` Nishanth Menon
2020-09-15 11:36 ` Vignesh Raghavendra
0 siblings, 1 reply; 22+ messages in thread
From: Nishanth Menon @ 2020-09-15 11:34 UTC (permalink / raw)
To: Vignesh Raghavendra
Cc: Device Tree Mailing List, Grygorii Strashko, Lokesh Vutla,
Sekhar Nori, Kishon Vijay Abraham I, Tero Kristo, Rob Herring,
Linux ARM Mailing List
On 10:39-20200915, Vignesh Raghavendra wrote:
> [...]
>
> On 9/14/20 9:52 PM, Lokesh Vutla wrote:
> > +
> > + cbass_main: bus@100000 {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
> > + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
> > + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
> > + <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
> > + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
> > + <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
> > + <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
> > + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
> > +
> > + /* MCUSS_WKUP Range */
> > + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
> > + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
> > + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
> > + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
> > + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
> > + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
> > + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
> > + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
> > + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
> > + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
> > + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
> > + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
> > + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
> > +
> > + cbass_mcu_wakeup: bus@28380000 {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
> > + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
> > + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
> > + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
> > + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
> > + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
> > + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
> > + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
> > + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
> > + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
> > + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
> > + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
> > + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
> > + };
> > + };
> > +};
>
> OSPI ranges look good to me... Thanks for adding them!
>
> [...]
Is that a reviewed-by ? if so, please add tag?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform
2020-09-14 16:22 [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform Lokesh Vutla
` (4 preceding siblings ...)
2020-09-14 16:22 ` [PATCH v4 5/5] arm64: dts: ti: Add support for J7200 Common Processor Board Lokesh Vutla
@ 2020-09-15 11:35 ` Nishanth Menon
2020-09-23 14:24 ` Nishanth Menon
6 siblings, 0 replies; 22+ messages in thread
From: Nishanth Menon @ 2020-09-15 11:35 UTC (permalink / raw)
To: Lokesh Vutla
Cc: Device Tree Mailing List, Grygorii Strashko, Sekhar Nori,
Kishon Vijay Abraham I, Tero Kristo, Rob Herring,
Linux ARM Mailing List
On 21:52-20200914, Lokesh Vutla wrote:
> This series adds initial support for latest new SoC, J7200, from Texas Instruments.
>
[..]
>
> Lokesh Vutla (5):
> arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs
> dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema
> dt-bindings: arm: ti: Add bindings for J7200 SoC
> arm64: dts: ti: Add support for J7200 SoC
> arm64: dts: ti: Add support for J7200 Common Processor Board
>
> .../devicetree/bindings/arm/ti/k3.txt | 26 --
> .../devicetree/bindings/arm/ti/k3.yaml | 35 +++
>
Series looks fine to me at least.. but the binding changes, will be
great if DT maintainers could review it.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 4/5] arm64: dts: ti: Add support for J7200 SoC
2020-09-15 11:34 ` Nishanth Menon
@ 2020-09-15 11:36 ` Vignesh Raghavendra
0 siblings, 0 replies; 22+ messages in thread
From: Vignesh Raghavendra @ 2020-09-15 11:36 UTC (permalink / raw)
To: Nishanth Menon
Cc: Device Tree Mailing List, Grygorii Strashko, Lokesh Vutla,
Sekhar Nori, Kishon Vijay Abraham I, Tero Kristo, Rob Herring,
Linux ARM Mailing List
On 9/15/20 5:04 PM, Nishanth Menon wrote:
> On 10:39-20200915, Vignesh Raghavendra wrote:
>> [...]
>>
>> On 9/14/20 9:52 PM, Lokesh Vutla wrote:
>>> +
>>> + cbass_main: bus@100000 {
>>> + compatible = "simple-bus";
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
>>> + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
>>> + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
>>> + <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
>>> + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
>>> + <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
>>> + <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
>>> + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
>>> +
>>> + /* MCUSS_WKUP Range */
>>> + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
>>> + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
>>> + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
>>> + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
>>> + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
>>> + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
>>> + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
>>> + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
>>> + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
>>> + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
>>> + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
>>> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
>>> + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
>>> +
>>> + cbass_mcu_wakeup: bus@28380000 {
>>> + compatible = "simple-bus";
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
>>> + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
>>> + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
>>> + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
>>> + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
>>> + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
>>> + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
>>> + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
>>> + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
>>> + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
>>> + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
>>> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
>>> + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
>>> + };
>>> + };
>>> +};
>>
>> OSPI ranges look good to me... Thanks for adding them!
>>
>> [...]
>
> Is that a reviewed-by ? if so, please add tag?
>
For OSPI bits:
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 4/5] arm64: dts: ti: Add support for J7200 SoC
2020-09-14 16:22 ` [PATCH v4 4/5] arm64: dts: ti: Add support " Lokesh Vutla
2020-09-15 5:09 ` Vignesh Raghavendra
@ 2020-09-15 12:11 ` Kishon Vijay Abraham I
1 sibling, 0 replies; 22+ messages in thread
From: Kishon Vijay Abraham I @ 2020-09-15 12:11 UTC (permalink / raw)
To: Lokesh Vutla, Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Sekhar Nori,
Linux ARM Mailing List
On 14/09/20 9:52 pm, Lokesh Vutla wrote:
> The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
> It is targeted for automotive gateway, vehicle compute systems,
> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
> The SoC aims to meet the complex processing needs of modern embedded
> products.
>
> Some highlights of this SoC are:
> * Dual Cortex-A72s in a single cluster, two clusters of lockstep
> capable dual Cortex-R5F MCUs and a Centralized Device Management and
> Security Controller (DMSC).
> * Configurable L3 Cache and IO-coherent architecture with high data
> throughput capable distributed DMA architecture under NAVSS.
> * Integrated Ethernet switch supporting up to a total of 4 external ports
> in addition to legacy Ethernet switch of up to 2 ports.
> * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
> 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C
> and I2C, eCAP/eQEP, eHRPWM among other peripherals.
> * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
> management.
>
> See J7200 Technical Reference Manual (SPRUIU1, June 2020)
> for further details: https://www.ti.com/lit/pdf/spruiu1
>
> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Reviewed-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 236 ++++++++++++++++++
> .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 95 +++++++
> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 172 +++++++++++++
> 3 files changed, 503 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> new file mode 100644
> index 000000000000..3df49577b06a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -0,0 +1,236 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for J7200 SoC Family Main Domain peripherals
> + *
> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&cbass_main {
> + msmc_ram: sram@70000000 {
> + compatible = "mmio-sram";
> + reg = <0x00 0x70000000 0x00 0x100000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x00 0x00 0x70000000 0x100000>;
> +
> + atf-sram@0 {
> + reg = <0x00 0x20000>;
> + };
> + };
> +
> + gic500: interrupt-controller@1800000 {
> + compatible = "arm,gic-v3";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
> + <0x00 0x01900000 0x00 0x100000>; /* GICR */
> +
> + /* vcpumntirq: virtual CPU interface maintenance interrupt */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + gic_its: msi-controller@1820000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x00 0x01820000 0x00 0x10000>;
> + socionext,synquacer-pre-its = <0x1000000 0x400000>;
> + msi-controller;
> + #msi-cells = <1>;
> + };
> + };
> +
> + main_gpio_intr: interrupt-controller0 {
> + compatible = "ti,sci-intr";
> + ti,intr-trigger-type = <1>;
> + interrupt-controller;
> + interrupt-parent = <&gic500>;
> + #interrupt-cells = <1>;
> + ti,sci = <&dmsc>;
> + ti,sci-dev-id = <131>;
> + ti,interrupt-ranges = <8 392 56>;
> + };
> +
> + main_navss: bus@30000000 {
> + compatible = "simple-mfd";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
> + ti,sci-dev-id = <199>;
> +
> + main_navss_intr: interrupt-controller1 {
> + compatible = "ti,sci-intr";
> + ti,intr-trigger-type = <4>;
> + interrupt-controller;
> + interrupt-parent = <&gic500>;
> + #interrupt-cells = <1>;
> + ti,sci = <&dmsc>;
> + ti,sci-dev-id = <213>;
> + ti,interrupt-ranges = <0 64 64>,
> + <64 448 64>,
> + <128 672 64>;
> + };
> +
> + main_udmass_inta: msi-controller@33d00000 {
> + compatible = "ti,sci-inta";
> + reg = <0x00 0x33d00000 0x00 0x100000>;
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + interrupt-parent = <&main_navss_intr>;
> + msi-controller;
> + ti,sci = <&dmsc>;
> + ti,sci-dev-id = <209>;
> + ti,interrupt-ranges = <0 0 256>;
> + };
> +
> + secure_proxy_main: mailbox@32c00000 {
> + compatible = "ti,am654-secure-proxy";
> + #mbox-cells = <1>;
> + reg-names = "target_data", "rt", "scfg";
> + reg = <0x00 0x32c00000 0x00 0x100000>,
> + <0x00 0x32400000 0x00 0x100000>,
> + <0x00 0x32800000 0x00 0x100000>;
> + interrupt-names = "rx_011";
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + main_pmx0: pinctrl@11c000 {
> + compatible = "pinctrl-single";
> + /* Proxy 0 addressing */
> + reg = <0x00 0x11c000 0x00 0x2b4>;
> + #pinctrl-cells = <1>;
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <0xffffffff>;
> + };
> +
> + main_uart0: serial@2800000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02800000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 146 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart1: serial@2810000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02810000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 278 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart2: serial@2820000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02820000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 279 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart3: serial@2830000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02830000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 280 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart4: serial@2840000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02840000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 281 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart5: serial@2850000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02850000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 282 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart6: serial@2860000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02860000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 283 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart7: serial@2870000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02870000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 284 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart8: serial@2880000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02880000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 285 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart9: serial@2890000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02890000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 286 2>;
> + clock-names = "fclk";
> + };
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> new file mode 100644
> index 000000000000..ec2745e0768e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
> + *
> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&cbass_mcu_wakeup {
> + dmsc: dmsc@44083000 {
> + compatible = "ti,k2g-sci";
> + ti,host-id = <12>;
> +
> + mbox-names = "rx", "tx";
> +
> + mboxes= <&secure_proxy_main 11>,
> + <&secure_proxy_main 13>;
> +
> + reg-names = "debug_messages";
> + reg = <0x00 0x44083000 0x00 0x1000>;
> +
> + k3_pds: power-controller {
> + compatible = "ti,sci-pm-domain";
> + #power-domain-cells = <2>;
> + };
> +
> + k3_clks: clocks {
> + compatible = "ti,k2g-sci-clk";
> + #clock-cells = <2>;
> + };
> +
> + k3_reset: reset-controller {
> + compatible = "ti,sci-reset";
> + #reset-cells = <2>;
> + };
> + };
> +
> + chipid@43000014 {
> + compatible = "ti,am654-chipid";
> + reg = <0x00 0x43000014 0x00 0x4>;
> + };
> +
> + wkup_pmx0: pinctrl@4301c000 {
> + compatible = "pinctrl-single";
> + /* Proxy 0 addressing */
> + reg = <0x00 0x4301c000 0x00 0x178>;
> + #pinctrl-cells = <1>;
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <0xffffffff>;
> + };
> +
> + mcu_ram: sram@41c00000 {
> + compatible = "mmio-sram";
> + reg = <0x00 0x41c00000 0x00 0x100000>;
> + ranges = <0x00 0x00 0x41c00000 0x100000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +
> + wkup_uart0: serial@42300000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x42300000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 287 2>;
> + clock-names = "fclk";
> + };
> +
> + mcu_uart0: serial@40a00000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x40a00000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <96000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 149 2>;
> + clock-names = "fclk";
> + };
> +
> + wkup_gpio_intr: interrupt-controller2 {
> + compatible = "ti,sci-intr";
> + ti,intr-trigger-type = <1>;
> + interrupt-controller;
> + interrupt-parent = <&gic500>;
> + #interrupt-cells = <1>;
> + ti,sci = <&dmsc>;
> + ti,sci-dev-id = <137>;
> + ti,interrupt-ranges = <16 960 16>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> new file mode 100644
> index 000000000000..66169bcf7c9a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> @@ -0,0 +1,172 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for J7200 SoC Family
> + *
> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/k3.h>
> +#include <dt-bindings/soc/ti,sci_pm_domain.h>
> +
> +/ {
> + model = "Texas Instruments K3 J7200 SoC";
> + compatible = "ti,j7200";
> + interrupt-parent = <&gic500>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = &wkup_uart0;
> + serial1 = &mcu_uart0;
> + serial2 = &main_uart0;
> + serial3 = &main_uart1;
> + serial4 = &main_uart2;
> + serial5 = &main_uart3;
> + serial6 = &main_uart4;
> + serial7 = &main_uart5;
> + serial8 = &main_uart6;
> + serial9 = &main_uart7;
> + serial10 = &main_uart8;
> + serial11 = &main_uart9;
> + };
> +
> + chosen { };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu-map {
> + cluster0: cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> + };
> +
> + };
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a72";
> + reg = <0x000>;
> + device_type = "cpu";
> + enable-method = "psci";
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a72";
> + reg = <0x001>;
> + device_type = "cpu";
> + enable-method = "psci";
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&L2_0>;
> + };
> + };
> +
> + L2_0: l2-cache0 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + next-level-cache = <&msmc_l3>;
> + };
> +
> + msmc_l3: l3-cache0 {
> + compatible = "cache";
> + cache-level = <3>;
> + };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> +
> + psci: psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> + };
> +
> + a72_timer0: timer-cl0-cpu0 {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
> + };
> +
> + pmu: pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + cbass_main: bus@100000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
> + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
> + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
> + <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
> + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
> + <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
> + <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
> + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
> +
> + /* MCUSS_WKUP Range */
> + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
> + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
> + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
> + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
> + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
> + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
> + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
> + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
> + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
> + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
> + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
> + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
> +
> + cbass_mcu_wakeup: bus@28380000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
> + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
> + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
> + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
> + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
> + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
> + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
> + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
> + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
> + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
> + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
> + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
> + };
> + };
> +};
> +
> +/* Now include the peripherals for each bus segments */
> +#include "k3-j7200-main.dtsi"
> +#include "k3-j7200-mcu-wakeup.dtsi"
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 1/5] arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs
2020-09-14 16:22 ` [PATCH v4 1/5] arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs Lokesh Vutla
@ 2020-09-15 15:28 ` Suman Anna
0 siblings, 0 replies; 22+ messages in thread
From: Suman Anna @ 2020-09-15 15:28 UTC (permalink / raw)
To: Lokesh Vutla, Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Sekhar Nori,
Linux ARM Mailing List, Kishon Vijay Abraham I
On 9/14/20 11:22 AM, Lokesh Vutla wrote:
> To allow lesser dependency and better maintainability use CONFIG_ARCH_K3
> for building dtbs for all K3 based devices. This is as per the
> discussion in [0].
>
> [0] https://lore.kernel.org/linux-arm-kernel/20200908112534.t5bgrjf7y3a6l2ss@akan/
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
regards
Suman
> ---
> arch/arm64/boot/dts/ti/Makefile | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 05c0bebf65d4..7f28be62b8da 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -3,9 +3,9 @@
> # Make file to build device tree binaries for boards based on
> # Texas Instruments Inc processors
> #
> -# Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
> +# Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
> #
>
> -dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
>
> -dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 3/5] dt-bindings: arm: ti: Add bindings for J7200 SoC
2020-09-14 16:22 ` [PATCH v4 3/5] dt-bindings: arm: ti: Add bindings for J7200 SoC Lokesh Vutla
@ 2020-09-15 15:28 ` Suman Anna
2020-09-22 23:41 ` Rob Herring
1 sibling, 0 replies; 22+ messages in thread
From: Suman Anna @ 2020-09-15 15:28 UTC (permalink / raw)
To: Lokesh Vutla, Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Sekhar Nori,
Linux ARM Mailing List, Kishon Vijay Abraham I
On 9/14/20 11:22 AM, Lokesh Vutla wrote:
> The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
> It is targeted for automotive gateway, vehicle compute systems,
> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
> The SoC aims to meet the complex processing needs of modern embedded
> products.
>
> Some highlights of this SoC are:
> * Dual Cortex-A72s in a single cluster, two clusters of lockstep
> capable dual Cortex-R5F MCUs and a Centralized Device Management and
> Security Controller (DMSC).
> * Configurable L3 Cache and IO-coherent architecture with high data
> throughput capable distributed DMA architecture under NAVSS.
> * Integrated Ethernet switch supporting up to a total of 4 external ports
> in addition to legacy Ethernet switch of up to 2 ports.
> * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
> 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
> I2C, eCAP/eQEP, eHRPWM among other peripherals.
> * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
> management.
>
> See J7200 Technical Reference Manual (SPRUIU1, June 2020)
> for further details: https://www.ti.com/lit/pdf/spruiu1
>
> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
regards
Suman
> ---
> Documentation/devicetree/bindings/arm/ti/k3.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> index c5e3e4aeda8e..829751209543 100644
> --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
> +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> @@ -28,4 +28,8 @@ properties:
> - description: K3 J721E SoC
> items:
> - const: ti,j721e
> +
> + - description: K3 J7200 SoC
> + items:
> + - const: ti,j7200
> ...
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema
2020-09-14 16:22 ` [PATCH v4 2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema Lokesh Vutla
@ 2020-09-15 15:31 ` Suman Anna
2020-09-22 23:41 ` Rob Herring
2020-09-28 16:51 ` Rob Herring
2 siblings, 0 replies; 22+ messages in thread
From: Suman Anna @ 2020-09-15 15:31 UTC (permalink / raw)
To: Lokesh Vutla, Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Sekhar Nori,
Linux ARM Mailing List, Kishon Vijay Abraham I
On 9/14/20 11:22 AM, Lokesh Vutla wrote:
> Convert TI K3 Board/SoC bindings to DT schema format.
>
> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
> .../devicetree/bindings/arm/ti/k3.txt | 26 ----------------
> .../devicetree/bindings/arm/ti/k3.yaml | 31 +++++++++++++++++++
> MAINTAINERS | 2 +-
> 3 files changed, 32 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/ti/k3.txt
> create mode 100644 Documentation/devicetree/bindings/arm/ti/k3.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt
> deleted file mode 100644
> index 333e7256126a..000000000000
> --- a/Documentation/devicetree/bindings/arm/ti/k3.txt
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -Texas Instruments K3 Multicore SoC architecture device tree bindings
> ---------------------------------------------------------------------
> -
> -Platforms based on Texas Instruments K3 Multicore SoC architecture
> -shall follow the following scheme:
> -
> -SoCs
> -----
> -
> -Each device tree root node must specify which exact SoC in K3 Multicore SoC
> -architecture it uses, using one of the following compatible values:
> -
> -- AM654
> - compatible = "ti,am654";
> -
> -- J721E
> - compatible = "ti,j721e";
> -
> -Boards
> -------
> -
> -In addition, each device tree root node must specify which one or more
> -of the following board-specific compatible values:
> -
> -- AM654 EVM
> - compatible = "ti,am654-evm", "ti,am654";
> diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> new file mode 100644
> index 000000000000..c5e3e4aeda8e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> @@ -0,0 +1,31 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/ti/k3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Texas Instruments K3 Multicore SoC architecture device tree bindings
> +
> +maintainers:
> + - Nishanth Menon <nm@ti.com>
> +
> +description: |
> + Platforms based on Texas Instruments K3 Multicore SoC architecture
> + shall have the following properties.
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> +
> + - description: K3 AM654 SoC
> + items:
> + - enum:
> + - ti,am654-evm
I am guessing the enum is for adding other vendors compatibles when they get
added in the future. Otherwise, const would have sufficed. So, looks ok.
Reviewed-by: Suman Anna <s-anna@ti.com>
regards
Suman
> + - const: ti,am654
> +
> + - description: K3 J721E SoC
> + items:
> + - const: ti,j721e
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e4647c84c987..076fae9aa75b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2636,7 +2636,7 @@ M: Tero Kristo <t-kristo@ti.com>
> M: Nishanth Menon <nm@ti.com>
> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> S: Supported
> -F: Documentation/devicetree/bindings/arm/ti/k3.txt
> +F: Documentation/devicetree/bindings/arm/ti/k3.yaml
> F: arch/arm64/boot/dts/ti/Makefile
> F: arch/arm64/boot/dts/ti/k3-*
> F: include/dt-bindings/pinctrl/k3.h
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 5/5] arm64: dts: ti: Add support for J7200 Common Processor Board
2020-09-14 16:22 ` [PATCH v4 5/5] arm64: dts: ti: Add support for J7200 Common Processor Board Lokesh Vutla
@ 2020-09-15 15:33 ` Suman Anna
2020-09-16 1:15 ` Nishanth Menon
0 siblings, 1 reply; 22+ messages in thread
From: Suman Anna @ 2020-09-15 15:33 UTC (permalink / raw)
To: Lokesh Vutla, Nishanth Menon, Tero Kristo, Rob Herring
Cc: Device Tree Mailing List, Grygorii Strashko, Sekhar Nori,
Linux ARM Mailing List, Kishon Vijay Abraham I
On 9/14/20 11:22 AM, Lokesh Vutla wrote:
> Add support for J7200 Common Processor Board.
> The EVM architecture is very similar to J721E as follows:
>
> +------------------------------------------------------+
> | +-------------------------------------------+ |
> | | | |
> | | Add-on Card 1 Options | |
> | | | |
> | +-------------------------------------------+ |
> | |
> | |
> | +-------------------+ |
> | | | |
> | | SOM | |
> | +--------------+ | | |
> | | | | | |
> | | Add-on | +-------------------+ |
> | | Card 2 | | Power Supply
> | | Options | | |
> | | | | |
> | +--------------+ | <---
> +------------------------------------------------------+
> Common Processor Board
>
> Common Processor board is the baseboard that has most of the actual
> connectors, power supply etc. A SOM (System on Module) is plugged on
> to the common processor board and this contains the SoC, PMIC, DDR and
> basic high speed components necessary for functionality.
>
> Note:
> * The minimum configuration required to boot up the board is System On
> Module(SOM) + Common Processor Board.
> * Since there is just a single SOM and Common Processor Board, we are
> maintaining common processor board as the base dts and SOM as the dtsi
> that we include. In the future as more SOM's appear, we should move
> common processor board as a dtsi and include configurations as dts.
> * All daughter cards beyond the basic boards shall be maintained as
> overlays.
>
> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---
> arch/arm64/boot/dts/ti/Makefile | 2 +
> .../dts/ti/k3-j7200-common-proc-board.dts | 64 +++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 29 +++++++++
> 3 files changed, 95 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 7f28be62b8da..65506f21ba30 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -9,3 +9,5 @@
> dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
>
> dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
> +
> +dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> new file mode 100644
> index 000000000000..e27069317c4e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -0,0 +1,64 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-j7200-som-p0.dtsi"
> +
> +/ {
> + chosen {
> + stdout-path = "serial2:115200n8";
> + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
> + };
> +};
> +
> +&wkup_uart0 {
> + /* Wakeup UART is used by System firmware */
> + status = "disabled";
> +};
> +
> +&main_uart0 {
> + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
Perhaps a comment here to explain why this is being overwritten to use
PD_SHARED. I don't see anything in the Changelog either.
Otherwise, looks good.
regards
Suman
> +};
> +
> +&main_uart2 {
> + /* MAIN UART 2 is used by R5F firmware */
> + status = "disabled";
> +};
> +
> +&main_uart3 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart4 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart5 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart6 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart7 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart8 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart9 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> new file mode 100644
> index 000000000000..f7e271c442a0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-j7200.dtsi"
> +
> +/ {
> + memory@80000000 {
> + device_type = "memory";
> + /* 4G RAM */
> + reg = <0x00 0x80000000 0x00 0x80000000>,
> + <0x08 0x80000000 0x00 0x80000000>;
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + secure_ddr: optee@9e800000 {
> + reg = <0x00 0x9e800000 0x00 0x01800000>;
> + alignment = <0x1000>;
> + no-map;
> + };
> + };
> +};
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 5/5] arm64: dts: ti: Add support for J7200 Common Processor Board
2020-09-15 15:33 ` Suman Anna
@ 2020-09-16 1:15 ` Nishanth Menon
2020-09-16 3:05 ` Suman Anna
0 siblings, 1 reply; 22+ messages in thread
From: Nishanth Menon @ 2020-09-16 1:15 UTC (permalink / raw)
To: Suman Anna
Cc: Device Tree Mailing List, Grygorii Strashko, Lokesh Vutla,
Sekhar Nori, Kishon Vijay Abraham I, Tero Kristo, Rob Herring,
Linux ARM Mailing List
On 10:33-20200915, Suman Anna wrote:
> On 9/14/20 11:22 AM, Lokesh Vutla wrote:
> > Add support for J7200 Common Processor Board.
> > The EVM architecture is very similar to J721E as follows:
> >
> > +------------------------------------------------------+
> > | +-------------------------------------------+ |
> > | | | |
> > | | Add-on Card 1 Options | |
> > | | | |
> > | +-------------------------------------------+ |
> > | |
> > | |
> > | +-------------------+ |
> > | | | |
> > | | SOM | |
> > | +--------------+ | | |
> > | | | | | |
> > | | Add-on | +-------------------+ |
> > | | Card 2 | | Power Supply
> > | | Options | | |
> > | | | | |
> > | +--------------+ | <---
> > +------------------------------------------------------+
> > Common Processor Board
> >
> > Common Processor board is the baseboard that has most of the actual
> > connectors, power supply etc. A SOM (System on Module) is plugged on
> > to the common processor board and this contains the SoC, PMIC, DDR and
> > basic high speed components necessary for functionality.
> >
> > Note:
> > * The minimum configuration required to boot up the board is System On
> > Module(SOM) + Common Processor Board.
> > * Since there is just a single SOM and Common Processor Board, we are
> > maintaining common processor board as the base dts and SOM as the dtsi
> > that we include. In the future as more SOM's appear, we should move
> > common processor board as a dtsi and include configurations as dts.
> > * All daughter cards beyond the basic boards shall be maintained as
> > overlays.
> >
> > Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
> > Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> > Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> > ---
> > arch/arm64/boot/dts/ti/Makefile | 2 +
> > .../dts/ti/k3-j7200-common-proc-board.dts | 64 +++++++++++++++++++
> > arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 29 +++++++++
> > 3 files changed, 95 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> > create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> > index 7f28be62b8da..65506f21ba30 100644
> > --- a/arch/arm64/boot/dts/ti/Makefile
> > +++ b/arch/arm64/boot/dts/ti/Makefile
> > @@ -9,3 +9,5 @@
> > dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
> >
> > dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
> > +
> > +dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
> > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> > new file mode 100644
> > index 000000000000..e27069317c4e
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> > @@ -0,0 +1,64 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "k3-j7200-som-p0.dtsi"
> > +
> > +/ {
> > + chosen {
> > + stdout-path = "serial2:115200n8";
> > + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
> > + };
> > +};
> > +
> > +&wkup_uart0 {
> > + /* Wakeup UART is used by System firmware */
> > + status = "disabled";
> > +};
> > +
> > +&main_uart0 {
> > + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
>
> Perhaps a comment here to explain why this is being overwritten to use
> PD_SHARED. I don't see anything in the Changelog either.
Shared with ATF on this platform -> I can add this comment on applying.
>
> Otherwise, looks good.
Would that be a reviewed-by?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 5/5] arm64: dts: ti: Add support for J7200 Common Processor Board
2020-09-16 1:15 ` Nishanth Menon
@ 2020-09-16 3:05 ` Suman Anna
0 siblings, 0 replies; 22+ messages in thread
From: Suman Anna @ 2020-09-16 3:05 UTC (permalink / raw)
To: Nishanth Menon
Cc: Device Tree Mailing List, Grygorii Strashko, Lokesh Vutla,
Sekhar Nori, Kishon Vijay Abraham I, Tero Kristo, Rob Herring,
Linux ARM Mailing List
On 9/15/20 8:15 PM, Nishanth Menon wrote:
> On 10:33-20200915, Suman Anna wrote:
>> On 9/14/20 11:22 AM, Lokesh Vutla wrote:
>>> Add support for J7200 Common Processor Board.
>>> The EVM architecture is very similar to J721E as follows:
>>>
>>> +------------------------------------------------------+
>>> | +-------------------------------------------+ |
>>> | | | |
>>> | | Add-on Card 1 Options | |
>>> | | | |
>>> | +-------------------------------------------+ |
>>> | |
>>> | |
>>> | +-------------------+ |
>>> | | | |
>>> | | SOM | |
>>> | +--------------+ | | |
>>> | | | | | |
>>> | | Add-on | +-------------------+ |
>>> | | Card 2 | | Power Supply
>>> | | Options | | |
>>> | | | | |
>>> | +--------------+ | <---
>>> +------------------------------------------------------+
>>> Common Processor Board
>>>
>>> Common Processor board is the baseboard that has most of the actual
>>> connectors, power supply etc. A SOM (System on Module) is plugged on
>>> to the common processor board and this contains the SoC, PMIC, DDR and
>>> basic high speed components necessary for functionality.
>>>
>>> Note:
>>> * The minimum configuration required to boot up the board is System On
>>> Module(SOM) + Common Processor Board.
>>> * Since there is just a single SOM and Common Processor Board, we are
>>> maintaining common processor board as the base dts and SOM as the dtsi
>>> that we include. In the future as more SOM's appear, we should move
>>> common processor board as a dtsi and include configurations as dts.
>>> * All daughter cards beyond the basic boards shall be maintained as
>>> overlays.
>>>
>>> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
>>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
>>> ---
>>> arch/arm64/boot/dts/ti/Makefile | 2 +
>>> .../dts/ti/k3-j7200-common-proc-board.dts | 64 +++++++++++++++++++
>>> arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 29 +++++++++
>>> 3 files changed, 95 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
>>> index 7f28be62b8da..65506f21ba30 100644
>>> --- a/arch/arm64/boot/dts/ti/Makefile
>>> +++ b/arch/arm64/boot/dts/ti/Makefile
>>> @@ -9,3 +9,5 @@
>>> dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
>>>
>>> dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
>>> +
>>> +dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
>>> new file mode 100644
>>> index 000000000000..e27069317c4e
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
>>> @@ -0,0 +1,64 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include "k3-j7200-som-p0.dtsi"
>>> +
>>> +/ {
>>> + chosen {
>>> + stdout-path = "serial2:115200n8";
>>> + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
>>> + };
>>> +};
>>> +
>>> +&wkup_uart0 {
>>> + /* Wakeup UART is used by System firmware */
>>> + status = "disabled";
>>> +};
>>> +
>>> +&main_uart0 {
>>> + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
>>
>> Perhaps a comment here to explain why this is being overwritten to use
>> PD_SHARED. I don't see anything in the Changelog either.
> Shared with ATF on this platform -> I can add this comment on applying.
>>
>> Otherwise, looks good.
>
> Would that be a reviewed-by?
>
Yes, with the comment added,
Reviewed-by: Suman Anna <s-anna@ti.com>
regards
Suman
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema
2020-09-14 16:22 ` [PATCH v4 2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema Lokesh Vutla
2020-09-15 15:31 ` Suman Anna
@ 2020-09-22 23:41 ` Rob Herring
2020-09-28 16:51 ` Rob Herring
2 siblings, 0 replies; 22+ messages in thread
From: Rob Herring @ 2020-09-22 23:41 UTC (permalink / raw)
To: Lokesh Vutla
Cc: Nishanth Menon, Device Tree Mailing List, Grygorii Strashko,
Sekhar Nori, Kishon Vijay Abraham I, Tero Kristo, Rob Herring,
Linux ARM Mailing List
On Mon, 14 Sep 2020 21:52:28 +0530, Lokesh Vutla wrote:
> Convert TI K3 Board/SoC bindings to DT schema format.
>
> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
> .../devicetree/bindings/arm/ti/k3.txt | 26 ----------------
> .../devicetree/bindings/arm/ti/k3.yaml | 31 +++++++++++++++++++
> MAINTAINERS | 2 +-
> 3 files changed, 32 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/ti/k3.txt
> create mode 100644 Documentation/devicetree/bindings/arm/ti/k3.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 3/5] dt-bindings: arm: ti: Add bindings for J7200 SoC
2020-09-14 16:22 ` [PATCH v4 3/5] dt-bindings: arm: ti: Add bindings for J7200 SoC Lokesh Vutla
2020-09-15 15:28 ` Suman Anna
@ 2020-09-22 23:41 ` Rob Herring
1 sibling, 0 replies; 22+ messages in thread
From: Rob Herring @ 2020-09-22 23:41 UTC (permalink / raw)
To: Lokesh Vutla
Cc: Nishanth Menon, Device Tree Mailing List, Grygorii Strashko,
Sekhar Nori, Kishon Vijay Abraham I, Tero Kristo, Rob Herring,
Linux ARM Mailing List
On Mon, 14 Sep 2020 21:52:29 +0530, Lokesh Vutla wrote:
> The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
> It is targeted for automotive gateway, vehicle compute systems,
> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
> The SoC aims to meet the complex processing needs of modern embedded
> products.
>
> Some highlights of this SoC are:
> * Dual Cortex-A72s in a single cluster, two clusters of lockstep
> capable dual Cortex-R5F MCUs and a Centralized Device Management and
> Security Controller (DMSC).
> * Configurable L3 Cache and IO-coherent architecture with high data
> throughput capable distributed DMA architecture under NAVSS.
> * Integrated Ethernet switch supporting up to a total of 4 external ports
> in addition to legacy Ethernet switch of up to 2 ports.
> * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
> 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
> I2C, eCAP/eQEP, eHRPWM among other peripherals.
> * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
> management.
>
> See J7200 Technical Reference Manual (SPRUIU1, June 2020)
> for further details: https://www.ti.com/lit/pdf/spruiu1
>
> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
> Documentation/devicetree/bindings/arm/ti/k3.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform
2020-09-14 16:22 [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform Lokesh Vutla
` (5 preceding siblings ...)
2020-09-15 11:35 ` [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform Nishanth Menon
@ 2020-09-23 14:24 ` Nishanth Menon
6 siblings, 0 replies; 22+ messages in thread
From: Nishanth Menon @ 2020-09-23 14:24 UTC (permalink / raw)
To: Rob Herring, Lokesh Vutla, Tero Kristo
Cc: Nishanth Menon, Device Tree Mailing List, Grygorii Strashko,
Sekhar Nori, Kishon Vijay Abraham I, Linux ARM Mailing List
On Mon, 14 Sep 2020 21:52:26 +0530, Lokesh Vutla wrote:
> This series adds initial support for latest new SoC, J7200, from Texas Instruments.
>
> The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
> It is targeted for for automotive gateway, vehicle compute systems,
> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
> The SoC aims to meet the complex processing needs of modern embedded products.
>
> [...]
Hi Lokesh Vutla,
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/5] arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs
commit: 21bb8c83c94923f1f996e1cb57c4744ea1163eed
[2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema
commit: 66e06509aa37bcf089ce341ec9c027922f105155
[3/5] dt-bindings: arm: ti: Add bindings for J7200 SoC
commit: 214b0eb35e55d9d726ad02ffec62f087c09864fb
[4/5] arm64: dts: ti: Add support for J7200 SoC
commit: d361ed88455feae5f7e555828b0d8104588cc53d
[5/5] arm64: dts: ti: Add support for J7200 Common Processor Board
commit: 26bd3f312c2ece0e8860c80fc64a112df5a620c6
NOTE: I have edited the patch to address the trivial comment
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema
2020-09-14 16:22 ` [PATCH v4 2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema Lokesh Vutla
2020-09-15 15:31 ` Suman Anna
2020-09-22 23:41 ` Rob Herring
@ 2020-09-28 16:51 ` Rob Herring
2020-09-30 12:15 ` Nishanth Menon
2 siblings, 1 reply; 22+ messages in thread
From: Rob Herring @ 2020-09-28 16:51 UTC (permalink / raw)
To: Lokesh Vutla, Suman Anna
Cc: Nishanth Menon, Device Tree Mailing List, Grygorii Strashko,
Sekhar Nori, Kishon Vijay Abraham I, Tero Kristo,
Linux ARM Mailing List
On Mon, Sep 14, 2020 at 11:22 AM Lokesh Vutla <lokeshvutla@ti.com> wrote:
>
> Convert TI K3 Board/SoC bindings to DT schema format.
>
> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
> .../devicetree/bindings/arm/ti/k3.txt | 26 ----------------
> .../devicetree/bindings/arm/ti/k3.yaml | 31 +++++++++++++++++++
> MAINTAINERS | 2 +-
> 3 files changed, 32 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/ti/k3.txt
> create mode 100644 Documentation/devicetree/bindings/arm/ti/k3.yaml
This causes warnings in ti,omap-hwspinlock.yaml which also landed for 5.10:
/builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.example.dt.yaml:
/: compatible: ['ti,am654'] is not valid under any of the given
schemas (Possible causes of the failure):
/builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.example.dt.yaml:
/: compatible: ['ti,am654'] is too short
/builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.example.dt.yaml:
/: compatible:0: 'ti,am654' is not one of ['ti,am654-evm']
/builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.example.dt.yaml:
/: compatible:0: 'ti,j721e' was expected
/builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.example.dt.yaml:
/: compatible:0: 'ti,j7200' was expected
From schema: /builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/arm/ti/k3.yaml
Please fix. I'd suggest just removing part of the example. It's not relevant.
Rob
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v4 2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema
2020-09-28 16:51 ` Rob Herring
@ 2020-09-30 12:15 ` Nishanth Menon
0 siblings, 0 replies; 22+ messages in thread
From: Nishanth Menon @ 2020-09-30 12:15 UTC (permalink / raw)
To: g
Cc: Device Tree Mailing List, Grygorii Strashko, Lokesh Vutla,
Sekhar Nori, Kishon Vijay Abraham I, Tero Kristo,
bjorn.andersson, Linux ARM Mailing List
On 11:51-20200928, Rob Herring wrote:
> On Mon, Sep 14, 2020 at 11:22 AM Lokesh Vutla <lokeshvutla@ti.com> wrote:
> >
> > Convert TI K3 Board/SoC bindings to DT schema format.
> >
> > Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
> > Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> > ---
> > .../devicetree/bindings/arm/ti/k3.txt | 26 ----------------
> > .../devicetree/bindings/arm/ti/k3.yaml | 31 +++++++++++++++++++
> > MAINTAINERS | 2 +-
> > 3 files changed, 32 insertions(+), 27 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/arm/ti/k3.txt
> > create mode 100644 Documentation/devicetree/bindings/arm/ti/k3.yaml
>
> This causes warnings in ti,omap-hwspinlock.yaml which also landed for 5.10:
>
> /builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.example.dt.yaml:
> /: compatible: ['ti,am654'] is not valid under any of the given
> schemas (Possible causes of the failure):
> /builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.example.dt.yaml:
> /: compatible: ['ti,am654'] is too short
> /builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.example.dt.yaml:
> /: compatible:0: 'ti,am654' is not one of ['ti,am654-evm']
> /builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.example.dt.yaml:
> /: compatible:0: 'ti,j721e' was expected
> /builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.example.dt.yaml:
> /: compatible:0: 'ti,j7200' was expected
>
> From schema: /builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/arm/ti/k3.yaml
>
> Please fix. I'd suggest just removing part of the example. It's not relevant.
I think this is addressed by [1]
[1] https://lore.kernel.org/linux-arm-kernel/20200928225155.12432-1-s-anna@ti.com/
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2020-09-30 12:16 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-14 16:22 [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform Lokesh Vutla
2020-09-14 16:22 ` [PATCH v4 1/5] arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs Lokesh Vutla
2020-09-15 15:28 ` Suman Anna
2020-09-14 16:22 ` [PATCH v4 2/5] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema Lokesh Vutla
2020-09-15 15:31 ` Suman Anna
2020-09-22 23:41 ` Rob Herring
2020-09-28 16:51 ` Rob Herring
2020-09-30 12:15 ` Nishanth Menon
2020-09-14 16:22 ` [PATCH v4 3/5] dt-bindings: arm: ti: Add bindings for J7200 SoC Lokesh Vutla
2020-09-15 15:28 ` Suman Anna
2020-09-22 23:41 ` Rob Herring
2020-09-14 16:22 ` [PATCH v4 4/5] arm64: dts: ti: Add support " Lokesh Vutla
2020-09-15 5:09 ` Vignesh Raghavendra
2020-09-15 11:34 ` Nishanth Menon
2020-09-15 11:36 ` Vignesh Raghavendra
2020-09-15 12:11 ` Kishon Vijay Abraham I
2020-09-14 16:22 ` [PATCH v4 5/5] arm64: dts: ti: Add support for J7200 Common Processor Board Lokesh Vutla
2020-09-15 15:33 ` Suman Anna
2020-09-16 1:15 ` Nishanth Menon
2020-09-16 3:05 ` Suman Anna
2020-09-15 11:35 ` [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform Nishanth Menon
2020-09-23 14:24 ` Nishanth Menon
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