* [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform
@ 2020-11-25 5:20 Dave Gerlach
2020-11-25 5:20 ` [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM642 SoC Dave Gerlach
` (3 more replies)
0 siblings, 4 replies; 16+ messages in thread
From: Dave Gerlach @ 2020-11-25 5:20 UTC (permalink / raw)
To: Rob Herring, Nishanth Menon
Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Peter Ujfalusi, Lokesh Vutla,
Aswath Govindraju, Suman Anna, linux-arm-kernel
This series adds initial support for the latest new SoC, AM642,
from Texas Instruments.
Additional detail can be found in the patch descriptions, also
see AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for
further details: https://www.ti.com/lit/pdf/spruim2
Regards,
Dave
Dave Gerlach (3):
dt-bindings: arm: ti: Add bindings for AM642 SoC
arm64: dts: ti: Add Support for AM642 SoC
arm64: dts: ti: Add support for AM642 EVM
.../devicetree/bindings/arm/ti/k3.yaml | 6 +
arch/arm64/boot/dts/ti/Makefile | 2 +
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 178 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 95 ++++++++++
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 61 ++++++
arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++++
6 files changed, 407 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM642 SoC 2020-11-25 5:20 [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform Dave Gerlach @ 2020-11-25 5:20 ` Dave Gerlach 2020-12-08 16:03 ` Rob Herring 2020-11-25 5:20 ` [PATCH 2/3] arm64: dts: ti: Add Support " Dave Gerlach ` (2 subsequent siblings) 3 siblings, 1 reply; 16+ messages in thread From: Dave Gerlach @ 2020-11-25 5:20 UTC (permalink / raw) To: Rob Herring, Nishanth Menon Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Peter Ujfalusi, Lokesh Vutla, Aswath Govindraju, Suman Anna, linux-arm-kernel The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Dave Gerlach <d-gerlach@ti.com> --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index c6e1c1e63e43..393f94a64f8d 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -33,6 +33,12 @@ properties: items: - const: ti,j7200 + - description: K3 AM642 SoC + items: + - enum: + - ti,am642-evm + - const: ti,am642 + additionalProperties: true ... -- 2.28.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM642 SoC 2020-11-25 5:20 ` [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM642 SoC Dave Gerlach @ 2020-12-08 16:03 ` Rob Herring 0 siblings, 0 replies; 16+ messages in thread From: Rob Herring @ 2020-12-08 16:03 UTC (permalink / raw) To: Dave Gerlach Cc: Nishanth Menon, devicetree, Vignesh Raghavendra, Lokesh Vutla, Sekhar Nori, Kishon Vijay Abraham, Peter Ujfalusi, Tony Lindgren, Rob Herring, Aswath Govindraju, linux-arm-kernel On Tue, 24 Nov 2020 23:20:02 -0600, Dave Gerlach wrote: > The AM642 SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration to enable applications such as > Motor Drives, PLC, Remote IO and IoT Gateways. > > Some highlights of this SoC are: > * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F > MCUs, and a single Cortex-M4F. > * Two Gigabit Industrial Communication Subsystems (ICSSG). > * Integrated Ethernet switch supporting up to a total of two external > ports. > * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory > controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other > peripherals. > * Centralized System Controller for Security, Power, and Resource > Management (DMSC). > > See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) > for further details: https://www.ti.com/lit/pdf/spruim2 > > Signed-off-by: Dave Gerlach <d-gerlach@ti.com> > --- > Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/3] arm64: dts: ti: Add Support for AM642 SoC 2020-11-25 5:20 [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform Dave Gerlach 2020-11-25 5:20 ` [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM642 SoC Dave Gerlach @ 2020-11-25 5:20 ` Dave Gerlach 2020-12-03 21:56 ` Suman Anna ` (2 more replies) 2020-11-25 5:20 ` [PATCH 3/3] arm64: dts: ti: Add support for AM642 EVM Dave Gerlach 2020-11-27 12:40 ` [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform Peter Ujfalusi 3 siblings, 3 replies; 16+ messages in thread From: Dave Gerlach @ 2020-11-25 5:20 UTC (permalink / raw) To: Rob Herring, Nishanth Menon Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Peter Ujfalusi, Lokesh Vutla, Aswath Govindraju, Suman Anna, linux-arm-kernel The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable minimal ramdisk boot. Introduce a limited set of MAIN domain periperhals under cbass_main and a placeholder cbass_mcu node for future MCU domain usage. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 178 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am64.dtsi | 95 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++++++ 3 files changed, 338 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi new file mode 100644 index 000000000000..4830a8e4d89b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM642 SoC Family Main Domain peripherals + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01840000 0x00 0xC0000>; /* GICR */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + dmss { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges; + + secure_proxy_main: mailbox@4d000000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + interrupt-names = "rx_012"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + dmsc: dmsc { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clocks { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + main_pmx0: pinctrl@f4000 { + compatible = "pinctrl-single"; + reg = <0x00 0xf4000 0x00 0x2e4>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + chipid@43000014 { + compatible = "ti,am654-chipid"; + reg = <0x00 0x43000014 0x00 0x4>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>; + clock-names = "fclk"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 154 0>; + clock-names = "fclk"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 155 0>; + clock-names = "fclk"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>; + clock-names = "fclk"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>; + clock-names = "fclk"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi new file mode 100644 index 000000000000..0637cf9ede5f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM642 SoC Family + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/k3.h> +#include <dt-bindings/soc/ti,sci_pm_domain.h> + +/ { + model = "Texas Instruments K3 AM642 SoC"; + compatible = "ti,am642"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + serial5 = &main_uart3; + serial6 = &main_uart4; + serial7 = &main_uart5; + serial8 = &main_uart6; + }; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + cbass_main: bus@f4000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ + <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */ + <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */ + <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */ + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ + <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */ + <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ + <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002e4>, /* PINCTRL */ + <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ + <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am64-main.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi new file mode 100644 index 000000000000..b30f239e84f1 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM642 SoC family in Dual core configuration + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am64.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; -- 2.28.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] arm64: dts: ti: Add Support for AM642 SoC 2020-11-25 5:20 ` [PATCH 2/3] arm64: dts: ti: Add Support " Dave Gerlach @ 2020-12-03 21:56 ` Suman Anna 2020-12-03 22:00 ` Suman Anna 2020-12-04 13:17 ` Grygorii Strashko 2021-01-05 7:19 ` Vignesh Raghavendra 2 siblings, 1 reply; 16+ messages in thread From: Suman Anna @ 2020-12-03 21:56 UTC (permalink / raw) To: Dave Gerlach, Rob Herring, Nishanth Menon Cc: devicetree, Vignesh Raghavendra, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Peter Ujfalusi, Lokesh Vutla, Aswath Govindraju, linux-arm-kernel Hi Dave, On 11/24/20 11:20 PM, Dave Gerlach wrote: > The AM642 SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration to enable applications such as > Motor Drives, PLC, Remote IO and IoT Gateways. > > Some highlights of this SoC are: > * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F > MCUs, and a single Cortex-M4F. > * Two Gigabit Industrial Communication Subsystems (ICSSG). > * Integrated Ethernet switch supporting up to a total of two external > ports. > * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory > controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other > peripherals. > * Centralized System Controller for Security, Power, and Resource > Management (DMSC). > > See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) > for further details: https://www.ti.com/lit/pdf/spruim2 > > Introduce basic support for the AM642 SoC to enable minimal > ramdisk boot. Introduce a limited set of MAIN domain periperhals > under cbass_main and a placeholder cbass_mcu node for future MCU > domain usage. > > Signed-off-by: Dave Gerlach <d-gerlach@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 178 +++++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am64.dtsi | 95 ++++++++++++ > arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++++++ > 3 files changed, 338 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi > > diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi > new file mode 100644 > index 000000000000..4830a8e4d89b > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi > @@ -0,0 +1,178 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for AM642 SoC Family Main Domain peripherals > + * > + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +&cbass_main { > + gic500: interrupt-controller@1800000 { > + compatible = "arm,gic-v3"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ > + <0x00 0x01840000 0x00 0xC0000>; /* GICR */ > + /* > + * vcpumntirq: > + * virtual CPU interface maintenance interrupt > + */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gic_its: msi-controller@1820000 { > + compatible = "arm,gic-v3-its"; > + reg = <0x00 0x01820000 0x00 0x10000>; > + socionext,synquacer-pre-its = <0x1000000 0x400000>; > + msi-controller; > + #msi-cells = <1>; > + }; > + }; > + > + dmss { > + compatible = "simple-mfd"; > + #address-cells = <2>; > + #size-cells = <2>; > + dma-ranges; > + ranges; > + > + secure_proxy_main: mailbox@4d000000 { > + compatible = "ti,am654-secure-proxy"; > + #mbox-cells = <1>; > + reg-names = "target_data", "rt", "scfg"; > + reg = <0x00 0x4d000000 0x00 0x80000>, > + <0x00 0x4a600000 0x00 0x80000>, > + <0x00 0x4a400000 0x00 0x80000>; > + interrupt-names = "rx_012"; > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + dmsc: dmsc { > + compatible = "ti,k2g-sci"; > + ti,host-id = <12>; > + mbox-names = "rx", "tx"; > + mboxes= <&secure_proxy_main 12>, > + <&secure_proxy_main 13>; > + > + k3_pds: power-controller { > + compatible = "ti,sci-pm-domain"; > + #power-domain-cells = <2>; > + }; > + > + k3_clks: clocks { > + compatible = "ti,k2g-sci-clk"; > + #clock-cells = <2>; > + }; > + > + k3_reset: reset-controller { > + compatible = "ti,sci-reset"; > + #reset-cells = <2>; > + }; > + }; > + > + main_pmx0: pinctrl@f4000 { > + compatible = "pinctrl-single"; > + reg = <0x00 0xf4000 0x00 0x2e4>; > + #pinctrl-cells = <1>; > + pinctrl-single,register-width = <32>; > + pinctrl-single,function-mask = <0xffffffff>; > + }; > + > + chipid@43000014 { > + compatible = "ti,am654-chipid"; > + reg = <0x00 0x43000014 0x00 0x4>; > + }; > + > + main_uart0: serial@2800000 { > + compatible = "ti,am64-uart", "ti,am654-uart"; > + reg = <0x00 0x02800000 0x00 0x100>; > + reg-shift = <2>; > + reg-io-width = <4>; > + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <48000000>; > + current-speed = <115200>; > + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 146 0>; > + clock-names = "fclk"; > + }; > + > + main_uart1: serial@2810000 { > + compatible = "ti,am64-uart", "ti,am654-uart"; > + reg = <0x00 0x02810000 0x00 0x100>; > + reg-shift = <2>; > + reg-io-width = <4>; > + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <48000000>; > + current-speed = <115200>; > + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 152 0>; > + clock-names = "fclk"; > + }; > + > + main_uart2: serial@2820000 { > + compatible = "ti,am64-uart", "ti,am654-uart"; > + reg = <0x00 0x02820000 0x00 0x100>; > + reg-shift = <2>; > + reg-io-width = <4>; > + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <48000000>; > + current-speed = <115200>; > + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 153 0>; > + clock-names = "fclk"; > + }; > + > + main_uart3: serial@2830000 { > + compatible = "ti,am64-uart", "ti,am654-uart"; > + reg = <0x00 0x02830000 0x00 0x100>; > + reg-shift = <2>; > + reg-io-width = <4>; > + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <48000000>; > + current-speed = <115200>; > + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 154 0>; > + clock-names = "fclk"; > + }; > + > + main_uart4: serial@2840000 { > + compatible = "ti,am64-uart", "ti,am654-uart"; > + reg = <0x00 0x02840000 0x00 0x100>; > + reg-shift = <2>; > + reg-io-width = <4>; > + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <48000000>; > + current-speed = <115200>; > + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 155 0>; > + clock-names = "fclk"; > + }; > + > + main_uart5: serial@2850000 { > + compatible = "ti,am64-uart", "ti,am654-uart"; > + reg = <0x00 0x02850000 0x00 0x100>; > + reg-shift = <2>; > + reg-io-width = <4>; > + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <48000000>; > + current-speed = <115200>; > + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 156 0>; > + clock-names = "fclk"; > + }; > + > + main_uart6: serial@2860000 { > + compatible = "ti,am64-uart", "ti,am654-uart"; > + reg = <0x00 0x02860000 0x00 0x100>; > + reg-shift = <2>; > + reg-io-width = <4>; > + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <48000000>; > + current-speed = <115200>; > + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 158 0>; > + clock-names = "fclk"; > + }; > +}; > diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi > new file mode 100644 > index 000000000000..0637cf9ede5f > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi > @@ -0,0 +1,95 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for AM642 SoC Family > + * > + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/k3.h> > +#include <dt-bindings/soc/ti,sci_pm_domain.h> > + > +/ { > + model = "Texas Instruments K3 AM642 SoC"; > + compatible = "ti,am642"; > + interrupt-parent = <&gic500>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial2 = &main_uart0; > + serial3 = &main_uart1; > + serial4 = &main_uart2; > + serial5 = &main_uart3; > + serial6 = &main_uart4; > + serial7 = &main_uart5; > + serial8 = &main_uart6; > + }; > + > + chosen { }; > + > + firmware { > + optee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + }; > + > + psci: psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + }; > + > + a53_timer0: timer-cl0-cpu0 { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ > + }; > + > + pmu: pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + cbass_main: bus@f4000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ > + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ > + <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ > + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ > + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ > + <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ > + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ > + <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */ > + <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */ > + <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */ > + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ > + <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */ > + <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */ > + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */ > + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */ > + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ > + <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002e4>, /* PINCTRL */ Can you move this to the top, so that all these are in increasing memory order? > + <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ > + <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ > + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ This is atleast missing the ranges for On-Chip SRAM and the R5FSS, but those can always be added incrementally as well. Also, is there a reason for using these ranges a bit more granular compared to the earlier SoCs? regards Suman > + > + /* MCU Domain Range */ > + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; > + > + cbass_mcu: bus@4000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ > + }; > + }; > +}; > + > +/* Now include the peripherals for each bus segments */ > +#include "k3-am64-main.dtsi" > diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi > new file mode 100644 > index 000000000000..b30f239e84f1 > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi > @@ -0,0 +1,65 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for AM642 SoC family in Dual core configuration > + * > + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +/dts-v1/; > + > +#include "k3-am64.dtsi" > + > +/ { > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0: cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + > + core1 { > + cpu = <&cpu1>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a53"; > + reg = <0x000>; > + device_type = "cpu"; > + enable-method = "psci"; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&L2_0>; > + }; > + > + cpu1: cpu@1 { > + compatible = "arm,cortex-a53"; > + reg = <0x001>; > + device_type = "cpu"; > + enable-method = "psci"; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&L2_0>; > + }; > + }; > + > + L2_0: l2-cache0 { > + compatible = "cache"; > + cache-level = <2>; > + cache-size = <0x40000>; > + cache-line-size = <64>; > + cache-sets = <512>; > + }; > +}; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] arm64: dts: ti: Add Support for AM642 SoC 2020-12-03 21:56 ` Suman Anna @ 2020-12-03 22:00 ` Suman Anna 2021-01-05 4:02 ` Dave Gerlach 0 siblings, 1 reply; 16+ messages in thread From: Suman Anna @ 2020-12-03 22:00 UTC (permalink / raw) To: Dave Gerlach, Rob Herring, Nishanth Menon Cc: devicetree, Vignesh Raghavendra, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Peter Ujfalusi, Lokesh Vutla, Aswath Govindraju, linux-arm-kernel On 12/3/20 3:56 PM, Suman Anna wrote: > Hi Dave, > > On 11/24/20 11:20 PM, Dave Gerlach wrote: >> The AM642 SoC belongs to the K3 Multicore SoC architecture platform, >> providing advanced system integration to enable applications such as >> Motor Drives, PLC, Remote IO and IoT Gateways. >> >> Some highlights of this SoC are: >> * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F >> MCUs, and a single Cortex-M4F. >> * Two Gigabit Industrial Communication Subsystems (ICSSG). >> * Integrated Ethernet switch supporting up to a total of two external >> ports. >> * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory >> controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other >> peripherals. >> * Centralized System Controller for Security, Power, and Resource >> Management (DMSC). >> >> See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) >> for further details: https://www.ti.com/lit/pdf/spruim2 >> >> Introduce basic support for the AM642 SoC to enable minimal >> ramdisk boot. Introduce a limited set of MAIN domain periperhals >> under cbass_main and a placeholder cbass_mcu node for future MCU >> domain usage. >> >> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 178 +++++++++++++++++++++++ >> arch/arm64/boot/dts/ti/k3-am64.dtsi | 95 ++++++++++++ >> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++++++ >> 3 files changed, 338 insertions(+) >> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi >> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi >> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi >> new file mode 100644 >> index 000000000000..4830a8e4d89b >> --- /dev/null >> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi >> @@ -0,0 +1,178 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Device Tree Source for AM642 SoC Family Main Domain peripherals >> + * >> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ >> + */ >> + >> +&cbass_main { >> + gic500: interrupt-controller@1800000 { >> + compatible = "arm,gic-v3"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ >> + <0x00 0x01840000 0x00 0xC0000>; /* GICR */ >> + /* >> + * vcpumntirq: >> + * virtual CPU interface maintenance interrupt >> + */ >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + >> + gic_its: msi-controller@1820000 { >> + compatible = "arm,gic-v3-its"; >> + reg = <0x00 0x01820000 0x00 0x10000>; >> + socionext,synquacer-pre-its = <0x1000000 0x400000>; >> + msi-controller; >> + #msi-cells = <1>; >> + }; >> + }; >> + >> + dmss { >> + compatible = "simple-mfd"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + dma-ranges; >> + ranges; >> + >> + secure_proxy_main: mailbox@4d000000 { >> + compatible = "ti,am654-secure-proxy"; >> + #mbox-cells = <1>; >> + reg-names = "target_data", "rt", "scfg"; >> + reg = <0x00 0x4d000000 0x00 0x80000>, >> + <0x00 0x4a600000 0x00 0x80000>, >> + <0x00 0x4a400000 0x00 0x80000>; >> + interrupt-names = "rx_012"; >> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + }; >> + >> + dmsc: dmsc { >> + compatible = "ti,k2g-sci"; >> + ti,host-id = <12>; >> + mbox-names = "rx", "tx"; >> + mboxes= <&secure_proxy_main 12>, >> + <&secure_proxy_main 13>; >> + >> + k3_pds: power-controller { >> + compatible = "ti,sci-pm-domain"; >> + #power-domain-cells = <2>; >> + }; >> + >> + k3_clks: clocks { >> + compatible = "ti,k2g-sci-clk"; >> + #clock-cells = <2>; >> + }; >> + >> + k3_reset: reset-controller { >> + compatible = "ti,sci-reset"; >> + #reset-cells = <2>; >> + }; >> + }; >> + >> + main_pmx0: pinctrl@f4000 { >> + compatible = "pinctrl-single"; >> + reg = <0x00 0xf4000 0x00 0x2e4>; >> + #pinctrl-cells = <1>; >> + pinctrl-single,register-width = <32>; >> + pinctrl-single,function-mask = <0xffffffff>; >> + }; >> + >> + chipid@43000014 { >> + compatible = "ti,am654-chipid"; >> + reg = <0x00 0x43000014 0x00 0x4>; >> + }; >> + >> + main_uart0: serial@2800000 { >> + compatible = "ti,am64-uart", "ti,am654-uart"; >> + reg = <0x00 0x02800000 0x00 0x100>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; >> + clock-frequency = <48000000>; >> + current-speed = <115200>; >> + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; >> + clocks = <&k3_clks 146 0>; >> + clock-names = "fclk"; >> + }; >> + >> + main_uart1: serial@2810000 { >> + compatible = "ti,am64-uart", "ti,am654-uart"; >> + reg = <0x00 0x02810000 0x00 0x100>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; >> + clock-frequency = <48000000>; >> + current-speed = <115200>; >> + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; >> + clocks = <&k3_clks 152 0>; >> + clock-names = "fclk"; >> + }; >> + >> + main_uart2: serial@2820000 { >> + compatible = "ti,am64-uart", "ti,am654-uart"; >> + reg = <0x00 0x02820000 0x00 0x100>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; >> + clock-frequency = <48000000>; >> + current-speed = <115200>; >> + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; >> + clocks = <&k3_clks 153 0>; >> + clock-names = "fclk"; >> + }; >> + >> + main_uart3: serial@2830000 { >> + compatible = "ti,am64-uart", "ti,am654-uart"; >> + reg = <0x00 0x02830000 0x00 0x100>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; >> + clock-frequency = <48000000>; >> + current-speed = <115200>; >> + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; >> + clocks = <&k3_clks 154 0>; >> + clock-names = "fclk"; >> + }; >> + >> + main_uart4: serial@2840000 { >> + compatible = "ti,am64-uart", "ti,am654-uart"; >> + reg = <0x00 0x02840000 0x00 0x100>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; >> + clock-frequency = <48000000>; >> + current-speed = <115200>; >> + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; >> + clocks = <&k3_clks 155 0>; >> + clock-names = "fclk"; >> + }; >> + >> + main_uart5: serial@2850000 { >> + compatible = "ti,am64-uart", "ti,am654-uart"; >> + reg = <0x00 0x02850000 0x00 0x100>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; >> + clock-frequency = <48000000>; >> + current-speed = <115200>; >> + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; >> + clocks = <&k3_clks 156 0>; >> + clock-names = "fclk"; >> + }; >> + >> + main_uart6: serial@2860000 { >> + compatible = "ti,am64-uart", "ti,am654-uart"; >> + reg = <0x00 0x02860000 0x00 0x100>; >> + reg-shift = <2>; >> + reg-io-width = <4>; >> + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; >> + clock-frequency = <48000000>; >> + current-speed = <115200>; >> + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; >> + clocks = <&k3_clks 158 0>; >> + clock-names = "fclk"; >> + }; >> +}; >> diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi >> new file mode 100644 >> index 000000000000..0637cf9ede5f >> --- /dev/null >> +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi >> @@ -0,0 +1,95 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Device Tree Source for AM642 SoC Family >> + * >> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ >> + */ >> + >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/pinctrl/k3.h> >> +#include <dt-bindings/soc/ti,sci_pm_domain.h> >> + >> +/ { >> + model = "Texas Instruments K3 AM642 SoC"; >> + compatible = "ti,am642"; >> + interrupt-parent = <&gic500>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + aliases { >> + serial2 = &main_uart0; >> + serial3 = &main_uart1; >> + serial4 = &main_uart2; >> + serial5 = &main_uart3; >> + serial6 = &main_uart4; >> + serial7 = &main_uart5; >> + serial8 = &main_uart6; Yeah, this looks weird. I understand that serial0 and serial1 are meant for MCU UARTs, but any reason why we don't want to add the k3-am64-mcu.dtsi and the MCU UARTs along with this patch? regards Suman >> + }; >> + >> + chosen { }; >> + >> + firmware { >> + optee { >> + compatible = "linaro,optee-tz"; >> + method = "smc"; >> + }; >> + >> + psci: psci { >> + compatible = "arm,psci-1.0"; >> + method = "smc"; >> + }; >> + }; >> + >> + a53_timer0: timer-cl0-cpu0 { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ >> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ >> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ >> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ >> + }; >> + >> + pmu: pmu { >> + compatible = "arm,armv8-pmuv3"; >> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + cbass_main: bus@f4000 { >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ >> + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ >> + <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ >> + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ >> + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ >> + <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ >> + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ >> + <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */ >> + <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */ >> + <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */ >> + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ >> + <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */ >> + <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */ >> + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */ >> + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */ >> + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ >> + <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002e4>, /* PINCTRL */ > > Can you move this to the top, so that all these are in increasing memory order? > >> + <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ >> + <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ >> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ > > This is atleast missing the ranges for On-Chip SRAM and the R5FSS, but those can > always be added incrementally as well. > > Also, is there a reason for using these ranges a bit more granular compared to > the earlier SoCs? > > regards > Suman > >> + >> + /* MCU Domain Range */ >> + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; >> + >> + cbass_mcu: bus@4000000 { >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ >> + }; >> + }; >> +}; >> + >> +/* Now include the peripherals for each bus segments */ >> +#include "k3-am64-main.dtsi" >> diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi >> new file mode 100644 >> index 000000000000..b30f239e84f1 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi >> @@ -0,0 +1,65 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Device Tree Source for AM642 SoC family in Dual core configuration >> + * >> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ >> + */ >> + >> +/dts-v1/; >> + >> +#include "k3-am64.dtsi" >> + >> +/ { >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu-map { >> + cluster0: cluster0 { >> + core0 { >> + cpu = <&cpu0>; >> + }; >> + >> + core1 { >> + cpu = <&cpu1>; >> + }; >> + }; >> + }; >> + >> + cpu0: cpu@0 { >> + compatible = "arm,cortex-a53"; >> + reg = <0x000>; >> + device_type = "cpu"; >> + enable-method = "psci"; >> + i-cache-size = <0x8000>; >> + i-cache-line-size = <64>; >> + i-cache-sets = <256>; >> + d-cache-size = <0x8000>; >> + d-cache-line-size = <64>; >> + d-cache-sets = <128>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + cpu1: cpu@1 { >> + compatible = "arm,cortex-a53"; >> + reg = <0x001>; >> + device_type = "cpu"; >> + enable-method = "psci"; >> + i-cache-size = <0x8000>; >> + i-cache-line-size = <64>; >> + i-cache-sets = <256>; >> + d-cache-size = <0x8000>; >> + d-cache-line-size = <64>; >> + d-cache-sets = <128>; >> + next-level-cache = <&L2_0>; >> + }; >> + }; >> + >> + L2_0: l2-cache0 { >> + compatible = "cache"; >> + cache-level = <2>; >> + cache-size = <0x40000>; >> + cache-line-size = <64>; >> + cache-sets = <512>; >> + }; >> +}; >> > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] arm64: dts: ti: Add Support for AM642 SoC 2020-12-03 22:00 ` Suman Anna @ 2021-01-05 4:02 ` Dave Gerlach 2021-01-05 15:12 ` Nishanth Menon 0 siblings, 1 reply; 16+ messages in thread From: Dave Gerlach @ 2021-01-05 4:02 UTC (permalink / raw) To: Suman Anna, Rob Herring, Nishanth Menon Cc: devicetree, Vignesh Raghavendra, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Aswath Govindraju, linux-arm-kernel Suman, On 12/3/20 4:00 PM, Suman Anna wrote: > On 12/3/20 3:56 PM, Suman Anna wrote: >> Hi Dave, >> >> On 11/24/20 11:20 PM, Dave Gerlach wrote: >>> The AM642 SoC belongs to the K3 Multicore SoC architecture platform, >>> providing advanced system integration to enable applications such as >>> Motor Drives, PLC, Remote IO and IoT Gateways. >>> >>> Some highlights of this SoC are: >>> * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F >>> MCUs, and a single Cortex-M4F. >>> * Two Gigabit Industrial Communication Subsystems (ICSSG). >>> * Integrated Ethernet switch supporting up to a total of two external >>> ports. >>> * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory >>> controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other >>> peripherals. >>> * Centralized System Controller for Security, Power, and Resource >>> Management (DMSC). >>> >>> See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) >>> for further details: https://www.ti.com/lit/pdf/spruim2 >>> >>> Introduce basic support for the AM642 SoC to enable minimal >>> ramdisk boot. Introduce a limited set of MAIN domain periperhals >>> under cbass_main and a placeholder cbass_mcu node for future MCU >>> domain usage. >>> >>> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> >>> --- >>> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 178 +++++++++++++++++++++++ >>> arch/arm64/boot/dts/ti/k3-am64.dtsi | 95 ++++++++++++ >>> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++++++ >>> 3 files changed, 338 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi >>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi >>> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi >>> ... snip ... >>> + main_uart6: serial@2860000 { >>> + compatible = "ti,am64-uart", "ti,am654-uart"; >>> + reg = <0x00 0x02860000 0x00 0x100>; >>> + reg-shift = <2>; >>> + reg-io-width = <4>; >>> + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-frequency = <48000000>; >>> + current-speed = <115200>; >>> + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; >>> + clocks = <&k3_clks 158 0>; >>> + clock-names = "fclk"; >>> + }; >>> +}; >>> diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi >>> new file mode 100644 >>> index 000000000000..0637cf9ede5f >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi >>> @@ -0,0 +1,95 @@ >>> +// SPDX-License-Identifier: GPL-2.0 >>> +/* >>> + * Device Tree Source for AM642 SoC Family >>> + * >>> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ >>> + */ >>> + >>> +#include <dt-bindings/interrupt-controller/irq.h> >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>> +#include <dt-bindings/pinctrl/k3.h> >>> +#include <dt-bindings/soc/ti,sci_pm_domain.h> >>> + >>> +/ { >>> + model = "Texas Instruments K3 AM642 SoC"; >>> + compatible = "ti,am642"; >>> + interrupt-parent = <&gic500>; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + aliases { >>> + serial2 = &main_uart0; >>> + serial3 = &main_uart1; >>> + serial4 = &main_uart2; >>> + serial5 = &main_uart3; >>> + serial6 = &main_uart4; >>> + serial7 = &main_uart5; >>> + serial8 = &main_uart6; > > Yeah, this looks weird. I understand that serial0 and serial1 are meant for MCU > UARTs, but any reason why we don't want to add the k3-am64-mcu.dtsi and the MCU > UARTs along with this patch? > > regards > Suman Sure, I will add them. Was originally trying to keep this as bare bones as possible but I will just add them to give us all uarts. > >>> + }; >>> + >>> + chosen { }; >>> + >>> + firmware { >>> + optee { >>> + compatible = "linaro,optee-tz"; >>> + method = "smc"; >>> + }; >>> + >>> + psci: psci { >>> + compatible = "arm,psci-1.0"; >>> + method = "smc"; >>> + }; >>> + }; >>> + >>> + a53_timer0: timer-cl0-cpu0 { >>> + compatible = "arm,armv8-timer"; >>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ >>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ >>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ >>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ >>> + }; >>> + >>> + pmu: pmu { >>> + compatible = "arm,armv8-pmuv3"; >>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>> + }; >>> + >>> + cbass_main: bus@f4000 { >>> + compatible = "simple-bus"; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ >>> + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ >>> + <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ >>> + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ >>> + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ >>> + <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ >>> + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ >>> + <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */ >>> + <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */ >>> + <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */ >>> + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ >>> + <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */ >>> + <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */ >>> + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */ >>> + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */ >>> + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ >>> + <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002e4>, /* PINCTRL */ >> >> Can you move this to the top, so that all these are in increasing memory order? Yes done. >> >>> + <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ >>> + <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ >>> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ >> >> This is atleast missing the ranges for On-Chip SRAM and the R5FSS, but those can >> always be added incrementally as well. Yes, I think they should be added incrementally once a user is present. >> >> Also, is there a reason for using these ranges a bit more granular compared to >> the earlier SoCs? Any reason we shouldn't be? Memory map has different groupings of peripherals. Regards, Dave >> >> regards >> Suman >> >>> + >>> + /* MCU Domain Range */ >>> + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; >>> + >>> + cbass_mcu: bus@4000000 { >>> + compatible = "simple-bus"; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ >>> + }; >>> + }; >>> +}; >>> + >>> +/* Now include the peripherals for each bus segments */ >>> +#include "k3-am64-main.dtsi" >>> diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi >>> new file mode 100644 >>> index 000000000000..b30f239e84f1 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi >>> @@ -0,0 +1,65 @@ >>> +// SPDX-License-Identifier: GPL-2.0 >>> +/* >>> + * Device Tree Source for AM642 SoC family in Dual core configuration >>> + * >>> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ >>> + */ >>> + >>> +/dts-v1/; >>> + >>> +#include "k3-am64.dtsi" >>> + >>> +/ { >>> + cpus { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + cpu-map { >>> + cluster0: cluster0 { >>> + core0 { >>> + cpu = <&cpu0>; >>> + }; >>> + >>> + core1 { >>> + cpu = <&cpu1>; >>> + }; >>> + }; >>> + }; >>> + >>> + cpu0: cpu@0 { >>> + compatible = "arm,cortex-a53"; >>> + reg = <0x000>; >>> + device_type = "cpu"; >>> + enable-method = "psci"; >>> + i-cache-size = <0x8000>; >>> + i-cache-line-size = <64>; >>> + i-cache-sets = <256>; >>> + d-cache-size = <0x8000>; >>> + d-cache-line-size = <64>; >>> + d-cache-sets = <128>; >>> + next-level-cache = <&L2_0>; >>> + }; >>> + >>> + cpu1: cpu@1 { >>> + compatible = "arm,cortex-a53"; >>> + reg = <0x001>; >>> + device_type = "cpu"; >>> + enable-method = "psci"; >>> + i-cache-size = <0x8000>; >>> + i-cache-line-size = <64>; >>> + i-cache-sets = <256>; >>> + d-cache-size = <0x8000>; >>> + d-cache-line-size = <64>; >>> + d-cache-sets = <128>; >>> + next-level-cache = <&L2_0>; >>> + }; >>> + }; >>> + >>> + L2_0: l2-cache0 { >>> + compatible = "cache"; >>> + cache-level = <2>; >>> + cache-size = <0x40000>; >>> + cache-line-size = <64>; >>> + cache-sets = <512>; >>> + }; >>> +}; >>> >> > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] arm64: dts: ti: Add Support for AM642 SoC 2021-01-05 4:02 ` Dave Gerlach @ 2021-01-05 15:12 ` Nishanth Menon 2021-01-05 15:53 ` Dave Gerlach 0 siblings, 1 reply; 16+ messages in thread From: Nishanth Menon @ 2021-01-05 15:12 UTC (permalink / raw) To: Dave Gerlach Cc: devicetree, Vignesh Raghavendra, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring, Aswath Govindraju, linux-arm-kernel On 22:02-20210104, Dave Gerlach wrote: > >> This is atleast missing the ranges for On-Chip SRAM and the R5FSS, but those can > >> always be added incrementally as well. > > Yes, I think they should be added incrementally once a user is present. > Most of the driver dependencies are resolved in v5.11-rc1. So, you should be able to add a lot of devices (aka users) instead of making this a barebones dts as the first introduction - I see no benefit of things coming in piece meal - other than creating all kind of dependency mayhem that I don't want to deal with. Please make sure that all nodes for all peripherals that can be introduced in v5.11-rc1 is part of this introduction of device. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] arm64: dts: ti: Add Support for AM642 SoC 2021-01-05 15:12 ` Nishanth Menon @ 2021-01-05 15:53 ` Dave Gerlach 2021-01-05 16:14 ` Nishanth Menon 0 siblings, 1 reply; 16+ messages in thread From: Dave Gerlach @ 2021-01-05 15:53 UTC (permalink / raw) To: Nishanth Menon Cc: devicetree, Vignesh Raghavendra, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring, Aswath Govindraju, linux-arm-kernel On 1/5/21 9:12 AM, Nishanth Menon wrote: > On 22:02-20210104, Dave Gerlach wrote: >>>> This is atleast missing the ranges for On-Chip SRAM and the R5FSS, but those can >>>> always be added incrementally as well. >> >> Yes, I think they should be added incrementally once a user is present. >> > > > Most of the driver dependencies are resolved in v5.11-rc1. So, you > should be able to add a lot of devices (aka users) instead of making > this a barebones dts as the first introduction - I see no benefit of > things coming in piece meal - other than creating all kind of dependency > mayhem that I don't want to deal with. > > Please make sure that all nodes for all peripherals that can be > introduced in v5.11-rc1 is part of this introduction of device. > Yeah that's no issue, I will add those that Suman referenced for v2 and then that covers every entry I am currently aware of. Regards, Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] arm64: dts: ti: Add Support for AM642 SoC 2021-01-05 15:53 ` Dave Gerlach @ 2021-01-05 16:14 ` Nishanth Menon 0 siblings, 0 replies; 16+ messages in thread From: Nishanth Menon @ 2021-01-05 16:14 UTC (permalink / raw) To: Dave Gerlach Cc: devicetree, Vignesh Raghavendra, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring, Aswath Govindraju, linux-arm-kernel On 09:53-20210105, Dave Gerlach wrote: > > On 1/5/21 9:12 AM, Nishanth Menon wrote: > > On 22:02-20210104, Dave Gerlach wrote: > >>>> This is atleast missing the ranges for On-Chip SRAM and the R5FSS, but those can > >>>> always be added incrementally as well. > >> > >> Yes, I think they should be added incrementally once a user is present. > >> > > > > > > Most of the driver dependencies are resolved in v5.11-rc1. So, you > > should be able to add a lot of devices (aka users) instead of making > > this a barebones dts as the first introduction - I see no benefit of > > things coming in piece meal - other than creating all kind of dependency > > mayhem that I don't want to deal with. > > > > Please make sure that all nodes for all peripherals that can be > > introduced in v5.11-rc1 is part of this introduction of device. > > > > Yeah that's no issue, I will add those that Suman referenced for v2 and > then that covers every entry I am currently aware of. Perfect, thanks. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] arm64: dts: ti: Add Support for AM642 SoC 2020-11-25 5:20 ` [PATCH 2/3] arm64: dts: ti: Add Support " Dave Gerlach 2020-12-03 21:56 ` Suman Anna @ 2020-12-04 13:17 ` Grygorii Strashko 2021-01-05 3:52 ` Dave Gerlach 2021-01-05 7:19 ` Vignesh Raghavendra 2 siblings, 1 reply; 16+ messages in thread From: Grygorii Strashko @ 2020-12-04 13:17 UTC (permalink / raw) To: Dave Gerlach, Rob Herring, Nishanth Menon Cc: devicetree, Vignesh Raghavendra, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Peter Ujfalusi, Lokesh Vutla, Aswath Govindraju, linux-arm-kernel On 25/11/2020 07:20, Dave Gerlach wrote: > The AM642 SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration to enable applications such as > Motor Drives, PLC, Remote IO and IoT Gateways. > > Some highlights of this SoC are: > * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F > MCUs, and a single Cortex-M4F. > * Two Gigabit Industrial Communication Subsystems (ICSSG). > * Integrated Ethernet switch supporting up to a total of two external > ports. > * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory > controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other > peripherals. > * Centralized System Controller for Security, Power, and Resource > Management (DMSC). > > See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) > for further details: https://www.ti.com/lit/pdf/spruim2 > > Introduce basic support for the AM642 SoC to enable minimal > ramdisk boot. Introduce a limited set of MAIN domain periperhals > under cbass_main and a placeholder cbass_mcu node for future MCU > domain usage. > > Signed-off-by: Dave Gerlach <d-gerlach@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 178 +++++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am64.dtsi | 95 ++++++++++++ > arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++++++ > 3 files changed, 338 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi > > diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi > new file mode 100644 > index 000000000000..4830a8e4d89b > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi > @@ -0,0 +1,178 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for AM642 SoC Family Main Domain peripherals > + * > + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +&cbass_main { > + gic500: interrupt-controller@1800000 { > + compatible = "arm,gic-v3"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ > + <0x00 0x01840000 0x00 0xC0000>; /* GICR */ > + /* > + * vcpumntirq: > + * virtual CPU interface maintenance interrupt > + */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gic_its: msi-controller@1820000 { > + compatible = "arm,gic-v3-its"; > + reg = <0x00 0x01820000 0x00 0x10000>; > + socionext,synquacer-pre-its = <0x1000000 0x400000>; > + msi-controller; > + #msi-cells = <1>; > + }; > + }; > + > + dmss { > + compatible = "simple-mfd"; > + #address-cells = <2>; > + #size-cells = <2>; > + dma-ranges; > + ranges; > + > + secure_proxy_main: mailbox@4d000000 { > + compatible = "ti,am654-secure-proxy"; > + #mbox-cells = <1>; > + reg-names = "target_data", "rt", "scfg"; > + reg = <0x00 0x4d000000 0x00 0x80000>, > + <0x00 0x4a600000 0x00 0x80000>, > + <0x00 0x4a400000 0x00 0x80000>; > + interrupt-names = "rx_012"; > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + dmsc: dmsc { > + compatible = "ti,k2g-sci"; > + ti,host-id = <12>; > + mbox-names = "rx", "tx"; > + mboxes= <&secure_proxy_main 12>, > + <&secure_proxy_main 13>; > + > + k3_pds: power-controller { > + compatible = "ti,sci-pm-domain"; > + #power-domain-cells = <2>; > + }; > + > + k3_clks: clocks { > + compatible = "ti,k2g-sci-clk"; > + #clock-cells = <2>; > + }; > + > + k3_reset: reset-controller { > + compatible = "ti,sci-reset"; > + #reset-cells = <2>; > + }; > + }; > + > + main_pmx0: pinctrl@f4000 { > + compatible = "pinctrl-single"; > + reg = <0x00 0xf4000 0x00 0x2e4>; > + #pinctrl-cells = <1>; > + pinctrl-single,register-width = <32>; > + pinctrl-single,function-mask = <0xffffffff>; > + }; > + > + chipid@43000014 { > + compatible = "ti,am654-chipid"; > + reg = <0x00 0x43000014 0x00 0x4>; > + }; Could you add proper syscon node for CTRL_MMR and place chipid under it, pls? -- Best regards, grygorii _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] arm64: dts: ti: Add Support for AM642 SoC 2020-12-04 13:17 ` Grygorii Strashko @ 2021-01-05 3:52 ` Dave Gerlach 0 siblings, 0 replies; 16+ messages in thread From: Dave Gerlach @ 2021-01-05 3:52 UTC (permalink / raw) To: Grygorii Strashko, Rob Herring, Nishanth Menon Cc: devicetree, Vignesh Raghavendra, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Aswath Govindraju, linux-arm-kernel Hi, On 12/4/20 7:17 AM, Grygorii Strashko wrote: > > > On 25/11/2020 07:20, Dave Gerlach wrote: >> The AM642 SoC belongs to the K3 Multicore SoC architecture platform, >> providing advanced system integration to enable applications such as >> Motor Drives, PLC, Remote IO and IoT Gateways. >> >> Some highlights of this SoC are: >> * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F >> MCUs, and a single Cortex-M4F. >> * Two Gigabit Industrial Communication Subsystems (ICSSG). >> * Integrated Ethernet switch supporting up to a total of two external >> ports. >> * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory >> controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other >> peripherals. >> * Centralized System Controller for Security, Power, and Resource >> Management (DMSC). >> >> See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) >> for further details: https://www.ti.com/lit/pdf/spruim2 >> >> Introduce basic support for the AM642 SoC to enable minimal >> ramdisk boot. Introduce a limited set of MAIN domain periperhals >> under cbass_main and a placeholder cbass_mcu node for future MCU >> domain usage. >> >> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 178 +++++++++++++++++++++++ >> arch/arm64/boot/dts/ti/k3-am64.dtsi | 95 ++++++++++++ >> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++++++ >> 3 files changed, 338 insertions(+) >> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi >> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi >> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi >> new file mode 100644 >> index 000000000000..4830a8e4d89b >> --- /dev/null >> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi >> @@ -0,0 +1,178 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Device Tree Source for AM642 SoC Family Main Domain peripherals >> + * >> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ >> + */ >> + >> +&cbass_main { >> + gic500: interrupt-controller@1800000 { >> + compatible = "arm,gic-v3"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ >> + <0x00 0x01840000 0x00 0xC0000>; /* GICR */ >> + /* >> + * vcpumntirq: >> + * virtual CPU interface maintenance interrupt >> + */ >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + >> + gic_its: msi-controller@1820000 { >> + compatible = "arm,gic-v3-its"; >> + reg = <0x00 0x01820000 0x00 0x10000>; >> + socionext,synquacer-pre-its = <0x1000000 0x400000>; >> + msi-controller; >> + #msi-cells = <1>; >> + }; >> + }; >> + >> + dmss { >> + compatible = "simple-mfd"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + dma-ranges; >> + ranges; >> + >> + secure_proxy_main: mailbox@4d000000 { >> + compatible = "ti,am654-secure-proxy"; >> + #mbox-cells = <1>; >> + reg-names = "target_data", "rt", "scfg"; >> + reg = <0x00 0x4d000000 0x00 0x80000>, >> + <0x00 0x4a600000 0x00 0x80000>, >> + <0x00 0x4a400000 0x00 0x80000>; >> + interrupt-names = "rx_012"; >> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + }; >> + >> + dmsc: dmsc { >> + compatible = "ti,k2g-sci"; >> + ti,host-id = <12>; >> + mbox-names = "rx", "tx"; >> + mboxes= <&secure_proxy_main 12>, >> + <&secure_proxy_main 13>; >> + >> + k3_pds: power-controller { >> + compatible = "ti,sci-pm-domain"; >> + #power-domain-cells = <2>; >> + }; >> + >> + k3_clks: clocks { >> + compatible = "ti,k2g-sci-clk"; >> + #clock-cells = <2>; >> + }; >> + >> + k3_reset: reset-controller { >> + compatible = "ti,sci-reset"; >> + #reset-cells = <2>; >> + }; >> + }; >> + >> + main_pmx0: pinctrl@f4000 { >> + compatible = "pinctrl-single"; >> + reg = <0x00 0xf4000 0x00 0x2e4>; >> + #pinctrl-cells = <1>; >> + pinctrl-single,register-width = <32>; >> + pinctrl-single,function-mask = <0xffffffff>; >> + }; >> + >> + chipid@43000014 { >> + compatible = "ti,am654-chipid"; >> + reg = <0x00 0x43000014 0x00 0x4>; >> + }; > > Could you add proper syscon node for CTRL_MMR and place chipid under it, pls? Sure this is no problem for v2, will do. Regards, Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/3] arm64: dts: ti: Add Support for AM642 SoC 2020-11-25 5:20 ` [PATCH 2/3] arm64: dts: ti: Add Support " Dave Gerlach 2020-12-03 21:56 ` Suman Anna 2020-12-04 13:17 ` Grygorii Strashko @ 2021-01-05 7:19 ` Vignesh Raghavendra 2 siblings, 0 replies; 16+ messages in thread From: Vignesh Raghavendra @ 2021-01-05 7:19 UTC (permalink / raw) To: Dave Gerlach, Rob Herring, Nishanth Menon Cc: devicetree, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Aswath Govindraju, linux-arm-kernel Hi Dave, On 11/25/20 10:50 AM, Dave Gerlach wrote: > + cbass_main: bus@f4000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ > + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ > + <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ > + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ > + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ > + <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ > + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ > + <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */ > + <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */ > + <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */ > + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ > + <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */ > + <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */ > + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */ > + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */ > + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ Could you please include OSPI DAT0 region: + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ This will be used by R5 SPL to access OSPI (OSPI data region within 32 bit addressable space) > + <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002e4>, /* PINCTRL */ > + <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ > + <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ > + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ > + > + /* MCU Domain Range */ > + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; > + > + cbass_mcu: bus@4000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ > + }; > + }; > +}; > + _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/3] arm64: dts: ti: Add support for AM642 EVM 2020-11-25 5:20 [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform Dave Gerlach 2020-11-25 5:20 ` [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM642 SoC Dave Gerlach 2020-11-25 5:20 ` [PATCH 2/3] arm64: dts: ti: Add Support " Dave Gerlach @ 2020-11-25 5:20 ` Dave Gerlach 2020-11-27 12:40 ` [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform Peter Ujfalusi 3 siblings, 0 replies; 16+ messages in thread From: Dave Gerlach @ 2020-11-25 5:20 UTC (permalink / raw) To: Rob Herring, Nishanth Menon Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Peter Ujfalusi, Lokesh Vutla, Aswath Govindraju, Suman Anna, linux-arm-kernel The AM642 EValuation Module (EVM) is a board that provides access to various peripherals available on the AM642 SoC, such as PCIe, USB 2.0, CPSW Ethernet, ADC, and more. Introduce basic support for the AM642 EVM to enable minimal ramdisk boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> --- arch/arm64/boot/dts/ti/Makefile | 2 + arch/arm64/boot/dts/ti/k3-am642-evm.dts | 61 +++++++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 65506f21ba30..c687739e2bca 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -11,3 +11,5 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb + +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts new file mode 100644 index 000000000000..8caa012382df --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am642.dtsi" + +/ { + compatible = "ti,am642-evm", "ti,am642"; + model = "Texas Instruments AM642 EVM"; + + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; +}; + +&main_uart1 { + status = "disabled"; +}; + +&main_uart2 { + status = "disabled"; +}; + +&main_uart3 { + status = "disabled"; +}; + +&main_uart4 { + status = "disabled"; +}; + +&main_uart5 { + status = "disabled"; +}; + +&main_uart6 { + status = "disabled"; +}; -- 2.28.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform 2020-11-25 5:20 [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform Dave Gerlach ` (2 preceding siblings ...) 2020-11-25 5:20 ` [PATCH 3/3] arm64: dts: ti: Add support for AM642 EVM Dave Gerlach @ 2020-11-27 12:40 ` Peter Ujfalusi 2020-11-27 14:25 ` Nishanth Menon 3 siblings, 1 reply; 16+ messages in thread From: Peter Ujfalusi @ 2020-11-27 12:40 UTC (permalink / raw) To: Dave Gerlach, Rob Herring, Nishanth Menon Cc: devicetree, Vignesh Raghavendra, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Aswath Govindraju, linux-arm-kernel Dave, On 25/11/2020 7.20, Dave Gerlach wrote: > This series adds initial support for the latest new SoC, AM642, > from Texas Instruments. > > Additional detail can be found in the patch descriptions, also > see AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for > further details: https://www.ti.com/lit/pdf/spruim2 Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com> fwiw, with these, plus the BCDMA/PKTDMA series [1] and one local dt patch to enable the DMAs on linux-next: https://pastebin.ubuntu.com/p/W5QkTMhrVp/ [1] https://lore.kernel.org/lkml/20201117105656.5236-1-peter.ujfalusi@ti.com/ > Regards, > Dave > > Dave Gerlach (3): > dt-bindings: arm: ti: Add bindings for AM642 SoC > arm64: dts: ti: Add Support for AM642 SoC > arm64: dts: ti: Add support for AM642 EVM > > .../devicetree/bindings/arm/ti/k3.yaml | 6 + > arch/arm64/boot/dts/ti/Makefile | 2 + > arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 178 ++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am64.dtsi | 95 ++++++++++ > arch/arm64/boot/dts/ti/k3-am642-evm.dts | 61 ++++++ > arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++++ > 6 files changed, 407 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts > create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi > - Péter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform 2020-11-27 12:40 ` [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform Peter Ujfalusi @ 2020-11-27 14:25 ` Nishanth Menon 0 siblings, 0 replies; 16+ messages in thread From: Nishanth Menon @ 2020-11-27 14:25 UTC (permalink / raw) To: Peter Ujfalusi Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring, Aswath Govindraju, linux-arm-kernel On 14:40-20201127, Peter Ujfalusi wrote: > Dave, > > On 25/11/2020 7.20, Dave Gerlach wrote: > > This series adds initial support for the latest new SoC, AM642, > > from Texas Instruments. > > > > Additional detail can be found in the patch descriptions, also > > see AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for > > further details: https://www.ti.com/lit/pdf/spruim2 > > Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> > Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com> > > fwiw, with these, plus the BCDMA/PKTDMA series [1] and one local dt > patch to enable the DMAs on linux-next: > https://pastebin.ubuntu.com/p/W5QkTMhrVp/ > > [1] > https://lore.kernel.org/lkml/20201117105656.5236-1-peter.ujfalusi@ti.com/ > Thanks Peter, Lets see if Rob is able to get to the binding.. The queue looks pretty deep today :( -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2021-01-05 16:16 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-11-25 5:20 [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform Dave Gerlach 2020-11-25 5:20 ` [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM642 SoC Dave Gerlach 2020-12-08 16:03 ` Rob Herring 2020-11-25 5:20 ` [PATCH 2/3] arm64: dts: ti: Add Support " Dave Gerlach 2020-12-03 21:56 ` Suman Anna 2020-12-03 22:00 ` Suman Anna 2021-01-05 4:02 ` Dave Gerlach 2021-01-05 15:12 ` Nishanth Menon 2021-01-05 15:53 ` Dave Gerlach 2021-01-05 16:14 ` Nishanth Menon 2020-12-04 13:17 ` Grygorii Strashko 2021-01-05 3:52 ` Dave Gerlach 2021-01-05 7:19 ` Vignesh Raghavendra 2020-11-25 5:20 ` [PATCH 3/3] arm64: dts: ti: Add support for AM642 EVM Dave Gerlach 2020-11-27 12:40 ` [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform Peter Ujfalusi 2020-11-27 14:25 ` Nishanth Menon
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).