From: Julien Thierry <jthierry@redhat.com>
To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com,
ardb@kernel.org, masahiroy@kernel.org, jpoimboe@redhat.com,
peterz@infradead.org, ycote@redhat.com,
Julien Thierry <jthierry@redhat.com>
Subject: [RFC PATCH v2 05/13] objtool: arm64: Decode add/sub instructions
Date: Wed, 3 Mar 2021 18:09:24 +0100 [thread overview]
Message-ID: <20210303170932.1838634-6-jthierry@redhat.com> (raw)
In-Reply-To: <20210303170932.1838634-1-jthierry@redhat.com>
Decode aarch64 additions and substractions and create stack_ops for
instructions interacting with SP or FP.
Signed-off-by: Julien Thierry <jthierry@redhat.com>
---
tools/objtool/arch/arm64/decode.c | 94 +++++++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
index 3ec0254f7306..54eeb8704a42 100644
--- a/tools/objtool/arch/arm64/decode.c
+++ b/tools/objtool/arch/arm64/decode.c
@@ -23,6 +23,13 @@
#include "../../../arch/arm64/lib/insn.c"
+static unsigned long sign_extend(unsigned long x, int nbits)
+{
+ unsigned long sign_bit = (x >> (nbits - 1)) & 1;
+
+ return ((~0UL + (sign_bit ^ 1)) << nbits) | x;
+}
+
bool arch_callee_saved_reg(unsigned char reg)
{
switch (reg) {
@@ -98,6 +105,61 @@ int arch_decode_hint_reg(struct instruction *insn, u8 sp_reg)
return -1;
}
+static struct stack_op *arm_make_add_op(enum aarch64_insn_register dest,
+ enum aarch64_insn_register src,
+ int val)
+{
+ struct stack_op *op;
+
+ op = calloc(1, sizeof(*op));
+ if (!op) {
+ WARN("calloc failed");
+ return NULL;
+ }
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = dest;
+ op->src.reg = src;
+ op->src.type = val != 0 ? OP_SRC_ADD : OP_SRC_REG;
+ op->src.offset = val;
+
+ return op;
+}
+
+static int arm_decode_add_sub_imm(u32 instr, bool set_flags,
+ enum insn_type *type,
+ unsigned long *immediate,
+ struct list_head *ops_list)
+{
+ u32 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, instr);
+ u32 rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, instr);
+
+ *type = INSN_OTHER;
+ *immediate = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_12, instr);
+
+ if (instr & AARCH64_INSN_LSL_12)
+ *immediate <<= 12;
+
+ if ((!set_flags && rd == AARCH64_INSN_REG_SP) ||
+ rd == AARCH64_INSN_REG_FP ||
+ rn == AARCH64_INSN_REG_FP ||
+ rn == AARCH64_INSN_REG_SP) {
+ struct stack_op *op;
+ int value;
+
+ if (aarch64_insn_is_subs_imm(instr) || aarch64_insn_is_sub_imm(instr))
+ value = -*immediate;
+ else
+ value = *immediate;
+
+ op = arm_make_add_op(rd, rn, value);
+ if (!op)
+ return -1;
+ list_add_tail(&op->list, ops_list);
+ }
+
+ return 0;
+}
+
int arch_decode_instruction(const struct elf *elf, const struct section *sec,
unsigned long offset, unsigned int maxlen,
unsigned int *len, enum insn_type *type,
@@ -121,6 +183,38 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
case AARCH64_INSN_CLS_UNKNOWN:
WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
return -1;
+ case AARCH64_INSN_CLS_DP_IMM:
+ /* Mov register to and from SP are aliases of add_imm */
+ if (aarch64_insn_is_add_imm(insn) ||
+ aarch64_insn_is_sub_imm(insn))
+ return arm_decode_add_sub_imm(insn, false, type, immediate,
+ ops_list);
+ else if (aarch64_insn_is_adds_imm(insn) ||
+ aarch64_insn_is_subs_imm(insn))
+ return arm_decode_add_sub_imm(insn, true, type, immediate,
+ ops_list);
+ else
+ *type = INSN_OTHER;
+ break;
+ case AARCH64_INSN_CLS_DP_REG:
+ if (aarch64_insn_is_mov_reg(insn)) {
+ enum aarch64_insn_register rd;
+ enum aarch64_insn_register rm;
+
+ rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, insn);
+ rm = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RM, insn);
+ if (rd == AARCH64_INSN_REG_FP || rm == AARCH64_INSN_REG_FP) {
+ struct stack_op *op;
+
+ op = arm_make_add_op(rd, rm, 0);
+ if (!op)
+ return -1;
+ list_add_tail(&op->list, ops_list);
+ break;
+ }
+ }
+ *type = INSN_OTHER;
+ break;
default:
*type = INSN_OTHER;
break;
--
2.25.4
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next prev parent reply other threads:[~2021-03-03 23:55 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-03 17:09 [RFC PATCH v2 00/13] objtool: add base support for arm64 Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 01/13] tools: Add some generic functions and headers Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 02/13] tools: arm64: Make aarch64 instruction decoder available to tools Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 03/13] tools: bug: Remove duplicate definition Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 04/13] objtool: arm64: Add base definition for arm64 backend Julien Thierry
2021-03-03 17:09 ` Julien Thierry [this message]
2021-03-03 17:09 ` [RFC PATCH v2 06/13] objtool: arm64: Decode jump and call related instructions Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 07/13] objtool: arm64: Decode other system instructions Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 08/13] objtool: arm64: Decode load/store instructions Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 09/13] objtool: arm64: Decode LDR instructions Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 10/13] objtool: arm64: Accept padding in code sections Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 11/13] objtool: arm64: Handle supported relocations in alternatives Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 12/13] objtool: arm64: Ignore replacement section for alternative callback Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 13/13] objtool: arm64: Enable stack validation for arm64 Julien Thierry
2021-03-07 10:25 ` Ard Biesheuvel
2021-03-09 14:31 ` Julien Thierry
2021-03-03 19:17 ` [RFC PATCH v2 00/13] objtool: add base support " Peter Zijlstra
2021-03-04 14:03 ` Julien Thierry
2021-03-05 23:51 ` Nick Desaulniers
2021-03-06 0:04 ` Nick Desaulniers
2021-03-09 14:27 ` Julien Thierry
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