From: Julien Thierry <jthierry@redhat.com>
To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com,
ardb@kernel.org, masahiroy@kernel.org, jpoimboe@redhat.com,
peterz@infradead.org, ycote@redhat.com,
Julien Thierry <jthierry@redhat.com>
Subject: [RFC PATCH v2 08/13] objtool: arm64: Decode load/store instructions
Date: Wed, 3 Mar 2021 18:09:27 +0100 [thread overview]
Message-ID: <20210303170932.1838634-9-jthierry@redhat.com> (raw)
In-Reply-To: <20210303170932.1838634-1-jthierry@redhat.com>
Decode load/store operations and create corresponding stack_ops for
operations targetting SP or FP.
Operations storing/loading multiple registers are split into separate
stack_ops storing single registers.
Operations modifying the base register get an additional stack_op
for the register update. Since the atomic register(s) load/store + base
register update gets split into multiple operations, to make sure
objtool always sees a valid stack, consider store instruction to perform
stack allocations (i.e. modifying the base pointer before the storing)
and loads de-allocations (i.e. modifying the base pointer after the
load).
Signed-off-by: Julien Thierry <jthierry@redhat.com>
---
tools/objtool/arch/arm64/decode.c | 148 ++++++++++++++++++++++++++++++
1 file changed, 148 insertions(+)
diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
index 3008dcbb5e64..4e086d2251f5 100644
--- a/tools/objtool/arch/arm64/decode.c
+++ b/tools/objtool/arch/arm64/decode.c
@@ -105,6 +105,48 @@ int arch_decode_hint_reg(struct instruction *insn, u8 sp_reg)
return -1;
}
+static struct stack_op *arm_make_store_op(enum aarch64_insn_register base,
+ enum aarch64_insn_register reg,
+ int offset)
+{
+ struct stack_op *op;
+
+ op = calloc(1, sizeof(*op));
+ if (!op) {
+ WARN("calloc failed");
+ return NULL;
+ }
+ op->dest.type = OP_DEST_REG_INDIRECT;
+ op->dest.reg = base;
+ op->dest.offset = offset;
+ op->src.type = OP_SRC_REG;
+ op->src.reg = reg;
+ op->src.offset = 0;
+
+ return op;
+}
+
+static struct stack_op *arm_make_load_op(enum aarch64_insn_register base,
+ enum aarch64_insn_register reg,
+ int offset)
+{
+ struct stack_op *op;
+
+ op = calloc(1, sizeof(*op));
+ if (!op) {
+ WARN("calloc failed");
+ return NULL;
+ }
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = reg;
+ op->dest.offset = 0;
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = base;
+ op->src.offset = offset;
+
+ return op;
+}
+
static struct stack_op *arm_make_add_op(enum aarch64_insn_register dest,
enum aarch64_insn_register src,
int val)
@@ -125,6 +167,101 @@ static struct stack_op *arm_make_add_op(enum aarch64_insn_register dest,
return op;
}
+static int arm_decode_load_store(u32 insn, enum insn_type *type,
+ unsigned long *immediate,
+ struct list_head *ops_list)
+{
+ enum aarch64_insn_register base;
+ enum aarch64_insn_register rt;
+ struct stack_op *op;
+ int size;
+ int offset;
+
+ *type = INSN_OTHER;
+
+ if (aarch64_insn_is_store_single(insn) ||
+ aarch64_insn_is_load_single(insn))
+ size = 1 << ((insn & GENMASK(31, 30)) >> 30);
+ else
+ size = 4 << ((insn >> 31) & 1);
+
+ if (aarch64_insn_is_store_imm(insn) || aarch64_insn_is_load_imm(insn))
+ *immediate = size * aarch64_insn_decode_immediate(AARCH64_INSN_IMM_12,
+ insn);
+ else if (aarch64_insn_is_store_pre(insn) ||
+ aarch64_insn_is_load_pre(insn) ||
+ aarch64_insn_is_store_post(insn) ||
+ aarch64_insn_is_load_post(insn))
+ *immediate = sign_extend(aarch64_insn_decode_immediate(AARCH64_INSN_IMM_9,
+ insn),
+ 9);
+ else if (aarch64_insn_is_stp(insn) || aarch64_insn_is_ldp(insn) ||
+ aarch64_insn_is_stp_pre(insn) ||
+ aarch64_insn_is_ldp_pre(insn) ||
+ aarch64_insn_is_stp_post(insn) ||
+ aarch64_insn_is_ldp_post(insn))
+ *immediate = size * sign_extend(aarch64_insn_decode_immediate(AARCH64_INSN_IMM_7,
+ insn),
+ 7);
+ else
+ return 1;
+
+ base = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, insn);
+ if (base != AARCH64_INSN_REG_FP && base != AARCH64_INSN_REG_SP)
+ return 0;
+
+ offset = *immediate;
+
+ if (aarch64_insn_is_store_pre(insn) || aarch64_insn_is_stp_pre(insn) ||
+ aarch64_insn_is_store_post(insn) || aarch64_insn_is_stp_post(insn)) {
+ op = arm_make_add_op(base, base, *immediate);
+ list_add_tail(&op->list, ops_list);
+
+ if (aarch64_insn_is_store_post(insn) || aarch64_insn_is_stp_post(insn))
+ offset = -*immediate;
+ else
+ offset = 0;
+ } else if (aarch64_insn_is_load_post(insn) || aarch64_insn_is_ldp_post(insn)) {
+ offset = 0;
+ }
+
+ /* First register */
+ rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
+ if (aarch64_insn_is_store_single(insn) ||
+ aarch64_insn_is_store_pair(insn))
+ op = arm_make_store_op(base, rt, offset);
+ else
+ op = arm_make_load_op(base, rt, offset);
+
+ if (!op)
+ return -1;
+ list_add_tail(&op->list, ops_list);
+
+ /* Second register (if present) */
+ if (aarch64_insn_is_store_pair(insn) ||
+ aarch64_insn_is_load_pair(insn)) {
+ rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT2,
+ insn);
+ if (aarch64_insn_is_store_pair(insn))
+ op = arm_make_store_op(base, rt, offset + size);
+ else
+ op = arm_make_load_op(base, rt, offset + size);
+ if (!op)
+ return -1;
+ list_add_tail(&op->list, ops_list);
+ }
+
+ if (aarch64_insn_is_load_pre(insn) || aarch64_insn_is_ldp_pre(insn) ||
+ aarch64_insn_is_load_post(insn) || aarch64_insn_is_ldp_post(insn)) {
+ op = arm_make_add_op(base, base, *immediate);
+ if (!op)
+ return -1;
+ list_add_tail(&op->list, ops_list);
+ }
+
+ return 0;
+}
+
static int arm_decode_add_sub_imm(u32 instr, bool set_flags,
enum insn_type *type,
unsigned long *immediate,
@@ -244,6 +381,17 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
*type = INSN_OTHER;
}
break;
+ case AARCH64_INSN_CLS_LDST:
+ {
+ int ret;
+
+ ret = arm_decode_load_store(insn, type, immediate, ops_list);
+ if (ret <= 0)
+ return ret;
+
+ *type = INSN_OTHER;
+ break;
+ }
default:
*type = INSN_OTHER;
break;
--
2.25.4
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next prev parent reply other threads:[~2021-03-03 23:49 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-03 17:09 [RFC PATCH v2 00/13] objtool: add base support for arm64 Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 01/13] tools: Add some generic functions and headers Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 02/13] tools: arm64: Make aarch64 instruction decoder available to tools Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 03/13] tools: bug: Remove duplicate definition Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 04/13] objtool: arm64: Add base definition for arm64 backend Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 05/13] objtool: arm64: Decode add/sub instructions Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 06/13] objtool: arm64: Decode jump and call related instructions Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 07/13] objtool: arm64: Decode other system instructions Julien Thierry
2021-03-03 17:09 ` Julien Thierry [this message]
2021-03-03 17:09 ` [RFC PATCH v2 09/13] objtool: arm64: Decode LDR instructions Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 10/13] objtool: arm64: Accept padding in code sections Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 11/13] objtool: arm64: Handle supported relocations in alternatives Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 12/13] objtool: arm64: Ignore replacement section for alternative callback Julien Thierry
2021-03-03 17:09 ` [RFC PATCH v2 13/13] objtool: arm64: Enable stack validation for arm64 Julien Thierry
2021-03-07 10:25 ` Ard Biesheuvel
2021-03-09 14:31 ` Julien Thierry
2021-03-03 19:17 ` [RFC PATCH v2 00/13] objtool: add base support " Peter Zijlstra
2021-03-04 14:03 ` Julien Thierry
2021-03-05 23:51 ` Nick Desaulniers
2021-03-06 0:04 ` Nick Desaulniers
2021-03-09 14:27 ` Julien Thierry
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