Re: [PATCH 1/9] dt-bindings: arm: msm: Add LLCC for SC7280

Re: [PATCH 1/9] dt-bindings: arm: msm: Add LLCC for SC7280

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2021-02-25 01:30:17)
> Add LLCC compatible for SC7280 SoC.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

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Re: [PATCH 1/9] dt-bindings: arm: msm: Add LLCC for SC7280

[Rob Herring]

On Thu, 25 Feb 2021 15:00:17 +0530, Sai Prakash Ranjan wrote:
> Add LLCC compatible for SC7280 SoC.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH 3/9] arm64: dts: qcom: sc7280: Add device tree node for LLCC

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
> Add a DT node for Last level cache (aka. system cache)
> controller which provides control over the last level
> cache present on SC7280 SoC.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Should add system-cache-controller to the devicetree spec. Or just use
cache-controller for the node name.

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Re: [PATCH 3/9] arm64: dts: qcom: sc7280: Add device tree node for LLCC

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2021-02-26 00:04:27)
> On 2021-02-26 01:07, Stephen Boyd wrote:
> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
> >> Add a DT node for Last level cache (aka. system cache)
> >> controller which provides control over the last level
> >> cache present on SC7280 SoC.
> >> 
> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> >> ---
> > 
> > Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> > 
> > Should add system-cache-controller to the devicetree spec. Or just use
> > cache-controller for the node name.
> 
> This was as per discussion in [1][2] where dt-schema throws an error
> since it expects cache-level to be associated with cache-controller.
> 

Ah right. Can you add system-cache-controller to the dt spec?

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Re: [PATCH 3/9] arm64: dts: qcom: sc7280: Add device tree node for LLCC

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2021-02-27 05:58:25)
> On 2021-02-27 00:15, Stephen Boyd wrote:
> > Quoting Sai Prakash Ranjan (2021-02-26 00:04:27)
> >> On 2021-02-26 01:07, Stephen Boyd wrote:
> >> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
> >> >> Add a DT node for Last level cache (aka. system cache)
> >> >> controller which provides control over the last level
> >> >> cache present on SC7280 SoC.
> >> >>
> >> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> >> >> ---
> >> >
> >> > Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> >> >
> >> > Should add system-cache-controller to the devicetree spec. Or just use
> >> > cache-controller for the node name.
> >> 
> >> This was as per discussion in [1][2] where dt-schema throws an error
> >> since it expects cache-level to be associated with cache-controller.
> >> 
> > 
> > Ah right. Can you add system-cache-controller to the dt spec?
> 
> Sure, I'll add it. Hopefully that won't have to block this change?
> Because I might need some time to get permissions to add it there.
> 

Doesn't block it for me.

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Re: [PATCH 4/9] dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280

[Manivannan Sadhasivam]

On Thu, Feb 25, 2021 at 03:00:20PM +0530, Sai Prakash Ranjan wrote:
> Add IPCC compatible for SC7280 SoC.
> 
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> index 168beeb7e9f7..06419543d235 100644
> --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> @@ -24,6 +24,7 @@ properties:
>    compatible:
>      items:
>        - enum:
> +          - qcom,sc7280-ipcc
>            - qcom,sm8250-ipcc
>        - const: qcom,ipcc
>  
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
> 

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Re: [PATCH 4/9] dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2021-02-25 01:30:20)
> Add IPCC compatible for SC7280 SoC.
> 
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

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Re: [PATCH 5/9] arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC

[Manivannan Sadhasivam]

On Thu, Feb 25, 2021 at 03:00:21PM +0530, Sai Prakash Ranjan wrote:
> Add the IPCC DT node which is used to send and receive IPC
> signals with remoteprocs for SC7280 SoC.
> 
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index aeeb47c70c3a..65c1e0f2fb56 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/clock/qcom,gcc-sc7280.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  
>  / {
> @@ -315,6 +316,15 @@ gcc: clock-controller@100000 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		ipcc: mailbox@408000 {
> +			compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
> +			reg = <0 0x00408000 0 0x1000>;
> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			#mbox-cells = <2>;
> +		};
> +
>  		qupv3_id_0: geniqup@9c0000 {
>  			compatible = "qcom,geni-se-qup";
>  			reg = <0 0x009c0000 0 0x2000>;
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
> 

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Re: [PATCH 5/9] arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2021-02-25 01:30:21)
> Add the IPCC DT node which is used to send and receive IPC
> signals with remoteprocs for SC7280 SoC.
> 
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

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Re: [PATCH 6/9] dt-bindings: soc: qcom: aoss: Add SC7280 compatible

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2021-02-25 01:30:22)
> Add SC7280 AOSS QMP compatible to the list of possible bindings.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

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Re: [PATCH 6/9] dt-bindings: soc: qcom: aoss: Add SC7280 compatible

[Rob Herring]

On Thu, 25 Feb 2021 15:00:22 +0530, Sai Prakash Ranjan wrote:
> Add SC7280 AOSS QMP compatible to the list of possible bindings.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH 7/9] soc: qcom: aoss: Add AOSS QMP support for SC7280

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2021-02-25 01:30:23)
> Add AOSS QMP support for SC7280 SoC.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

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Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
> Add a DT node for the AOSS QMP on SC7280 SoC.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 65c1e0f2fb56..cbd567ccc04e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -9,6 +9,7 @@
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/power/qcom-aoss-qmp.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  
>  / {
> @@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 {
>                         interrupt-controller;
>                 };
>  
> +               aoss_qmp: qmp@c300000 {

power-domain-controller@c300000? power-controller@c300000?

> +                       compatible = "qcom,sc7280-aoss-qmp";
> +                       reg = <0 0x0c300000 0 0x100000>;
> +                       interrupts-extended = <&ipcc IPCC_CLIENT_AOP
> +                                                    IPCC_MPROC_SIGNAL_GLINK_QMP
> +                                                    IRQ_TYPE_EDGE_RISING>;
> +                       mboxes = <&ipcc IPCC_CLIENT_AOP
> +                                       IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> +                       #clock-cells = <0>;
> +                       #power-domain-cells = <1>;
> +               };
> +
>                 spmi_bus: qcom,spmi@c440000 {

Ick, should be spmi@

>                         compatible = "qcom,spmi-pmic-arb";
>                         reg = <0 0x0c440000 0 0x1100>,

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Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2021-02-25 23:51:00)
> On 2021-02-26 01:11, Stephen Boyd wrote:
> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
> >> Add a DT node for the AOSS QMP on SC7280 SoC.
> >> 
> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> >> ---
> >>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++
> >>  1 file changed, 14 insertions(+)
> >> 
> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
> >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> index 65c1e0f2fb56..cbd567ccc04e 100644
> >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> @@ -9,6 +9,7 @@
> >>  #include <dt-bindings/clock/qcom,rpmh.h>
> >>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>  #include <dt-bindings/mailbox/qcom-ipcc.h>
> >> +#include <dt-bindings/power/qcom-aoss-qmp.h>
> >>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> >> 
> >>  / {
> >> @@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 {
> >>                         interrupt-controller;
> >>                 };
> >> 
> >> +               aoss_qmp: qmp@c300000 {
> > 
> > power-domain-controller@c300000? power-controller@c300000?
> > 
> 
> Its an AOSS message RAM and all other SM* SoCs have as qmp@
> and the dt binding as well, I see only SM8150 with power-controller,
> that should probably be fixed?

Node name should be generic while still being meaningful. Nobody knows
what qmp is, but power-controller makes sense. Can you fix this and the
others to be power-controller?

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Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node

[Stephen Boyd]

Quoting Sibi Sankar (2021-03-08 21:58:21)
> On 2021-02-27 19:26, Sai Prakash Ranjan wrote:
> > On 2021-02-27 00:16, Stephen Boyd wrote:
> >> Quoting Sai Prakash Ranjan (2021-02-25 23:51:00)
> >>> On 2021-02-26 01:11, Stephen Boyd wrote:
> >>> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
> >>> >> Add a DT node for the AOSS QMP on SC7280 SoC.
> >>> >>
> >>> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> >>> >> ---
> >>> >>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++
> >>> >>  1 file changed, 14 insertions(+)
> >>> >>
> >>> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> >> index 65c1e0f2fb56..cbd567ccc04e 100644
> >>> >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> >> @@ -9,6 +9,7 @@
> >>> >>  #include <dt-bindings/clock/qcom,rpmh.h>
> >>> >>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>> >>  #include <dt-bindings/mailbox/qcom-ipcc.h>
> >>> >> +#include <dt-bindings/power/qcom-aoss-qmp.h>
> >>> >>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> >>> >>
> >>> >>  / {
> >>> >> @@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 {
> >>> >>                         interrupt-controller;
> >>> >>                 };
> >>> >>
> >>> >> +               aoss_qmp: qmp@c300000 {
> >>> >
> >>> > power-domain-controller@c300000? power-controller@c300000?
> >>> >
> >>> 
> >>> Its an AOSS message RAM and all other SM* SoCs have as qmp@
> >>> and the dt binding as well, I see only SM8150 with power-controller,
> >>> that should probably be fixed?
> >> 
> >> Node name should be generic while still being meaningful. Nobody knows
> >> what qmp is, but power-controller makes sense. Can you fix this and 
> >> the
> >> others to be power-controller?
> >> 
> 
> we probably would be changing them back
> to qmp or something more generic soon
> since the consensus was qmp wasn't a
> power-controller. So not sure if its
> worth the effort here.
> 

Hmm alright. Maybe mailbox? qmp is not generic. What does it stand for?
qualcomm messaging protocol?

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Re: [PATCH 0/9] qcom/sc7280: Enable various hardware blocks on SC7280 SoC

[Bjorn Andersson]

On Thu 25 Feb 03:30 CST 2021, Sai Prakash Ranjan wrote:

> This series enables various hardware blocks such as LLCC, IPCC, AOSS QMP
> and Coresight on SC7280 SoC.
> 
> This series is dependent on the base support added for SC7280 in [1].
> 

I've picked some of these patches...


It would be helpful if you split series like this based on how they will
be picked up my various maintainers. E.g. I think it's quite likely
Jassi won't find and pick up the mailbox binding patch.


PS. I sent a patch to Jassi adding the mailbox binding directory to
MAINTAINERS.

Regards,
Bjorn

> [1] https://lore.kernel.org/patchwork/cover/1379842/
> 
> Sai Prakash Ranjan (9):
>   dt-bindings: arm: msm: Add LLCC for SC7280
>   soc: qcom: llcc: Add configuration data for SC7280
>   arm64: dts: qcom: sc7280: Add device tree node for LLCC
>   dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280
>   arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC
>   dt-bindings: soc: qcom: aoss: Add SC7280 compatible
>   soc: qcom: aoss: Add AOSS QMP support for SC7280
>   arm64: dts: qcom: sc7280: Add AOSS QMP node
>   arm64: dts: qcom: sc7280: Add Coresight support
> 
>  .../bindings/arm/msm/qcom,llcc.yaml           |   1 +
>  .../bindings/mailbox/qcom-ipcc.yaml           |   1 +
>  .../bindings/soc/qcom/qcom,aoss-qmp.txt       |   1 +
>  arch/arm64/boot/dts/qcom/sc7280.dtsi          | 520 ++++++++++++++++++
>  drivers/soc/qcom/llcc-qcom.c                  |  19 +
>  drivers/soc/qcom/qcom_aoss.c                  |   1 +
>  6 files changed, 543 insertions(+)
> 
> 
> base-commit: d79b47c59576a51d8e288a6b98b75ccf4afb8acd
> prerequisite-patch-id: d8babdd3c8a9923360af342f3d8d9876820272e5
> prerequisite-patch-id: 5757e07e4336d773d402769d09106924962ce31b
> prerequisite-patch-id: 9b21eb51aa86619f5695a511c65c9236e3bc0f2b
> prerequisite-patch-id: 2f834cc892f7f9109cbf32a87d504ba27b64a5df
> prerequisite-patch-id: 14b1185357703d750c3411a16e97675489ca7dde
> prerequisite-patch-id: 55c143f21b646c18da921a62bbd2801a5df38c8f
> prerequisite-patch-id: 66f4c58aff2f1a7283b0103590ff82384907bae3
> prerequisite-patch-id: 75e73e6b13ab91ed5e3a96b59957aa5e867d65ea
> prerequisite-patch-id: eb46845b4f9eb3706a26911042c2865a58577198
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
> 

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