From: Marco Felsch <m.felsch@pengutronix.de>
To: Heiko Schocher <hs@denx.de>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
linux-kernel@vger.kernel.org,
Krzysztof Kozlowski <krzk@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
NXP Linux Team <linux-imx@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Teresa Remmet <t.remmet@phytec.de>,
Fabio Estevam <festevam@gmail.com>
Subject: Re: [PATCH 2/2] arm64: imx8mp: imx8mp-phycore-som enable spi nor
Date: Mon, 8 Mar 2021 09:40:47 +0100 [thread overview]
Message-ID: <20210308084047.numy4o2jvsiz5d3v@pengutronix.de> (raw)
In-Reply-To: <20210308064046.1576267-3-hs@denx.de>
On 21-03-08 07:40, Heiko Schocher wrote:
> enable the mt25qu256aba spi nor on the imx8mp-phycore-som.
>
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
>
> .../dts/freescale/imx8mp-phycore-som.dtsi | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> index 44a8c2337cee4..0284e7a5c6bba 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> @@ -65,6 +65,22 @@ ethphy1: ethernet-phy@0 {
> };
> };
>
> +&flexspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexspi0>;
> + status = "okay";
> +
> + flash0: mt25qu256aba@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
Please make the compatible the first property followed by the reg
property. Also you don't need to add the #size-cells and #address-cells
now since you don't add a child node.
Regards,
Marco
> + spi-max-frequency = <80000000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + };
> +};
> +
> &i2c1 {
> clock-frequency = <400000>;
> pinctrl-names = "default";
> @@ -217,6 +233,17 @@ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11
> >;
> };
>
> + pinctrl_flexspi0: flexspi0grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
> + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
> + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
> + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
> + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
> + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
> + >;
> + };
> +
> pinctrl_i2c1: i2c1grp {
> fsl,pins = <
> MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
> --
> 2.29.2
>
>
>
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next prev parent reply other threads:[~2021-03-08 8:42 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-08 6:40 [PATCH 0/2] enable flexspi support on imx8mp Heiko Schocher
2021-03-08 6:40 ` [PATCH 1/2] arm64: dts: imx8mp: add flexspi node Heiko Schocher
2021-03-08 8:33 ` Marco Felsch
2021-03-08 6:40 ` [PATCH 2/2] arm64: imx8mp: imx8mp-phycore-som enable spi nor Heiko Schocher
2021-03-08 7:46 ` Teresa Remmet
2021-03-08 8:03 ` Marco Felsch
2021-03-08 8:40 ` Marco Felsch [this message]
2021-03-08 8:52 ` Teresa Remmet
2021-03-08 9:28 ` Marco Felsch
2021-03-08 9:55 ` Heiko Schocher
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