[PATCH 0/4] AM64x HwSpinlock and Mailbox DT nodes

[PATCH 0/4] AM64x HwSpinlock and Mailbox DT nodes

[Suman Anna]

Hi Nishanth,

The following series adds the HwSpinlock and Mailbox DT nodes for
AM64x SoCs on AM64x-EVM and AM64x-SK boards. The bindings for both
drivers were merged in 5.12-rc1.

Patches are based on top of your latest ti-k3-dts-next branch,
commit 04a80a75baa1 ("arm64: dts: ti: k3-am642-evm: Add USB support").

Following is the patch summary:
 - Patch 1 adds the HwSpinlock node
 - Patch 2 adds all the relevant Mailbox clusters that generate
   interrupts towards A53
 - Patches 3 and 4 add the actual communication sub-mailbox devices
   and disables unused clusters for AM64x EVM and AM64x SK boards
   respectively.

Boot Logs:
1. AM64x EVM: https://pastebin.ubuntu.com/p/JMxrqr2zQN/
2. AM64x SK: https://pastebin.ubuntu.com/p/rJcyXvD9hV/

regards
Suman

Suman Anna (4):
  arm64: dts: ti: k3-am64-main: Add hwspinlock node
  arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes
  arm64: dts: ti: k3-am642-evm: Add IPC sub-mailbox nodes
  arm64: dts: ti: k3-am642-sk: Add IPC sub-mailbox nodes

 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 64 ++++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-evm.dts  | 43 ++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-sk.dts   | 43 ++++++++++++++++
 3 files changed, 150 insertions(+)

-- 
2.30.1


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[PATCH 1/4] arm64: dts: ti: k3-am64-main: Add hwspinlock node

[Suman Anna]

The AM64x SoC contains a HwSpinlock IP instance that is a minor variant
of the IP on existing TI K3 SoCs such as AM65x, J721E or J7200 SoCs.
Add the DT node for this on AM64x SoCs. The node is present within the
MAIN domain, and is added as a child node under the cbass_main node.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 7e7997e3adff..96a19d4be9d5 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -521,4 +521,10 @@ usb0: usb@f400000{
 			dr_mode = "otg";
 		};
 	};
+
+	hwspinlock: spinlock@2a000000 {
+		compatible = "ti,am64-hwspinlock";
+		reg = <0x00 0x2a000000 0x00 0x1000>;
+		#hwlock-cells = <1>;
+	};
 };
-- 
2.30.1


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[PATCH 2/4] arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes

[Suman Anna]

The AM64 MAIN domain contains a Mailbox IP instance with multiple
clusters, and is a variant of the IP on current AM65x and J721E
SoCs. The AM64x SoC has only 8 clusters with no interrupts routed
to the A53 core on the first 2 clusters. The interrupt outputs
from the IP do not go through any Interrupt Routers and are
hard-wired to each processor, with only couple of interrupts
from each cluster reaching the A53 core.

Add all the Mailbox clusters that generate interrupts towards the
A53 core as their own nodes under the cbass_main node instead of
creating an almost empty parent node for the Mailbox IP and the
clusters as its child nodes. All these nodes are enabled by default
in the base dtsi file, but any cluster that does not define any
child sub-mailbox nodes should be disabled in the corresponding
board dts files.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 58 ++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 96a19d4be9d5..1c8dc531e6d8 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -527,4 +527,62 @@ hwspinlock: spinlock@2a000000 {
 		reg = <0x00 0x2a000000 0x00 0x1000>;
 		#hwlock-cells = <1>;
 	};
+
+	mailbox0_cluster2: mailbox@29020000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29020000 0x00 0x200>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster3: mailbox@29030000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29030000 0x00 0x200>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster4: mailbox@29040000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29040000 0x00 0x200>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster5: mailbox@29050000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29050000 0x00 0x200>;
+		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster6: mailbox@29060000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29060000 0x00 0x200>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
+
+	mailbox0_cluster7: mailbox@29070000 {
+		compatible = "ti,am64-mailbox";
+		reg = <0x00 0x29070000 0x00 0x200>;
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <1>;
+		ti,mbox-num-users = <4>;
+		ti,mbox-num-fifos = <16>;
+	};
 };
-- 
2.30.1


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[PATCH 3/4] arm64: dts: ti: k3-am642-evm: Add IPC sub-mailbox nodes

[Suman Anna]

Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the AM64x SoCs for the AM642 EVM
board. These include the R5F remote processors in the two dual-R5F
clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; and a M4
processor in the MCU safety island.

These sub-mailbox nodes utilize the System Mailbox clusters 2, 4 and 6.
The remaining clusters 3, 5 and 7 are currently not used, and so are
disabled. Clusters 0 and 1 were never added to the dts file as they do
not support interrupts towards the A53 core.

The sub-mailbox nodes added match the hard-coded mailbox configuration
used within the TI RTOS IPC software packages. The R5F processor
sub-systems are assumed to be running in Split mode, so a sub-mailbox
node is used by each of the R5F cores. Only the sub-mailbox node for
the first R5F core in each cluster is used in case of a Single-CPU mode
for that R5F cluster.

NOTE:
The cluster nodes only have the Mailbox IP interrupt outputs that are
routed to the GIC_SPI. The sub-mailbox nodes' irq-id are indexing into
the listed interrupts, with the usr-id using the actual interrupt output
line number from the Mailbox IP.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am642-evm.dts | 43 +++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 1365e3164294..6dbd84a96a8d 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -377,3 +377,46 @@ cpsw3g_phy0: ethernet-phy@0 {
 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 	};
 };
+
+&mailbox0_cluster2 {
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster3 {
+	status = "disabled";
+};
+
+&mailbox0_cluster4 {
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	mbox_m4_0: mbox-m4-0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
-- 
2.30.1


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[PATCH 4/4] arm64: dts: ti: k3-am642-sk: Add IPC sub-mailbox nodes

[Suman Anna]

Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the AM64x SoCs for the AM642 SK
board. These include the R5F remote processors in the two dual-R5F
clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; and a M4
processor in the MCU safety island.

These sub-mailbox nodes utilize the System Mailbox clusters 2, 4 and 6.
The remaining clusters 3, 5 and 7 are currently not used, and so are
disabled. Clusters 0 and 1 were never added to the dts file as they do
not support interrupts towards the A53 core.

The sub-mailbox nodes added match the hard-coded mailbox configuration
used within the TI RTOS IPC software packages. The R5F processor
sub-systems are assumed to be running in Split mode, so a sub-mailbox
node is used by each of the R5F cores. Only the sub-mailbox node for
the first R5F core in each cluster is used in case of a Single-CPU mode
for that R5F cluster. The nodes are all identical to those added on the
AM64x EVM board to maintain firmware compatibility between the two boards.

NOTE:
The cluster nodes only have the Mailbox IP interrupt outputs that are
routed to the GIC_SPI. The sub-mailbox nodes' irq-id are indexing into
the listed interrupts, with the usr-id using the actual interrupt output
line number from the Mailbox IP.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am642-sk.dts | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 397ed3b2e121..fad0cddd67d6 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -244,3 +244,46 @@ cpsw3g_phy1: ethernet-phy@1 {
 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 	};
 };
+
+&mailbox0_cluster2 {
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster3 {
+	status = "disabled";
+};
+
+&mailbox0_cluster4 {
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 2>;
+		ti,mbox-tx = <3 0 2>;
+	};
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	mbox_m4_0: mbox-m4-0 {
+		ti,mbox-rx = <0 0 2>;
+		ti,mbox-tx = <1 0 2>;
+	};
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
-- 
2.30.1


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Re: [PATCH 0/4] AM64x HwSpinlock and Mailbox DT nodes

[Gowtham Tammana]

> Hi Nishanth,
>
> The following series adds the HwSpinlock and Mailbox DT nodes for
> AM64x SoCs on AM64x-EVM and AM64x-SK boards. The bindings for both
> drivers were merged in 5.12-rc1.
>
> Patches are based on top of your latest ti-k3-dts-next branch,
> commit 04a80a75baa1 ("arm64: dts: ti: k3-am642-evm: Add USB support").
>
> Following is the patch summary:
>  - Patch 1 adds the HwSpinlock node
>  - Patch 2 adds all the relevant Mailbox clusters that generate
>    interrupts towards A53
>  - Patches 3 and 4 add the actual communication sub-mailbox devices
>    and disables unused clusters for AM64x EVM and AM64x SK boards
>    respectively.
>
> Boot Logs:
> 1. AM64x EVM: https://pastebin.ubuntu.com/p/JMxrqr2zQN/
> 2. AM64x SK: https://pastebin.ubuntu.com/p/rJcyXvD9hV/
>
> regards
> Suman
>
> Suman Anna (4):
>   arm64: dts: ti: k3-am64-main: Add hwspinlock node
>   arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes
>   arm64: dts: ti: k3-am642-evm: Add IPC sub-mailbox nodes
>   arm64: dts: ti: k3-am642-sk: Add IPC sub-mailbox nodes
>
>  arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 64 ++++++++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am642-evm.dts  | 43 ++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am642-sk.dts   | 43 ++++++++++++++++
>  3 files changed, 150 insertions(+)

I don't see any issues with this patchset, and dtbs_check reports no errors.

Reviewed-by: Gowtham Tammana <g-tammana@ti.com>

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Re: [PATCH 0/4] AM64x HwSpinlock and Mailbox DT nodes

[Nishanth Menon]

On 18:09-20210317, Suman Anna wrote:
> Hi Nishanth,
> 
> The following series adds the HwSpinlock and Mailbox DT nodes for
> AM64x SoCs on AM64x-EVM and AM64x-SK boards. The bindings for both
> drivers were merged in 5.12-rc1.
> 
> Patches are based on top of your latest ti-k3-dts-next branch,
> commit 04a80a75baa1 ("arm64: dts: ti: k3-am642-evm: Add USB support").

yep, you'd be next in the queue here, so if you dont mind rebasing one
last time, it will help. Also in the repost, please address the
following comment.

> 
> 
> Suman Anna (4):
>   arm64: dts: ti: k3-am64-main: Add hwspinlock node
>   arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes
>   arm64: dts: ti: k3-am642-evm: Add IPC sub-mailbox nodes
>   arm64: dts: ti: k3-am642-sk: Add IPC sub-mailbox nodes

	please squash patches 3,4.



-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH 0/4] AM64x HwSpinlock and Mailbox DT nodes

[Suman Anna]

Hi Nishanth,

On 3/22/21 12:24 PM, Nishanth Menon wrote:
> On 18:09-20210317, Suman Anna wrote:
>> Hi Nishanth,
>>
>> The following series adds the HwSpinlock and Mailbox DT nodes for
>> AM64x SoCs on AM64x-EVM and AM64x-SK boards. The bindings for both
>> drivers were merged in 5.12-rc1.
>>
>> Patches are based on top of your latest ti-k3-dts-next branch,
>> commit 04a80a75baa1 ("arm64: dts: ti: k3-am642-evm: Add USB support").
> 
> yep, you'd be next in the queue here, so if you dont mind rebasing one
> last time, it will help. Also in the repost, please address the
> following comment.
> 
>>
>>
>> Suman Anna (4):
>>   arm64: dts: ti: k3-am64-main: Add hwspinlock node
>>   arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes
>>   arm64: dts: ti: k3-am642-evm: Add IPC sub-mailbox nodes
>>   arm64: dts: ti: k3-am642-sk: Add IPC sub-mailbox nodes
> 
> 	please squash patches 3,4.

Hmm, I prefer to not mix or combine stuff that affects more than a single board.
This is not a bug fix, so, if you don't mind, I would like to keep these as is.

regards
Suman

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Re: [PATCH 0/4] AM64x HwSpinlock and Mailbox DT nodes

[Nishanth Menon]

On 12:34-20210322, Suman Anna wrote:
> Hi Nishanth,
> 
> On 3/22/21 12:24 PM, Nishanth Menon wrote:
> > On 18:09-20210317, Suman Anna wrote:
> >> Hi Nishanth,
> >>
> >> The following series adds the HwSpinlock and Mailbox DT nodes for
> >> AM64x SoCs on AM64x-EVM and AM64x-SK boards. The bindings for both
> >> drivers were merged in 5.12-rc1.
> >>
> >> Patches are based on top of your latest ti-k3-dts-next branch,
> >> commit 04a80a75baa1 ("arm64: dts: ti: k3-am642-evm: Add USB support").
> > 
> > yep, you'd be next in the queue here, so if you dont mind rebasing one
> > last time, it will help. Also in the repost, please address the
> > following comment.
> > 
> >>
> >>
> >> Suman Anna (4):
> >>   arm64: dts: ti: k3-am64-main: Add hwspinlock node
> >>   arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes
> >>   arm64: dts: ti: k3-am642-evm: Add IPC sub-mailbox nodes
> >>   arm64: dts: ti: k3-am642-sk: Add IPC sub-mailbox nodes
> > 
> > 	please squash patches 3,4.
> 
> Hmm, I prefer to not mix or combine stuff that affects more than a single board.
> This is not a bug fix, so, if you don't mind, I would like to keep these as is.

Lets stay consistent with patches I have been consolidating, I
see no reason to add to a patch count here.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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