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From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de
Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
	p.zabel@pengutronix.de, l.stach@pengutronix.de, krzk@kernel.org,
	agx@sigxcpu.org, marex@denx.de, andrew.smirnov@gmail.com,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, ping.bai@nxp.com,
	frieder.schrempf@kontron.de, aford173@gmail.com,
	abel.vesa@nxp.com, Peng Fan <peng.fan@nxp.com>
Subject: [PATCH V2 04/13] soc: imx: gpcv2: split power up and power down sequence control
Date: Thu,  6 May 2021 09:04:31 +0800	[thread overview]
Message-ID: <20210506010440.7016-5-peng.fan@oss.nxp.com> (raw)
In-Reply-To: <20210506010440.7016-1-peng.fan@oss.nxp.com>

From: Lucas Stach <l.stach@pengutronix.de>

The current mixed function to control both power up and power down
sequences is very hard to follow and already contains some sequence
errors like triggering the ADB400 handshake at the wrong time due to
this. Split the function into two, which results in slightly more
code, but is way easier to get right.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/soc/imx/gpcv2.c | 141 ++++++++++++++++++++++++----------------
 1 file changed, 86 insertions(+), 55 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 4222b6e87e7c..bcf1f338b0bf 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -125,20 +125,19 @@ struct imx_pgc_domain_data {
 	const struct regmap_access_table *reg_access_table;
 };
 
-static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
-				      bool on)
+static inline struct imx_pgc_domain *
+to_imx_pgc_domain(struct generic_pm_domain *genpd)
 {
-	struct imx_pgc_domain *domain = container_of(genpd,
-						      struct imx_pgc_domain,
-						      genpd);
-	unsigned int offset = on ?
-		GPC_PU_PGC_SW_PUP_REQ : GPC_PU_PGC_SW_PDN_REQ;
-	const bool enable_power_control = !on;
-	const bool has_regulator = !IS_ERR(domain->regulator);
-	int i, ret = 0;
-	u32 pxx_req;
-
-	if (has_regulator && on) {
+	return container_of(genpd, struct imx_pgc_domain, genpd);
+}
+
+static int imx_pgc_power_up(struct generic_pm_domain *genpd)
+{
+	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
+	u32 reg_val;
+	int ret;
+
+	if (!IS_ERR(domain->regulator)) {
 		ret = regulator_enable(domain->regulator);
 		if (ret) {
 			dev_err(domain->dev, "failed to enable regulator\n");
@@ -150,69 +149,101 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
 	ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
 	if (ret) {
 		dev_err(domain->dev, "failed to enable reset clocks\n");
-		regulator_disable(domain->regulator);
-		return ret;
+		goto out_regulator_disable;
 	}
 
-	if (enable_power_control)
-		regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
-				   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
-
-	if (domain->bits.hsk)
-		regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
-				   domain->bits.hsk, on ? domain->bits.hsk : 0);
-
-	regmap_update_bits(domain->regmap, offset,
+	/* request the domain to power up */
+	regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
 			   domain->bits.pxx, domain->bits.pxx);
-
 	/*
 	 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
 	 * for PUP_REQ/PDN_REQ bit to be cleared
 	 */
-	ret = regmap_read_poll_timeout(domain->regmap, offset, pxx_req,
-				       !(pxx_req & domain->bits.pxx),
+	ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+				       reg_val, !(reg_val & domain->bits.pxx),
 				       0, USEC_PER_MSEC);
 	if (ret) {
 		dev_err(domain->dev, "failed to command PGC\n");
-		/*
-		 * If we were in a process of enabling a
-		 * domain and failed we might as well disable
-		 * the regulator we just enabled. And if it
-		 * was the opposite situation and we failed to
-		 * power down -- keep the regulator on
-		 */
-		on = !on;
+		goto out_clk_disable;
 	}
 
-	if (enable_power_control)
-		regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
-				   GPC_PGC_CTRL_PCR, 0);
+	/* disable power control */
+	regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+			  GPC_PGC_CTRL_PCR);
+
+	/* request the ADB400 to power up */
+	if (domain->bits.hsk)
+		regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
+				   domain->bits.hsk, domain->bits.hsk);
 
 	/* Disable reset clocks for all devices in the domain */
 	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 
-	if (has_regulator && !on) {
-		int err;
+	return 0;
 
-		err = regulator_disable(domain->regulator);
-		if (err)
-			dev_err(domain->dev,
-				"failed to disable regulator: %d\n", err);
-		/* Preserve earlier error code */
-		ret = ret ?: err;
-	}
+out_clk_disable:
+	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
+out_regulator_disable:
+	if (!IS_ERR(domain->regulator))
+		regulator_disable(domain->regulator);
 
 	return ret;
 }
 
-static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
+static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 {
-	return imx_gpc_pu_pgc_sw_pxx_req(genpd, true);
-}
+	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
+	u32 reg_val;
+	int ret;
 
-static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
-{
-	return imx_gpc_pu_pgc_sw_pxx_req(genpd, false);
+	/* Enable reset clocks for all devices in the domain */
+	ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
+	if (ret) {
+		dev_err(domain->dev, "failed to enable reset clocks\n");
+		return ret;
+	}
+
+	/* request the ADB400 to power down */
+	if (domain->bits.hsk)
+		regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
+				  domain->bits.hsk);
+
+	/* enable power control */
+	regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+			   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+
+	/* request the domain to power down */
+	regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
+			   domain->bits.pxx, domain->bits.pxx);
+	/*
+	 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
+	 * for PUP_REQ/PDN_REQ bit to be cleared
+	 */
+	ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
+				       reg_val, !(reg_val & domain->bits.pxx),
+				       0, USEC_PER_MSEC);
+	if (ret) {
+		dev_err(domain->dev, "failed to command PGC\n");
+		goto out_clk_disable;
+	}
+
+	/* Disable reset clocks for all devices in the domain */
+	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
+
+	if (!IS_ERR(domain->regulator)) {
+		ret = regulator_disable(domain->regulator);
+		if (ret) {
+			dev_err(domain->dev, "failed to disable regulator\n");
+			return ret;
+		}
+	}
+
+	return 0;
+
+out_clk_disable:
+	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
+
+	return ret;
 }
 
 static const struct imx_pgc_domain imx7_pgc_domains[] = {
@@ -590,8 +621,8 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
 
 		domain = pd_pdev->dev.platform_data;
 		domain->regmap = regmap;
-		domain->genpd.power_on  = imx_gpc_pu_pgc_sw_pup_req;
-		domain->genpd.power_off = imx_gpc_pu_pgc_sw_pdn_req;
+		domain->genpd.power_on  = imx_pgc_power_up;
+		domain->genpd.power_off = imx_pgc_power_down;
 
 		pd_pdev->dev.parent = dev;
 		pd_pdev->dev.of_node = np;
-- 
2.30.0


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  parent reply	other threads:[~2021-05-06  0:35 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-06  1:04 [PATCH V2 00/13] soc: imx: gpcv2: support i.MX8MM Peng Fan (OSS)
2021-05-06  1:04 ` [PATCH V2 01/13] soc: imx: gpcv2: move to more ideomatic error handling in probe Peng Fan (OSS)
2021-05-06  1:04 ` [PATCH V2 02/13] soc: imx: gpcv2: move domain mapping to domain driver probe Peng Fan (OSS)
2021-05-06  1:04 ` [PATCH V2 03/13] soc: imx: gpcv2: switch to clk_bulk_* API Peng Fan (OSS)
2021-05-06  6:30   ` Frieder Schrempf
2021-05-06  1:04 ` Peng Fan (OSS) [this message]
2021-05-06  6:36   ` [PATCH V2 04/13] soc: imx: gpcv2: split power up and power down sequence control Frieder Schrempf
2021-05-06  1:04 ` [PATCH V2 05/13] soc: imx: gpcv2: wait for ADB400 handshake Peng Fan (OSS)
2021-05-06  1:04 ` [PATCH V2 06/13] soc: imx: gpcv2: add runtime PM support for power-domains Peng Fan (OSS)
2021-05-06  1:04 ` [PATCH V2 07/13] soc: imx: gpcv2: allow domains without power-sequence control Peng Fan (OSS)
2021-05-06  1:04 ` [PATCH V2 08/13] dt-bindings: imx: gpcv2: add support for optional resets Peng Fan (OSS)
2021-05-06  6:43   ` Frieder Schrempf
2021-05-07 21:16     ` Rob Herring
2021-05-08  0:50       ` Peng Fan
2021-05-06  1:04 ` [PATCH V2 09/13] soc: " Peng Fan (OSS)
2021-05-06  1:04 ` [PATCH V2 10/13] dt-bindings: power: add defines for i.MX8MM power domains Peng Fan (OSS)
2021-05-06  1:04 ` [PATCH V2 11/13] soc: imx: gpcv2: add support " Peng Fan (OSS)
2021-05-06  1:04 ` [PATCH V2 12/13] soc: imx: gpcv2: Add support for missing i.MX8MM VPU/DISPMIX " Peng Fan (OSS)
2021-05-06  1:04 ` [PATCH V2 13/13] soc: imx: gpcv2: move reset assert after requesting domain power up Peng Fan (OSS)
2021-05-06  6:56   ` Frieder Schrempf
2021-05-06  8:32 ` [PATCH V2 00/13] soc: imx: gpcv2: support i.MX8MM Frieder Schrempf
2021-05-19 16:09   ` Frieder Schrempf
2021-05-20 15:16     ` Frieder Schrempf
2021-07-21 20:51       ` Lucas Stach
2021-07-22  6:36         ` Frieder Schrempf
2021-08-04 14:30 ` Ezequiel Garcia
2021-08-09  8:15   ` Lucas Stach
2021-09-03 12:26     ` Benjamin Gaignard
  -- strict thread matches above, loose matches on Subject: below --
2020-11-05 17:44 [PATCH v2 00/13] i.MX8MM power domain support Lucas Stach
2020-11-05 17:44 ` [PATCH v2 04/13] soc: imx: gpcv2: split power up and power down sequence control Lucas Stach

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