From: Guenter Roeck <linux@roeck-us.net>
To: Roger Lu <roger.lu@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Enric Balletbo Serra <eballetbo@gmail.com>,
Kevin Hilman <khilman@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Nicolas Boichat <drinkcat@google.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Fan Chen <fan.chen@mediatek.com>,
HenryC Chen <HenryC.Chen@mediatek.com>,
YT Lee <yt.lee@mediatek.com>,
Xiaoqing Liu <Xiaoqing.Liu@mediatek.com>,
Charles Yang <Charles.Yang@mediatek.com>,
Angus Lin <Angus.Lin@mediatek.com>,
Mark Rutland <mark.rutland@arm.com>, Nishanth Menon <nm@ti.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v16 3/7] soc: mediatek: SVS: introduce MTK SVS engine
Date: Wed, 5 May 2021 21:51:15 -0700 [thread overview]
Message-ID: <20210506045115.GA767398@roeck-us.net> (raw)
In-Reply-To: <20210428065440.3704-4-roger.lu@mediatek.com>
On Wed, Apr 28, 2021 at 02:54:36PM +0800, Roger Lu wrote:
> The Smart Voltage Scaling(SVS) engine is a piece of hardware
> which calculates suitable SVS bank voltages to OPP voltage table.
> Then, DVFS driver could apply those SVS bank voltages to PMIC/Buck
> when receiving OPP_EVENT_ADJUST_VOLTAGE.
>
> Signed-off-by: Roger Lu <roger.lu@mediatek.com>
> ---
> drivers/soc/mediatek/Kconfig | 10 +
> drivers/soc/mediatek/Makefile | 1 +
> drivers/soc/mediatek/mtk-svs.c | 1723 ++++++++++++++++++++++++++++++++
> 3 files changed, 1734 insertions(+)
> create mode 100644 drivers/soc/mediatek/mtk-svs.c
>
[ ... ]
> +
> + svsp_irq = irq_of_parse_and_map(svsp->dev->of_node, 0);
> + ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr,
> + svsp->irqflags, svsp->name, svsp);
0-day reports:
drivers/soc/mediatek/mtk-svs.c:1663:7-32: ERROR:
Threaded IRQ with no primary handler requested without IRQF_ONESHOT
I would be a bit concerned about this. There is no primary (hard)
interrupt handler, meaning the hard interrupt may be re-enabled after
the default hard interrupt handler runs. This might result in endless
interrupts.
Guenter
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next prev parent reply other threads:[~2021-05-06 4:56 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-28 6:54 [PATCH v16 0/7] soc: mediatek: SVS: introduce MTK SVS Roger Lu
2021-04-28 6:54 ` [PATCH v16 1/7] dt-bindings: soc: mediatek: add mtk svs dt-bindings Roger Lu
2021-04-28 6:54 ` [PATCH v16 2/7] arm64: dts: mt8183: add svs device information Roger Lu
2021-10-20 15:20 ` AngeloGioacchino Del Regno
2021-12-24 7:33 ` Roger Lu
2021-12-30 12:54 ` Matthias Brugger
2022-01-03 6:08 ` Roger Lu
2021-04-28 6:54 ` [PATCH v16 3/7] soc: mediatek: SVS: introduce MTK SVS engine Roger Lu
2021-05-06 4:51 ` Guenter Roeck [this message]
2021-05-14 3:10 ` Roger Lu
2021-05-14 3:33 ` Guenter Roeck
2021-05-14 5:58 ` Roger Lu
2021-10-21 8:46 ` AngeloGioacchino Del Regno
2021-12-24 9:27 ` Roger Lu
2021-12-24 9:34 ` AngeloGioacchino Del Regno
2021-04-28 6:54 ` [PATCH v16 4/7] soc: mediatek: SVS: add debug commands Roger Lu
2021-10-21 8:52 ` AngeloGioacchino Del Regno
2021-12-24 9:38 ` Roger Lu
2021-04-28 6:54 ` [PATCH v16 5/7] dt-bindings: soc: mediatek: add mt8192 svs dt-bindings Roger Lu
2021-04-28 6:54 ` [PATCH v16 6/7] arm64: dts: mt8192: add svs device information Roger Lu
2021-10-20 15:16 ` AngeloGioacchino Del Regno
2021-12-24 9:42 ` Roger Lu
2021-10-20 15:18 ` AngeloGioacchino Del Regno
2021-04-28 6:54 ` [PATCH v16 7/7] soc: mediatek: SVS: add mt8192 SVS GPU driver Roger Lu
2021-05-14 3:20 ` YT Lee
2021-10-21 9:08 ` AngeloGioacchino Del Regno
2021-12-30 13:18 ` [PATCH v16 0/7] soc: mediatek: SVS: introduce MTK SVS Matthias Brugger
2022-01-03 7:43 ` Roger Lu
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