linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: Mark Brown <broonie@kernel.org>
To: Dave Martin <Dave.Martin@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 3/3] arm64/sve: Skip flushing Z registers with 128 bit vectors
Date: Wed, 12 May 2021 15:22:32 +0100	[thread overview]
Message-ID: <20210512142232.GC6343@sirena.org.uk> (raw)
In-Reply-To: <20210512134909.GF4187@arm.com>


[-- Attachment #1.1: Type: text/plain, Size: 825 bytes --]

On Wed, May 12, 2021 at 02:49:09PM +0100, Dave Martin wrote:
> On Tue, May 11, 2021 at 05:04:46PM +0100, Mark Brown wrote:

> > +/*
> > + * Zero all SVE registers but the first 128-bits of each vector
> > + *
> > + * x0 = VQ - 1

> This does require that ZCR_EL1.LEN has already been set to match x0, and
> is not changed again before entering userspace.

> It would be a good idea to at least describe this in a comment so that
> this doesn't get forgotten later on, but there's a limit to how
> foolproof this low-level backend code needs to be...

Similar concerns exist for huge chunks of the existing SVE code (eg, the
no further changes on vector length constraint is pretty much universal
and is I'd say largely more of a "make sure you handle the register
contents" thing on anything that changes the vector length).

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-05-12 14:24 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-11 16:04 [PATCH v2 0/3] arm64/sve: Trivial optimisation for 128 bit SVE vectors Mark Brown
2021-05-11 16:04 ` [PATCH v2 1/3] arm64/sve: Split _sve_flush macro into separate Z and predicate flushes Mark Brown
2021-05-12 13:40   ` Dave Martin
2021-05-11 16:04 ` [PATCH v2 2/3] arm64/sve: Use the sve_flush macros in sve_load_from_fpsimd_state() Mark Brown
2021-05-12 13:40   ` Dave Martin
2021-05-11 16:04 ` [PATCH v2 3/3] arm64/sve: Skip flushing Z registers with 128 bit vectors Mark Brown
2021-05-12 13:49   ` Dave Martin
2021-05-12 14:22     ` Mark Brown [this message]
2021-05-12 16:16 ` [PATCH v2 0/3] arm64/sve: Trivial optimisation for 128 bit SVE vectors Catalin Marinas

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210512142232.GC6343@sirena.org.uk \
    --to=broonie@kernel.org \
    --cc=Dave.Martin@arm.com \
    --cc=catalin.marinas@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).