From: Kishon Vijay Abraham I <kishon@ti.com>
To: Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>,
Rob Herring <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Lokesh Vutla <lokeshvutla@ti.com>
Subject: [PATCH 3/4] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES
Date: Wed, 12 May 2021 20:42:08 +0530 [thread overview]
Message-ID: <20210512151209.27560-4-kishon@ti.com> (raw)
In-Reply-To: <20210512151209.27560-1-kishon@ti.com>
Use external clock for all the SERDES used by PCIe controller. This will
make the same clock used by the local SERDES as well as the clock
provided to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../dts/ti/k3-j721e-common-proc-board.dts | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 86f7ab511ee8..1b25a5ae9635 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
/ {
chosen {
@@ -639,7 +640,40 @@
clock-frequency = <100000000>;
};
+&wiz0_pll1_refclk {
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz0_refclk_dig {
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_pll1_refclk {
+ assigned-clocks = <&wiz1_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_refclk_dig {
+ assigned-clocks = <&wiz1_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_pll1_refclk {
+ assigned-clocks = <&wiz2_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_refclk_dig {
+ assigned-clocks = <&wiz2_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
&serdes0 {
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
+
serdes0_pcie_link: link@0 {
reg = <0>;
cdns,num-lanes = <1>;
@@ -650,6 +684,9 @@
};
&serdes1 {
+ assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz1_pll1_refclk>;
+
serdes1_pcie_link: link@0 {
reg = <0>;
cdns,num-lanes = <2>;
@@ -660,6 +697,9 @@
};
&serdes2 {
+ assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz2_pll1_refclk>;
+
serdes2_pcie_link: link@0 {
reg = <0>;
cdns,num-lanes = <2>;
--
2.17.1
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next prev parent reply other threads:[~2021-05-12 15:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-12 15:12 [PATCH 0/4] J721E: Use external clock in EVM for SERDES Kishon Vijay Abraham I
2021-05-12 15:12 ` [PATCH 1/4] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES Kishon Vijay Abraham I
2021-05-12 18:51 ` Nishanth Menon
2021-05-13 12:11 ` Kishon Vijay Abraham I
2021-05-13 14:01 ` Nishanth Menon
2021-05-17 8:30 ` Kishon Vijay Abraham I
2021-05-17 14:05 ` Nishanth Menon
2021-05-20 13:18 ` Kishon Vijay Abraham I
2021-05-20 13:41 ` Nishanth Menon
2021-05-12 15:12 ` [PATCH 2/4] arm64: dts: ti: k3-j721e-main: Add #clock-cells property to serdes DT node Kishon Vijay Abraham I
2021-05-12 15:12 ` Kishon Vijay Abraham I [this message]
2021-05-12 15:12 ` [PATCH 4/4] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy" Kishon Vijay Abraham I
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