[PATCH 0/3] Add crypto nodes for J7200 and AM64x

[PATCH 0/3] Add crypto nodes for J7200 and AM64x

[Suman Anna]

Hi Nishanth,

The following series adds the crypto nodes including the underlying
rng nodes for J7200 and AM64x SoCs. Patches are on top of 5.13-rc1.

Note that AM64x supports only a limited number of algos compared to
the other K3 SoCs. The AM64x driver support accounting for this is
merged in v5.13-rc1. Also, the IP appears at the same address on
J7200 and AM64x but is in different domains.

I have verified the basic crypto self-tests, extra-tests and some
basic tcrypt tests on both J7200 EVM and AM64x EVM boards.

regards
Suman

Peter Ujfalusi (2):
  arm64: dts: ti: k3-j7200-mcu: Add the mcu sa2ul crypto node
  arm64: dts: ti: k3-am64-main: Enable crypto accelerator

Suman Anna (1):
  arm64: dts: ti: k3-am64: Add SA2UL address space to Main CBASS ranges

 arch/arm64/boot/dts/ti/k3-am64-main.dtsi      | 19 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am64.dtsi           |  1 +
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 20 +++++++++++++++++++
 3 files changed, 40 insertions(+)

-- 
2.30.1


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[PATCH 1/3] arm64: dts: ti: k3-j7200-mcu: Add the mcu sa2ul crypto node

[Suman Anna]

From: Peter Ujfalusi <peter.ujfalusi@ti.com>

Add sa2ul crypto accelarator node.
In comparision to j721e, The sa2ul crypto device on j7200
has moved to mcu domain and is available for linux usage as
a shared device.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[praneeth@ti.com: picked recommendation from author to
k3-j7200-mcu-wakeup.dtsi and verified functionality]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
[s-anna@ti.com: minor formatting cleanups]
Signed-off-by: Suman Anna <s-anna@ti.com>
---
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 5e74e43822c3..f24bd4af62c8 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -380,4 +380,24 @@ mcu_r5fss0_core1: r5f@41400000 {
 			ti,loczrama = <1>;
 		};
 	};
+
+	mcu_crypto: crypto@40900000 {
+		compatible = "ti,j721e-sa2ul";
+		reg = <0x00 0x40900000 0x00 0x1200>;
+		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+		dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
+		       <&mcu_udmap 0x7503>;
+		dma-names = "tx", "rx1", "rx2";
+		dma-coherent;
+
+		rng: rng@40910000 {
+			compatible = "inside-secure,safexcel-eip76";
+			reg = <0x00 0x40910000 0x00 0x7d>;
+			interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&k3_clks 265 1>;
+		};
+	};
 };
-- 
2.30.1


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[PATCH 2/3] arm64: dts: ti: k3-am64: Add SA2UL address space to Main CBASS ranges

[Suman Anna]

Add the address space for the SA2UL in MAIN domain to the ranges property
of the cbass_main interconnect node so that the addresses within the
corresponding sram nodes and its children can be translated properly by
the relevant OF address API.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
index de6805b0c72c..8ccd03ee3036 100644
--- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
@@ -77,6 +77,7 @@ cbass_main: bus@f4000 {
 			 <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
 			 <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
 			 <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
+			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */
 			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
 			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
 			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
-- 
2.30.1


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[PATCH 3/3] arm64: dts: ti: k3-am64-main: Enable crypto accelerator

[Suman Anna]

From: Peter Ujfalusi <peter.ujfalusi@ti.com>

Add the node for SA2UL including the random number generator.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[s-anna@ti.com: drop label, minor cleanups]
Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index b2bcbf23eefd..43f982291350 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -672,4 +672,23 @@ mailbox0_cluster7: mailbox@29070000 {
 		ti,mbox-num-users = <4>;
 		ti,mbox-num-fifos = <16>;
 	};
+
+	crypto: crypto@40900000 {
+		compatible = "ti,am64-sa2ul";
+		reg = <0x00 0x40900000 0x00 0x1200>;
+		power-domains = <&k3_pds 133 TI_SCI_PD_EXCLUSIVE>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+		dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
+		       <&main_pktdma 0x4003 0>;
+		dma-names = "tx", "rx1", "rx2";
+
+		rng: rng@40910000 {
+			compatible = "inside-secure,safexcel-eip76";
+			reg = <0x00 0x40910000 0x00 0x7d>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&k3_clks 133 0>;
+		};
+	};
 };
-- 
2.30.1


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Re: [PATCH 0/3] Add crypto nodes for J7200 and AM64x

[Nishanth Menon]

On 16:07-20210514, Suman Anna wrote:
> The following series adds the crypto nodes including the underlying
> rng nodes for J7200 and AM64x SoCs. Patches are on top of 5.13-rc1.
> 
> Note that AM64x supports only a limited number of algos compared to
> the other K3 SoCs. The AM64x driver support accounting for this is
> merged in v5.13-rc1. Also, the IP appears at the same address on
> J7200 and AM64x but is in different domains.
> 
> I have verified the basic crypto self-tests, extra-tests and some
> basic tcrypt tests on both J7200 EVM and AM64x EVM boards.
> 

Thanks..

While this is an appropriate description for a subset of hardware,
this maybe missing the pieces needed for certain "high security"
(HS-*) device variants. Public channels, shared data flows and lack of
full control on RNG (we can read RNG, but not seed it) come to mind
immediately and further, I am not completely sure I understand how
this plays well with DKEK with OPTEE.

I know that u-boot does have capability to disable some of these, but:
a) TF-A can definitely boot to linux kernel without the need for u-boot.
b) We still need to be able to leverage h/w acceleration support that
   the high security devices is already capable of.

As a result, I am not entirely sure what we can do with this series
without breaking existing "high-security" devices (which can boot mainline
linux today with TF-A).

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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