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* [PATCH 2/3 v2] crypto: ixp4xx: Add DT bindings
@ 2021-05-20 22:30 Linus Walleij
  2021-05-21 17:27 ` Rob Herring
  0 siblings, 1 reply; 4+ messages in thread
From: Linus Walleij @ 2021-05-20 22:30 UTC (permalink / raw)
  To: linux-crypto, Herbert Xu, David S . Miller, Corentin Labbe
  Cc: linux-arm-kernel, Imre Kaloz, Krzysztof Halasa, Arnd Bergmann,
	Linus Walleij, devicetree

This adds device tree bindings for the ixp4xx crypto engine.

Cc: Corentin Labbe <clabbe@baylibre.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Drop the phandle to self, just add an NPE instance number
  instead.
- Add the crypto node to the NPE binding.
- Move the example over to the NPE binding where it appears
  in context.
---
 .../bindings/crypto/intel,ixp4xx-crypto.yaml  | 46 +++++++++++++++++++
 ...ntel,ixp4xx-network-processing-engine.yaml | 13 +++++-
 2 files changed, 58 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml

diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
new file mode 100644
index 000000000000..79e9d23be1f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2018 Linaro Ltd.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel IXP4xx cryptographic engine
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+  The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
+  (Network Processing Engine). Since it is not a device on its own
+  it is defined as a subnode of the NPE, if crypto support is
+  available on the platform.
+
+properties:
+  compatible:
+    const: intel,ixp4xx-crypto
+
+  intel,npe:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 3
+    description: phandle to the NPE this ethernet instance is using
+      and the instance to use in the second cell
+
+  queue-rx:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+    description: phandle to the RX queue on the NPE
+
+  queue-txready:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+    description: phandle to the TX READY queue on the NPE
+
+required:
+  - compatible
+  - intel,npe
+  - queue-rx
+  - queue-txready
+
+additionalProperties: false
diff --git a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
index 1bd2870c3a9c..add46ae6c461 100644
--- a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
+++ b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
@@ -30,6 +30,10 @@ properties:
       - description: NPE1 register range
       - description: NPE2 register range
 
+  crypto:
+    type: object
+    description: optional node for the embedded crypto engine
+
 required:
   - compatible
   - reg
@@ -38,8 +42,15 @@ additionalProperties: false
 
 examples:
   - |
-    npe@c8006000 {
+    npe: npe@c8006000 {
          compatible = "intel,ixp4xx-network-processing-engine";
          reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+
+         crypto {
+             compatible = "intel,ixp4xx-crypto";
+             intel,npe = <2>;
+             queue-rx = <&qmgr 30>;
+             queue-txready = <&qmgr 29>;
+         };
     };
 ...
-- 
2.31.1


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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 2/3 v2] crypto: ixp4xx: Add DT bindings
  2021-05-20 22:30 [PATCH 2/3 v2] crypto: ixp4xx: Add DT bindings Linus Walleij
@ 2021-05-21 17:27 ` Rob Herring
  2021-05-22 16:26   ` Linus Walleij
  0 siblings, 1 reply; 4+ messages in thread
From: Rob Herring @ 2021-05-21 17:27 UTC (permalink / raw)
  To: Linus Walleij
  Cc: linux-crypto, Herbert Xu, David S . Miller, Corentin Labbe,
	linux-arm-kernel, Imre Kaloz, Krzysztof Halasa, Arnd Bergmann,
	devicetree

On Fri, May 21, 2021 at 12:30:20AM +0200, Linus Walleij wrote:
> This adds device tree bindings for the ixp4xx crypto engine.
> 
> Cc: Corentin Labbe <clabbe@baylibre.com>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ChangeLog v1->v2:
> - Drop the phandle to self, just add an NPE instance number
>   instead.
> - Add the crypto node to the NPE binding.
> - Move the example over to the NPE binding where it appears
>   in context.
> ---
>  .../bindings/crypto/intel,ixp4xx-crypto.yaml  | 46 +++++++++++++++++++
>  ...ntel,ixp4xx-network-processing-engine.yaml | 13 +++++-
>  2 files changed, 58 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
> 
> diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
> new file mode 100644
> index 000000000000..79e9d23be1f4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2018 Linaro Ltd.
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Intel IXP4xx cryptographic engine
> +
> +maintainers:
> +  - Linus Walleij <linus.walleij@linaro.org>
> +
> +description: |
> +  The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
> +  (Network Processing Engine). Since it is not a device on its own
> +  it is defined as a subnode of the NPE, if crypto support is
> +  available on the platform.
> +
> +properties:
> +  compatible:
> +    const: intel,ixp4xx-crypto
> +
> +  intel,npe:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 3
> +    description: phandle to the NPE this ethernet instance is using

Not a phandle now.

> +      and the instance to use in the second cell

Maybe 'reg' works here? You can only have 1 thing you address though if 
you use reg here.

How are other NPE instances used? Are you going to need to have a 
reference to them?

> +
> +  queue-rx:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +    description: phandle to the RX queue on the NPE

Plus a cell value. What's it for?

> +
> +  queue-txready:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +    description: phandle to the TX READY queue on the NPE

And here.

> +
> +required:
> +  - compatible
> +  - intel,npe
> +  - queue-rx
> +  - queue-txready
> +
> +additionalProperties: false
> diff --git a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
> index 1bd2870c3a9c..add46ae6c461 100644
> --- a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
> +++ b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
> @@ -30,6 +30,10 @@ properties:
>        - description: NPE1 register range
>        - description: NPE2 register range
>  
> +  crypto:
> +    type: object
> +    description: optional node for the embedded crypto engine

$ref: /schemas/crypto/intel,ixp4xx-crypto.yaml#

> +
>  required:
>    - compatible
>    - reg
> @@ -38,8 +42,15 @@ additionalProperties: false
>  
>  examples:
>    - |
> -    npe@c8006000 {
> +    npe: npe@c8006000 {
>           compatible = "intel,ixp4xx-network-processing-engine";
>           reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
> +
> +         crypto {
> +             compatible = "intel,ixp4xx-crypto";
> +             intel,npe = <2>;
> +             queue-rx = <&qmgr 30>;
> +             queue-txready = <&qmgr 29>;
> +         };
>      };
>  ...
> -- 
> 2.31.1
> 

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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 2/3 v2] crypto: ixp4xx: Add DT bindings
  2021-05-21 17:27 ` Rob Herring
@ 2021-05-22 16:26   ` Linus Walleij
  2021-05-24 13:47     ` Rob Herring
  0 siblings, 1 reply; 4+ messages in thread
From: Linus Walleij @ 2021-05-22 16:26 UTC (permalink / raw)
  To: Rob Herring
  Cc: Linux Crypto Mailing List, Herbert Xu, David S . Miller,
	Corentin Labbe, Linux ARM, Imre Kaloz, Krzysztof Halasa,
	Arnd Bergmann,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS

On Fri, May 21, 2021 at 7:27 PM Rob Herring <robh@kernel.org> wrote:

> > +  intel,npe:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    minimum: 0
> > +    maximum: 3
> > +    description: phandle to the NPE this ethernet instance is using
>
> Not a phandle now.
>
> > +      and the instance to use in the second cell
>
> Maybe 'reg' works here? You can only have 1 thing you address though if
> you use reg here.

Good idea, I'll try that.

> How are other NPE instances used? Are you going to need to have a
> reference to them?

They are used by phandle from the combined ethernet and phy
instances. They are accelerators with firmware which have direct
access to the ethernet and phy port, and one of the NPE:s can
additionally contain a crypto engine.

Yours,
Linus Walleij

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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 2/3 v2] crypto: ixp4xx: Add DT bindings
  2021-05-22 16:26   ` Linus Walleij
@ 2021-05-24 13:47     ` Rob Herring
  0 siblings, 0 replies; 4+ messages in thread
From: Rob Herring @ 2021-05-24 13:47 UTC (permalink / raw)
  To: Linus Walleij
  Cc: Linux Crypto Mailing List, Herbert Xu, David S . Miller,
	Corentin Labbe, Linux ARM, Imre Kaloz, Krzysztof Halasa,
	Arnd Bergmann,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS

On Sat, May 22, 2021 at 11:26 AM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Fri, May 21, 2021 at 7:27 PM Rob Herring <robh@kernel.org> wrote:
>
> > > +  intel,npe:
> > > +    $ref: /schemas/types.yaml#/definitions/uint32
> > > +    minimum: 0
> > > +    maximum: 3
> > > +    description: phandle to the NPE this ethernet instance is using
> >
> > Not a phandle now.
> >
> > > +      and the instance to use in the second cell
> >
> > Maybe 'reg' works here? You can only have 1 thing you address though if
> > you use reg here.
>
> Good idea, I'll try that.
>
> > How are other NPE instances used? Are you going to need to have a
> > reference to them?
>
> They are used by phandle from the combined ethernet and phy
> instances.

So 'intel,npe' property? Then we should probably just keep that. For
sure, we don't want a given property to have 2 different types. (Some
day I intend to check for that.)

> They are accelerators with firmware which have direct
> access to the ethernet and phy port, and one of the NPE:s can
> additionally contain a crypto engine.

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^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-05-25  0:11 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-05-20 22:30 [PATCH 2/3 v2] crypto: ixp4xx: Add DT bindings Linus Walleij
2021-05-21 17:27 ` Rob Herring
2021-05-22 16:26   ` Linus Walleij
2021-05-24 13:47     ` Rob Herring

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