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From: Andre Przywara <andre.przywara@arm.com>
To: Jaxson Han <jaxson.han@arm.com>
Cc: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org,
	wei.chen@arm.com
Subject: Re: [boot-wrapper PATCH v2 6/8] gic-v3: Prepare for gicv3 with EL2
Date: Mon, 24 May 2021 10:33:14 +0100	[thread overview]
Message-ID: <20210524103314.464c9aab@slackpad.fritz.box> (raw)
In-Reply-To: <20210521104807.138269-7-jaxson.han@arm.com>

On Fri, 21 May 2021 18:48:05 +0800
Jaxson Han <jaxson.han@arm.com> wrote:

Hi,

> This is a preparation for allowing boot-wrapper configuring the gicv3
> with EL2.
> 
> When confiuring with EL2, since there is no ICC_CTLR_EL2, the
> ICC_CTLR_EL3 cannot be replaced with ICC_CTLR_EL2 simply.
> See [https://developer.arm.com/documentation/ihi0069/latest/].
> 
> As the caller, gic_secure_init expects the ICC_CTLR to be written,
> we change the function into gic_init_icc_ctlr(). In the GIC spec,
> the r/w bits in this register ([6:0]) either affect EL3 IRQ routing
> (not applicable since no EL3), non-secure IRQ handling (not applicable
> since only secure state in Armv8-R aarch64), or are aliased to
> ICC_CTLR_EL1 bits.
> So, based on this, the new gic_init_icc_ctlr() would be:
> When currentEL is EL3, init ICC_CTLR_EL3 as before.
> When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET.

Looks good, thanks!

> 
> Signed-off-by: Jaxson Han <jaxson.han@arm.com>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre


> ---
>  arch/aarch32/include/asm/gic-v3.h |  7 ++++++
>  arch/aarch64/include/asm/gic-v3.h | 38 ++++++++++++++++++++++++++++---
>  gic-v3.c                          |  2 +-
>  3 files changed, 43 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h
> index ec9a327..86abe09 100644
> --- a/arch/aarch32/include/asm/gic-v3.h
> +++ b/arch/aarch32/include/asm/gic-v3.h
> @@ -9,6 +9,8 @@
>  #ifndef __ASM_AARCH32_GICV3_H
>  #define __ASM_AARCH32_GICV3_H
>  
> +#define ICC_CTLR_RESET	(0UL)
> +
>  static inline uint32_t gic_read_icc_sre(void)
>  {
>  	uint32_t val;
> @@ -26,4 +28,9 @@ static inline void gic_write_icc_ctlr(uint32_t val)
>  	asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val));
>  }
>  
> +static inline void gic_init_icc_ctlr()
> +{
> +	gic_write_icc_ctlr(ICC_CTLR_RESET);
> +}
> +
>  #endif
> diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h
> index e743c02..b3dfbd3 100644
> --- a/arch/aarch64/include/asm/gic-v3.h
> +++ b/arch/aarch64/include/asm/gic-v3.h
> @@ -15,21 +15,53 @@
>  #define ICC_CTLR_EL3	"S3_6_C12_C12_4"
>  #define ICC_PMR_EL1	"S3_0_C4_C6_0"
>  
> +#define ICC_CTLR_EL3_RESET	(0UL)
> +#define ICC_CTLR_EL1_RESET	(0UL)
> +
> +static inline uint32_t current_el(void)
> +{
> +	uint32_t val;
> +
> +	asm volatile ("mrs %0, CurrentEL" : "=r" (val));
> +	return val;
> +}
> +
>  static inline uint32_t gic_read_icc_sre(void)
>  {
>  	uint32_t val;
> -	asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
> +
> +	if(current_el() == CURRENTEL_EL3)
> +		asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
> +	else
> +		asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val));
> +
>  	return val;
>  }
>  
>  static inline void gic_write_icc_sre(uint32_t val)
>  {
> -	asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
> +	if(current_el() == CURRENTEL_EL3)
> +		asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
> +	else
> +		asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val));
>  }
>  
> -static inline void gic_write_icc_ctlr(uint32_t val)
> +static inline void gic_write_icc_ctlr_el3(uint32_t val)
>  {
>  	asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));
>  }
>  
> +static inline void gic_write_icc_ctlr_el1(uint32_t val)
> +{
> +	asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (val));
> +}
> +
> +static inline void gic_init_icc_ctlr()
> +{
> +	if(current_el() == CURRENTEL_EL3)
> +		gic_write_icc_ctlr_el3(ICC_CTLR_EL3_RESET);
> +	else
> +		gic_write_icc_ctlr_el1(ICC_CTLR_EL1_RESET);
> +}
> +
>  #endif
> diff --git a/gic-v3.c b/gic-v3.c
> index ae2d2bc..4850572 100644
> --- a/gic-v3.c
> +++ b/gic-v3.c
> @@ -121,6 +121,6 @@ void gic_secure_init(void)
>  	gic_write_icc_sre(sre);
>  	isb();
>  
> -	gic_write_icc_ctlr(0);
> +	gic_init_icc_ctlr();
>  	isb();
>  }


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  reply	other threads:[~2021-05-24 18:55 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-21 10:47 [boot-wrapper PATCH v2 0/8] Add Armv8-R AArch64 support Jaxson Han
2021-05-21 10:48 ` [boot-wrapper PATCH v2 1/8] Decouple V2M_SYS config by auto-detect dtb node Jaxson Han
2021-05-21 10:48 ` [boot-wrapper PATCH v2 2/8] aarch64: Rename labels and prepare for lower EL booting Jaxson Han
2021-05-24  9:32   ` Andre Przywara
2021-05-25  1:54     ` Jaxson Han
2021-05-21 10:48 ` [boot-wrapper PATCH v2 3/8] aarch64: Remove the redundant setup_stack Jaxson Han
2021-05-24  9:32   ` Andre Przywara
2021-05-21 10:48 ` [boot-wrapper PATCH v2 4/8] aarch64: Prepare for EL1 booting Jaxson Han
2021-05-24  9:32   ` Andre Przywara
2021-05-21 10:48 ` [boot-wrapper PATCH v2 5/8] aarch64: Prepare for lower EL booting Jaxson Han
2021-05-24  9:33   ` Andre Przywara
2021-05-21 10:48 ` [boot-wrapper PATCH v2 6/8] gic-v3: Prepare for gicv3 with EL2 Jaxson Han
2021-05-24  9:33   ` Andre Przywara [this message]
2021-05-21 10:48 ` [boot-wrapper PATCH v2 7/8] aarch64: Prepare for booting " Jaxson Han
2021-05-24  9:33   ` Andre Przywara
2021-05-21 10:48 ` [boot-wrapper PATCH v2 8/8] aarch64: Introduce EL2 boot code for Armv8-R AArch64 Jaxson Han
2021-05-24 10:19   ` Andre Przywara
2021-05-25  1:59     ` Jaxson Han

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