* [PATCH v2 0/2] arm64: Taint the kernel on different GMID_EL1.BS
@ 2021-05-26 19:36 Catalin Marinas
2021-05-26 19:36 ` [PATCH v2 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64 Catalin Marinas
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Catalin Marinas @ 2021-05-26 19:36 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Will Deacon, Mark Rutland, Suzuki K Poulose
Hi,
An updated version of the GMID_EL1.BS sanity check since the first one
broke the boot on CPUs not supporting MTE.
Changes since v1 [1]:
- Add an id_aa64pfr1_mte() function to check whether the CPU supports
MTE before reading the GMID_EL1 register and updating the sanitised
one
- Dropped Mark's ack on the second patch because of the changes.
[1] https://lore.kernel.org/r/20210511182322.3830-1-catalin.marinas@arm.com
Catalin Marinas (2):
arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
arm64: Check if GMID_EL1.BS is the same on all CPUs
arch/arm64/include/asm/cpu.h | 11 ++++++-----
arch/arm64/include/asm/cpufeature.h | 7 +++++++
arch/arm64/kernel/cpufeature.c | 21 +++++++++++++++++++++
arch/arm64/kernel/cpuinfo.c | 5 ++++-
4 files changed, 38 insertions(+), 6 deletions(-)
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
2021-05-26 19:36 [PATCH v2 0/2] arm64: Taint the kernel on different GMID_EL1.BS Catalin Marinas
@ 2021-05-26 19:36 ` Catalin Marinas
2021-05-26 19:36 ` [PATCH v2 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs Catalin Marinas
2021-05-26 22:15 ` [PATCH v2 0/2] arm64: Taint the kernel on different GMID_EL1.BS Will Deacon
2 siblings, 0 replies; 4+ messages in thread
From: Catalin Marinas @ 2021-05-26 19:36 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Will Deacon, Mark Rutland, Suzuki K Poulose
The architecture has been updated and the CTR_EL0, CNTFRQ_EL0,
DCZID_EL0, MIDR_EL1, REVIDR_EL1 registers are all 64-bit, even if most
of them have a RES0 top 32-bit.
Change their type to u64 in struct cpuinfo_arm64.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Suzuki K Poulose <Suzuki.Poulose@arm.com>
---
arch/arm64/include/asm/cpu.h | 10 +++++-----
arch/arm64/kernel/cpuinfo.c | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index 7faae6ff3ab4..fe5a8499ddc2 100644
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -15,11 +15,11 @@
struct cpuinfo_arm64 {
struct cpu cpu;
struct kobject kobj;
- u32 reg_ctr;
- u32 reg_cntfrq;
- u32 reg_dczid;
- u32 reg_midr;
- u32 reg_revidr;
+ u64 reg_ctr;
+ u64 reg_cntfrq;
+ u64 reg_dczid;
+ u64 reg_midr;
+ u64 reg_revidr;
u64 reg_id_aa64dfr0;
u64 reg_id_aa64dfr1;
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 51fcf99d5351..0e9e965e18d8 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -246,7 +246,7 @@ static struct kobj_type cpuregs_kobj_type = {
struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
\
if (info->reg_midr) \
- return sprintf(buf, "0x%016x\n", info->reg_##_field); \
+ return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
else \
return 0; \
} \
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs
2021-05-26 19:36 [PATCH v2 0/2] arm64: Taint the kernel on different GMID_EL1.BS Catalin Marinas
2021-05-26 19:36 ` [PATCH v2 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64 Catalin Marinas
@ 2021-05-26 19:36 ` Catalin Marinas
2021-05-26 22:15 ` [PATCH v2 0/2] arm64: Taint the kernel on different GMID_EL1.BS Will Deacon
2 siblings, 0 replies; 4+ messages in thread
From: Catalin Marinas @ 2021-05-26 19:36 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Will Deacon, Mark Rutland, Suzuki K Poulose
The GMID_EL1.BS field determines the number of tags accessed by the
LDGM/STGM instructions (EL1 and up), used by the kernel for copying or
zeroing page tags.
Taint the kernel if GMID_EL1.BS differs between CPUs but only of
CONFIG_ARM64_MTE is enabled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
---
arch/arm64/include/asm/cpu.h | 1 +
arch/arm64/include/asm/cpufeature.h | 7 +++++++
arch/arm64/kernel/cpufeature.c | 21 +++++++++++++++++++++
arch/arm64/kernel/cpuinfo.c | 3 +++
4 files changed, 32 insertions(+)
diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index fe5a8499ddc2..9088e72c7cf6 100644
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -20,6 +20,7 @@ struct cpuinfo_arm64 {
u64 reg_dczid;
u64 reg_midr;
u64 reg_revidr;
+ u64 reg_gmid;
u64 reg_id_aa64dfr0;
u64 reg_id_aa64dfr1;
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 338840c00e8e..650de920e067 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -619,6 +619,13 @@ static inline bool id_aa64pfr0_sve(u64 pfr0)
return val > 0;
}
+static inline bool id_aa64pfr1_mte(u64 pfr1)
+{
+ u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_MTE_SHIFT);
+
+ return val >= ID_AA64PFR1_MTE;
+}
+
void __init setup_cpu_features(void);
void check_local_cpu_capabilities(void);
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index efed2830d141..0645300cc1a8 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -400,6 +400,11 @@ static const struct arm64_ftr_bits ftr_dczid[] = {
ARM64_FTR_END,
};
+static const struct arm64_ftr_bits ftr_gmid[] = {
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
+ ARM64_FTR_END,
+};
+
static const struct arm64_ftr_bits ftr_id_isar0[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
@@ -617,6 +622,9 @@ static const struct __ftr_reg_entry {
/* Op1 = 0, CRn = 1, CRm = 2 */
ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
+ /* Op1 = 1, CRn = 0, CRm = 0 */
+ ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
+
/* Op1 = 3, CRn = 0, CRm = 0 */
{ SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
@@ -911,6 +919,9 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
sve_init_vq_map();
}
+ if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
+ init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
+
/*
* Initialize the indirect array of CPU hwcaps capabilities pointers
* before we handle the boot CPU below.
@@ -1134,6 +1145,16 @@ void update_cpu_features(int cpu,
sve_update_vq_map();
}
+ /*
+ * The kernel uses the LDGM/STGM instructions and the number of tags
+ * they read/write depends on the GMID_EL1.BS field. Check that the
+ * value is the same on all CPUs.
+ */
+ if (IS_ENABLED(CONFIG_ARM64_MTE) &&
+ id_aa64pfr1_mte(info->reg_id_aa64pfr1))
+ taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
+ info->reg_gmid, boot->reg_gmid);
+
/*
* This relies on a sanitised view of the AArch64 ID registers
* (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 0e9e965e18d8..5321b8218591 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -371,6 +371,9 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
+ if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
+ info->reg_gmid = read_cpuid(GMID_EL1);
+
/* Update the 32bit ID registers only if AArch32 is implemented */
if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2 0/2] arm64: Taint the kernel on different GMID_EL1.BS
2021-05-26 19:36 [PATCH v2 0/2] arm64: Taint the kernel on different GMID_EL1.BS Catalin Marinas
2021-05-26 19:36 ` [PATCH v2 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64 Catalin Marinas
2021-05-26 19:36 ` [PATCH v2 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs Catalin Marinas
@ 2021-05-26 22:15 ` Will Deacon
2 siblings, 0 replies; 4+ messages in thread
From: Will Deacon @ 2021-05-26 22:15 UTC (permalink / raw)
To: linux-arm-kernel, Catalin Marinas
Cc: kernel-team, Will Deacon, Mark Rutland, Suzuki K Poulose
On Wed, 26 May 2021 20:36:19 +0100, Catalin Marinas wrote:
> An updated version of the GMID_EL1.BS sanity check since the first one
> broke the boot on CPUs not supporting MTE.
>
> Changes since v1 [1]:
>
> - Add an id_aa64pfr1_mte() function to check whether the CPU supports
> MTE before reading the GMID_EL1 register and updating the sanitised
> one
>
> [...]
Applied to arm64 (for-next/cpufeature), thanks!
[1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
https://git.kernel.org/arm64/c/7513cc8a1b74
[2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs
https://git.kernel.org/arm64/c/21047e91a5a6
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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2021-05-26 19:36 [PATCH v2 0/2] arm64: Taint the kernel on different GMID_EL1.BS Catalin Marinas
2021-05-26 19:36 ` [PATCH v2 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64 Catalin Marinas
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