From: Leo Yan <leo.yan@linaro.org>
To: Arnaldo Carvalho de Melo <acme@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Andi Kleen <ak@linux.intel.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org
Cc: Leo Yan <leo.yan@linaro.org>
Subject: [PATCH v2 3/8] coresight: tmc-etf: Add comment for store ordering
Date: Wed, 2 Jun 2021 18:30:02 +0800 [thread overview]
Message-ID: <20210602103007.184993-4-leo.yan@linaro.org> (raw)
In-Reply-To: <20210602103007.184993-1-leo.yan@linaro.org>
AUX ring buffer is required to separate the data store and aux_head
store, since the function CS_LOCK() has contained memory barrier mb(),
mb() is a more conservative barrier than smp_wmb() on Arm32/Arm64, thus
it's needless to add any explicit barrier anymore.
Add comment to make clear for the barrier usage for ETF.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 45b85edfc690..9a42ee689921 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -553,6 +553,12 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
if (buf->snapshot)
handle->head += to_read;
+ /*
+ * AUX ring buffer requires to use memory barrier to separate the trace
+ * data store and aux_head store, because CS_LOCK() contains mb() which
+ * gives more heavy barrier than smp_wmb(), it's not necessary to
+ * explicitly invoke any barrier.
+ */
CS_LOCK(drvdata->base);
out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
--
2.25.1
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next prev parent reply other threads:[~2021-06-02 10:33 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-02 10:29 [PATCH v2 0/8] perf: Refine barriers for AUX ring buffer Leo Yan
2021-06-02 10:30 ` [PATCH v2 1/8] perf/ring_buffer: Add comment for barriers on " Leo Yan
2021-06-07 15:27 ` Peter Zijlstra
2021-06-02 10:30 ` [PATCH v2 2/8] coresight: tmc-etr: Add barrier after updating " Leo Yan
2021-06-02 10:30 ` Leo Yan [this message]
2021-06-02 10:30 ` [PATCH v2 4/8] perf/x86: Add barrier after updating bts Leo Yan
2021-06-07 15:29 ` Peter Zijlstra
2021-06-02 10:30 ` [PATCH v2 5/8] perf auxtrace: Change to use SMP memory barriers Leo Yan
2021-06-07 10:02 ` Adrian Hunter
2021-06-07 15:29 ` Peter Zijlstra
2021-06-08 16:45 ` Arnaldo Carvalho de Melo
2021-06-02 10:30 ` [PATCH v2 6/8] perf auxtrace: Drop legacy __sync functions Leo Yan
2021-06-02 10:47 ` Adrian Hunter
2021-06-02 11:16 ` Leo Yan
2021-06-02 11:21 ` Adrian Hunter
2021-06-02 13:01 ` Leo Yan
2021-06-02 10:30 ` [PATCH v2 7/8] perf auxtrace: Use WRITE_ONCE() for updating aux_tail Leo Yan
2021-06-07 10:03 ` Adrian Hunter
2021-06-07 15:31 ` Peter Zijlstra
2021-06-08 17:04 ` Arnaldo Carvalho de Melo
2021-06-09 0:21 ` Leo Yan
2021-06-02 10:30 ` [PATCH v2 8/8] perf record: Directly bail out for compat case Leo Yan
2021-06-02 11:18 ` Adrian Hunter
2021-06-02 12:38 ` Leo Yan
2021-06-07 10:23 ` Adrian Hunter
2021-06-07 15:09 ` Leo Yan
2021-06-09 8:23 ` Adrian Hunter
2021-06-09 8:57 ` Leo Yan
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