From: Peter Zijlstra <peterz@infradead.org>
To: Leo Yan <leo.yan@linaro.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>,
Ingo Molnar <mingo@redhat.com>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Andi Kleen <ak@linux.intel.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 4/8] perf/x86: Add barrier after updating bts
Date: Mon, 7 Jun 2021 17:29:23 +0200 [thread overview]
Message-ID: <YL47U1GyrY0kG06n@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20210602103007.184993-5-leo.yan@linaro.org>
On Wed, Jun 02, 2021 at 06:30:03PM +0800, Leo Yan wrote:
> Add barrier wmb() to separate the AUX data store and aux_head store.
>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
> arch/x86/events/intel/bts.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c
> index 6320d2cfd9d3..4a015d160bc5 100644
> --- a/arch/x86/events/intel/bts.c
> +++ b/arch/x86/events/intel/bts.c
> @@ -209,6 +209,9 @@ static void bts_update(struct bts_ctx *bts)
> } else {
> local_set(&buf->data_size, head);
> }
> +
> + /* The WMB separates data store and aux_head store matches. */
> + wmb();
Alexander, do we indeed need an MFENCE here? or is the BTS hardware
coherent, in which case a compiler barrier would be sufficient.
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next prev parent reply other threads:[~2021-06-07 15:31 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-02 10:29 [PATCH v2 0/8] perf: Refine barriers for AUX ring buffer Leo Yan
2021-06-02 10:30 ` [PATCH v2 1/8] perf/ring_buffer: Add comment for barriers on " Leo Yan
2021-06-07 15:27 ` Peter Zijlstra
2021-06-02 10:30 ` [PATCH v2 2/8] coresight: tmc-etr: Add barrier after updating " Leo Yan
2021-06-02 10:30 ` [PATCH v2 3/8] coresight: tmc-etf: Add comment for store ordering Leo Yan
2021-06-02 10:30 ` [PATCH v2 4/8] perf/x86: Add barrier after updating bts Leo Yan
2021-06-07 15:29 ` Peter Zijlstra [this message]
2021-06-02 10:30 ` [PATCH v2 5/8] perf auxtrace: Change to use SMP memory barriers Leo Yan
2021-06-07 10:02 ` Adrian Hunter
2021-06-07 15:29 ` Peter Zijlstra
2021-06-08 16:45 ` Arnaldo Carvalho de Melo
2021-06-02 10:30 ` [PATCH v2 6/8] perf auxtrace: Drop legacy __sync functions Leo Yan
2021-06-02 10:47 ` Adrian Hunter
2021-06-02 11:16 ` Leo Yan
2021-06-02 11:21 ` Adrian Hunter
2021-06-02 13:01 ` Leo Yan
2021-06-02 10:30 ` [PATCH v2 7/8] perf auxtrace: Use WRITE_ONCE() for updating aux_tail Leo Yan
2021-06-07 10:03 ` Adrian Hunter
2021-06-07 15:31 ` Peter Zijlstra
2021-06-08 17:04 ` Arnaldo Carvalho de Melo
2021-06-09 0:21 ` Leo Yan
2021-06-02 10:30 ` [PATCH v2 8/8] perf record: Directly bail out for compat case Leo Yan
2021-06-02 11:18 ` Adrian Hunter
2021-06-02 12:38 ` Leo Yan
2021-06-07 10:23 ` Adrian Hunter
2021-06-07 15:09 ` Leo Yan
2021-06-09 8:23 ` Adrian Hunter
2021-06-09 8:57 ` Leo Yan
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