[PATCH 0/5] arm64: imx8mn: Add power domain and more peripherals

[PATCH 0/5] arm64: imx8mn: Add power domain and more peripherals

[Adam Ford]

The i.MX8M Nano has a similar power domain controller to that of the
i.MX8M Mini, but it's different enough to require some changes to
both the device tree bindings and to the power domain registers.

This series enables the power domains which don't require blk-ctl
and a few peripherals that also do not require blk-ctl.

V2:  Rebase on Shawn Guo's 5.14 for-next repo where the PGC for
     i.MX8M is alreay appled.

Adam Ford (5):
  dt-bindings: add defines for i.MX8MN power domains
  soc: imx: gpcv2: add support for i.MX8MN power domains
  arm64: dts: imx8mn: add GPC node and power domains
  arm64: dts: imx8mn: Add power-domain reference in USB controller
  arm64: dts: imx8mn: Add GPU node

 .../bindings/power/fsl,imx-gpcv2.yaml         |  1 +
 arch/arm64/boot/dts/freescale/imx8mn.dtsi     | 62 +++++++++++++
 drivers/soc/imx/gpcv2.c                       | 93 +++++++++++++++++++
 include/dt-bindings/power/imx8mn-power.h      | 15 +++
 4 files changed, 171 insertions(+)
 create mode 100644 include/dt-bindings/power/imx8mn-power.h

-- 
2.25.1


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[PATCH 1/5] dt-bindings: add defines for i.MX8MN power domains

[Adam Ford]

The i.MX8M Nano has a similar power domain controller to that of the
mini, but it isn't fully compatible, so it needs a separate binding
and power domain tables.

Add the bindings and tables.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>

diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
index 87b6318bf2b9..01bdda167eef 100644
--- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
+++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
@@ -25,6 +25,7 @@ properties:
   compatible:
     enum:
       - fsl,imx7d-gpc
+      - fsl,imx8mn-gpc
       - fsl,imx8mq-gpc
       - fsl,imx8mm-gpc
 
diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h
new file mode 100644
index 000000000000..102ee85a9b62
--- /dev/null
+++ b/include/dt-bindings/power/imx8mn-power.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ *  Copyright (C) 2020 Compass Electronics Group, LLC
+ */
+
+#ifndef __DT_BINDINGS_IMX8MN_POWER_H__
+#define __DT_BINDINGS_IMX8MN_POWER_H__
+
+#define IMX8MN_POWER_DOMAIN_HSIOMIX	0
+#define IMX8MN_POWER_DOMAIN_OTG1	1
+#define IMX8MN_POWER_DOMAIN_GPUMIX	2
+#define IMX8MN_POWER_DOMAIN_DISPMIX	3
+#define IMX8MN_POWER_DOMAIN_MIPI	4
+
+#endif
-- 
2.25.1


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Re: [PATCH 1/5] dt-bindings: add defines for i.MX8MN power domains

[Shawn Guo]

On Mon, May 24, 2021 at 08:07:28PM -0500, Adam Ford wrote:
> The i.MX8M Nano has a similar power domain controller to that of the
> mini, but it isn't fully compatible, so it needs a separate binding
> and power domain tables.
> 
> Add the bindings and tables.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> Acked-by: Rob Herring <robh@kernel.org>

Applied, thanks.

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[PATCH 2/5] soc: imx: gpcv2: add support for i.MX8MN power domains

[Adam Ford]

This adds support for the power domains founds on i.MX8MN. The Nano
has fewer domains than the Mini, and the access to some of these domains
is different than that of the Mini, the Mini power domains cannot be
reused.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 35bbb1bc5159..3120718e1dd7 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -20,6 +20,7 @@
 #include <dt-bindings/power/imx7-power.h>
 #include <dt-bindings/power/imx8mq-power.h>
 #include <dt-bindings/power/imx8mm-power.h>
+#include <dt-bindings/power/imx8mn-power.h>
 
 #define GPC_LPCR_A_CORE_BSC			0x000
 
@@ -58,6 +59,12 @@
 #define IMX8MM_PCIE_A53_DOMAIN			BIT(3)
 #define IMX8MM_MIPI_A53_DOMAIN			BIT(2)
 
+#define IMX8MN_DISPMIX_A53_DOMAIN		BIT(12)
+#define IMX8MN_GPUMIX_A53_DOMAIN		BIT(9)
+#define IMX8MN_DDR1_A53_DOMAIN		BIT(7)
+#define IMX8MN_OTG1_A53_DOMAIN		BIT(4)
+#define IMX8MN_MIPI_A53_DOMAIN		BIT(2)
+
 #define GPC_PU_PGC_SW_PUP_REQ		0x0f8
 #define GPC_PU_PGC_SW_PDN_REQ		0x104
 
@@ -94,6 +101,12 @@
 #define IMX8MM_PCIE_SW_Pxx_REQ			BIT(1)
 #define IMX8MM_MIPI_SW_Pxx_REQ			BIT(0)
 
+#define IMX8MN_DISPMIX_SW_Pxx_REQ		BIT(10)
+#define IMX8MN_GPUMIX_SW_Pxx_REQ		BIT(7)
+#define IMX8MN_DDR1_SW_Pxx_REQ		BIT(5)
+#define IMX8MN_OTG1_SW_Pxx_REQ		BIT(2)
+#define IMX8MN_MIPI_SW_Pxx_REQ		BIT(0)
+
 #define GPC_M4_PU_PDN_FLG		0x1bc
 
 #define GPC_PU_PWRHSK			0x1fc
@@ -116,6 +129,14 @@
 #define IMX8MM_VPUMIX_HSK_PWRDNREQN		BIT(8)
 #define IMX8MM_DISPMIX_HSK_PWRDNREQN		BIT(7)
 #define IMX8MM_HSIO_HSK_PWRDNREQN		(BIT(5) | BIT(6))
+
+#define IMX8MN_GPUMIX_HSK_PWRDNACKN		(BIT(29) | BIT(27))
+#define IMX8MN_DISPMIX_HSK_PWRDNACKN		BIT(25)
+#define IMX8MN_HSIO_HSK_PWRDNACKN		BIT(23)
+#define IMX8MN_GPUMIX_HSK_PWRDNREQN		(BIT(11) | BIT(9))
+#define IMX8MN_DISPMIX_HSK_PWRDNREQN		BIT(7)
+#define IMX8MN_HSIO_HSK_PWRDNREQN		BIT(5)
+
 /*
  * The PGC offset values in Reference Manual
  * (Rev. 1, 01/2018 and the older ones) GPC chapter's
@@ -152,6 +173,12 @@
 #define IMX8MM_PGC_VPUG2		28
 #define IMX8MM_PGC_VPUH1		29
 
+#define IMX8MN_PGC_MIPI		16
+#define IMX8MN_PGC_OTG1		18
+#define IMX8MN_PGC_DDR1		21
+#define IMX8MN_PGC_GPUMIX		23
+#define IMX8MN_PGC_DISPMIX		26
+
 #define GPC_PGC_CTRL(n)			(0x800 + (n) * 0x40)
 #define GPC_PGC_SR(n)			(GPC_PGC_CTRL(n) + 0xc)
 
@@ -764,6 +791,71 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
 	.reg_access_table = &imx8mm_access_table,
 };
 
+static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
+	[IMX8MN_POWER_DOMAIN_HSIOMIX] = {
+		.genpd = {
+			.name = "hsiomix",
+		},
+		.bits  = {
+			.pxx = 0, /* no power sequence control */
+			.map = 0, /* no power sequence control */
+			.hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
+			.hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
+		},
+	},
+
+	[IMX8MN_POWER_DOMAIN_OTG1] = {
+		.genpd = {
+			.name = "usb-otg1",
+		},
+		.bits  = {
+			.pxx = IMX8MN_OTG1_SW_Pxx_REQ,
+			.map = IMX8MN_OTG1_A53_DOMAIN,
+		},
+		.pgc   = IMX8MN_PGC_OTG1,
+	},
+
+	[IMX8MN_POWER_DOMAIN_GPUMIX] = {
+		.genpd = {
+			.name = "gpumix",
+		},
+		.bits  = {
+			.pxx = IMX8MN_GPUMIX_SW_Pxx_REQ,
+			.map = IMX8MN_GPUMIX_A53_DOMAIN,
+			.hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
+			.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
+		},
+		.pgc   = IMX8MN_PGC_GPUMIX,
+	},
+};
+
+static const struct regmap_range imx8mn_yes_ranges[] = {
+	regmap_reg_range(GPC_LPCR_A_CORE_BSC,
+			 GPC_PU_PWRHSK),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
+			 GPC_PGC_SR(IMX8MN_PGC_MIPI)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
+			 GPC_PGC_SR(IMX8MN_PGC_OTG1)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
+			 GPC_PGC_SR(IMX8MN_PGC_DDR1)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
+			 GPC_PGC_SR(IMX8MN_PGC_GPUMIX)),
+	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
+			 GPC_PGC_SR(IMX8MN_PGC_DISPMIX)),
+};
+
+static const struct regmap_access_table imx8mn_access_table = {
+	.yes_ranges	= imx8mn_yes_ranges,
+	.n_yes_ranges	= ARRAY_SIZE(imx8mn_yes_ranges),
+};
+
+static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
+	.domains = imx8mn_pgc_domains,
+	.domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
+	.reg_access_table = &imx8mn_access_table,
+};
+
+
 static int imx_pgc_domain_probe(struct platform_device *pdev)
 {
 	struct imx_pgc_domain *domain = pdev->dev.platform_data;
@@ -948,6 +1040,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
 static const struct of_device_id imx_gpcv2_dt_ids[] = {
 	{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
 	{ .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
+	{ .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
 	{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
 	{ }
 };
-- 
2.25.1


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Re: [PATCH 2/5] soc: imx: gpcv2: add support for i.MX8MN power domains

[Shawn Guo]

On Mon, May 24, 2021 at 08:07:29PM -0500, Adam Ford wrote:
> This adds support for the power domains founds on i.MX8MN. The Nano
> has fewer domains than the Mini, and the access to some of these domains
> is different than that of the Mini, the Mini power domains cannot be
> reused.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index 35bbb1bc5159..3120718e1dd7 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -20,6 +20,7 @@
>  #include <dt-bindings/power/imx7-power.h>
>  #include <dt-bindings/power/imx8mq-power.h>
>  #include <dt-bindings/power/imx8mm-power.h>
> +#include <dt-bindings/power/imx8mn-power.h>
>  
>  #define GPC_LPCR_A_CORE_BSC			0x000
>  
> @@ -58,6 +59,12 @@
>  #define IMX8MM_PCIE_A53_DOMAIN			BIT(3)
>  #define IMX8MM_MIPI_A53_DOMAIN			BIT(2)
>  
> +#define IMX8MN_DISPMIX_A53_DOMAIN		BIT(12)
> +#define IMX8MN_GPUMIX_A53_DOMAIN		BIT(9)
> +#define IMX8MN_DDR1_A53_DOMAIN		BIT(7)
> +#define IMX8MN_OTG1_A53_DOMAIN		BIT(4)
> +#define IMX8MN_MIPI_A53_DOMAIN		BIT(2)
> +
>  #define GPC_PU_PGC_SW_PUP_REQ		0x0f8
>  #define GPC_PU_PGC_SW_PDN_REQ		0x104
>  
> @@ -94,6 +101,12 @@
>  #define IMX8MM_PCIE_SW_Pxx_REQ			BIT(1)
>  #define IMX8MM_MIPI_SW_Pxx_REQ			BIT(0)
>  
> +#define IMX8MN_DISPMIX_SW_Pxx_REQ		BIT(10)
> +#define IMX8MN_GPUMIX_SW_Pxx_REQ		BIT(7)
> +#define IMX8MN_DDR1_SW_Pxx_REQ		BIT(5)
> +#define IMX8MN_OTG1_SW_Pxx_REQ		BIT(2)
> +#define IMX8MN_MIPI_SW_Pxx_REQ		BIT(0)
> +
>  #define GPC_M4_PU_PDN_FLG		0x1bc
>  
>  #define GPC_PU_PWRHSK			0x1fc
> @@ -116,6 +129,14 @@
>  #define IMX8MM_VPUMIX_HSK_PWRDNREQN		BIT(8)
>  #define IMX8MM_DISPMIX_HSK_PWRDNREQN		BIT(7)
>  #define IMX8MM_HSIO_HSK_PWRDNREQN		(BIT(5) | BIT(6))
> +
> +#define IMX8MN_GPUMIX_HSK_PWRDNACKN		(BIT(29) | BIT(27))
> +#define IMX8MN_DISPMIX_HSK_PWRDNACKN		BIT(25)
> +#define IMX8MN_HSIO_HSK_PWRDNACKN		BIT(23)
> +#define IMX8MN_GPUMIX_HSK_PWRDNREQN		(BIT(11) | BIT(9))
> +#define IMX8MN_DISPMIX_HSK_PWRDNREQN		BIT(7)
> +#define IMX8MN_HSIO_HSK_PWRDNREQN		BIT(5)
> +
>  /*
>   * The PGC offset values in Reference Manual
>   * (Rev. 1, 01/2018 and the older ones) GPC chapter's
> @@ -152,6 +173,12 @@
>  #define IMX8MM_PGC_VPUG2		28
>  #define IMX8MM_PGC_VPUH1		29
>  
> +#define IMX8MN_PGC_MIPI		16
> +#define IMX8MN_PGC_OTG1		18
> +#define IMX8MN_PGC_DDR1		21
> +#define IMX8MN_PGC_GPUMIX		23
> +#define IMX8MN_PGC_DISPMIX		26
> +
>  #define GPC_PGC_CTRL(n)			(0x800 + (n) * 0x40)
>  #define GPC_PGC_SR(n)			(GPC_PGC_CTRL(n) + 0xc)
>  
> @@ -764,6 +791,71 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
>  	.reg_access_table = &imx8mm_access_table,
>  };
>  
> +static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
> +	[IMX8MN_POWER_DOMAIN_HSIOMIX] = {
> +		.genpd = {
> +			.name = "hsiomix",
> +		},
> +		.bits  = {
> +			.pxx = 0, /* no power sequence control */
> +			.map = 0, /* no power sequence control */
> +			.hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
> +			.hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
> +		},
> +	},
> +
> +	[IMX8MN_POWER_DOMAIN_OTG1] = {
> +		.genpd = {
> +			.name = "usb-otg1",
> +		},
> +		.bits  = {
> +			.pxx = IMX8MN_OTG1_SW_Pxx_REQ,
> +			.map = IMX8MN_OTG1_A53_DOMAIN,
> +		},
> +		.pgc   = IMX8MN_PGC_OTG1,
> +	},
> +
> +	[IMX8MN_POWER_DOMAIN_GPUMIX] = {
> +		.genpd = {
> +			.name = "gpumix",
> +		},
> +		.bits  = {
> +			.pxx = IMX8MN_GPUMIX_SW_Pxx_REQ,
> +			.map = IMX8MN_GPUMIX_A53_DOMAIN,
> +			.hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
> +			.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
> +		},
> +		.pgc   = IMX8MN_PGC_GPUMIX,
> +	},
> +};
> +
> +static const struct regmap_range imx8mn_yes_ranges[] = {
> +	regmap_reg_range(GPC_LPCR_A_CORE_BSC,
> +			 GPC_PU_PWRHSK),
> +	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
> +			 GPC_PGC_SR(IMX8MN_PGC_MIPI)),
> +	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
> +			 GPC_PGC_SR(IMX8MN_PGC_OTG1)),
> +	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
> +			 GPC_PGC_SR(IMX8MN_PGC_DDR1)),
> +	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
> +			 GPC_PGC_SR(IMX8MN_PGC_GPUMIX)),
> +	regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
> +			 GPC_PGC_SR(IMX8MN_PGC_DISPMIX)),
> +};
> +
> +static const struct regmap_access_table imx8mn_access_table = {
> +	.yes_ranges	= imx8mn_yes_ranges,
> +	.n_yes_ranges	= ARRAY_SIZE(imx8mn_yes_ranges),
> +};
> +
> +static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
> +	.domains = imx8mn_pgc_domains,
> +	.domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
> +	.reg_access_table = &imx8mn_access_table,
> +};
> +
> +

One newline is good enough.

Fixed it up and applied the patch.

Shawn

>  static int imx_pgc_domain_probe(struct platform_device *pdev)
>  {
>  	struct imx_pgc_domain *domain = pdev->dev.platform_data;
> @@ -948,6 +1040,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
>  static const struct of_device_id imx_gpcv2_dt_ids[] = {
>  	{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
>  	{ .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
> +	{ .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
>  	{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
>  	{ }
>  };
> -- 
> 2.25.1
> 

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[PATCH 3/5] arm64: dts: imx8mn: add GPC node and power domains

[Adam Ford]

This adds the DT nodes to describe the power domains available on the
i.MX8MN. There are more power domains, but the displaymix and mipi
power domains need a separate clock block controller which not yet
available, so this limits it to the HSIO, OTG and GPU domains.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index d4231e061403..0eb64b59c8e3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -4,6 +4,8 @@
  */
 
 #include <dt-bindings/clock/imx8mn-clock.h>
+#include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -613,6 +615,40 @@ src: reset-controller@30390000 {
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx8mn-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_hsiomix: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
+						clocks = <&clk IMX8MN_CLK_USB_BUS>;
+					};
+
+					pgc_otg1: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_OTG1>;
+						power-domains = <&pgc_hsiomix>;
+					};
+
+					pgc_gpumix: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
+						clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+							 <&clk IMX8MN_CLK_GPU_SHADER_DIV>,
+							 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+							 <&clk IMX8MN_CLK_GPU_AHB>;
+						resets = <&src IMX8MQ_RESET_GPU_RESET>;
+					};
+				};
+			};
 		};
 
 		aips2: bus@30400000 {
-- 
2.25.1


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[PATCH 4/5] arm64: dts: imx8mn: Add power-domain reference in USB controller

[Adam Ford]

The USB OTG controller cannot be used until the power-domain is enabled
unless it was started in the bootloader.

Adding the power-domain reference to the OTG node allows the OTG
controller to operate.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 0eb64b59c8e3..8b1fb83cb893 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1009,6 +1009,7 @@ usbotg1: usb@32e40000 {
 				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
 				fsl,usbphy = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
+				power-domains = <&pgc_otg1>;
 				status = "disabled";
 			};
 
-- 
2.25.1


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[PATCH 5/5] arm64: dts: imx8mn: Add GPU node

[Adam Ford]

According to the documentation from NXP, the i.MX8M Nano has a
Vivante GC7000 Ultra Lite as its GPU core.

With this patch, the Etnaviv driver presents the GPU as:
   etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203

The stock operating voltage for the i.MX8M Nano is .85V which means
the GPU needs to run at 400MHz.  For boards where the operating
voltage is higher, this can be increased.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 8b1fb83cb893..8fc5d46d076b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1049,6 +1049,31 @@ gpmi: nand-controller@33002000 {
 			status = "disabled";
 		};
 
+		gpu: gpu@38000000 {
+			compatible = "vivante,gc";
+			reg = <0x38000000 0x8000>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MN_CLK_GPU_AHB>,
+				<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+				<&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+				<&clk IMX8MN_CLK_GPU_SHADER_DIV>;
+			clock-names = "reg", "bus", "core", "shader";
+			assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>,
+					  <&clk IMX8MN_CLK_GPU_SHADER_SRC>,
+					  <&clk IMX8MN_CLK_GPU_AXI>,
+					  <&clk IMX8MN_CLK_GPU_AHB>,
+					  <&clk IMX8MN_GPU_PLL>,
+					  <&clk IMX8MN_CLK_GPU_CORE_DIV>,
+					  <&clk IMX8MN_CLK_GPU_SHADER_DIV>;
+			assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
+						  <&clk IMX8MN_GPU_PLL_OUT>,
+						  <&clk IMX8MN_SYS_PLL1_800M>,
+						  <&clk IMX8MN_SYS_PLL1_800M>;
+			assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>,
+				<400000000>, <400000000>;
+			power-domains = <&pgc_gpumix>;
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>,
-- 
2.25.1


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