* [PATCH v2 00/11] Add imx8ulp basic dtsi support
@ 2021-06-18 6:54 Jacky Bai
2021-06-18 6:54 ` [PATCH v2 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string Jacky Bai
` (9 more replies)
0 siblings, 10 replies; 13+ messages in thread
From: Jacky Bai @ 2021-06-18 6:54 UTC (permalink / raw)
To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel
i.MX 8ULP is part of the ULP family with emphasis on extreme low-power
techniques using the 28 nm fully depleted silicon on insulator process.
Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric architecture,
however will add a third DSP domain for advanced voice/audio capability and
a Graphics domain where it is possible to access graphics resources from the
application side or the realtime side.
This patchset adds the basic dtsi support for i.MX8ULP, and also update the
dt-bindings docs for i.MX8ULP.
Jacky Bai (11):
dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string
dt-bindings: i2c: imx-lpi2c: Add imx8ulp compatible string
dt-bindings: mmc: imx-esdhc: Add imx8ulp compatible string
dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string
dt-bindings: spi: fsl-lpspi: Add imx8ulp compatible string
dt-bindings: timer: tpm-timer: Add imx8ulp compatible string
dt-bindings: watchdog: imx7ulp-wdt: Add imx8ulp compatible string
dt-bindings: arm: fsl: Add binding for imx8ulp evk
dt-bindings: clock: Add imx8ulp clock support
arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp
arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board
.../devicetree/bindings/arm/fsl.yaml | 6 +
.../bindings/clock/imx8ulp-clock.yaml | 72 ++
.../devicetree/bindings/gpio/gpio-vf610.yaml | 3 +
.../bindings/i2c/i2c-imx-lpi2c.yaml | 4 +-
.../bindings/mmc/fsl-imx-esdhc.yaml | 4 +
.../bindings/serial/fsl-lpuart.yaml | 4 +-
.../bindings/spi/spi-fsl-lpspi.yaml | 11 +-
.../bindings/timer/nxp,tpm-timer.yaml | 6 +-
.../bindings/watchdog/fsl-imx7ulp-wdt.yaml | 7 +-
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 148 +++
.../boot/dts/freescale/imx8ulp-pinfunc.h | 978 ++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 474 +++++++++
include/dt-bindings/clock/imx8ulp-clock.h | 261 +++++
14 files changed, 1970 insertions(+), 9 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
create mode 100755 arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp.dtsi
create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string
2021-06-18 6:54 [PATCH v2 00/11] Add imx8ulp basic dtsi support Jacky Bai
@ 2021-06-18 6:54 ` Jacky Bai
2021-06-18 6:54 ` [PATCH v2 02/11] dt-bindings: i2c: imx-lpi2c: " Jacky Bai
` (8 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Jacky Bai @ 2021-06-18 6:54 UTC (permalink / raw)
To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel
Add the compatible string for i.MX8ULP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
- v2 changes:
no
---
Documentation/devicetree/bindings/gpio/gpio-vf610.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml
index 19738a457a58..e1359391d3a4 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml
+++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml
@@ -24,6 +24,9 @@ properties:
- items:
- const: fsl,imx7ulp-gpio
- const: fsl,vf610-gpio
+ - items:
+ - const: fsl,imx8ulp-gpio
+ - const: fsl,imx7ulp-gpio
reg:
description: The first reg tuple represents the PORT module, the second tuple
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 02/11] dt-bindings: i2c: imx-lpi2c: Add imx8ulp compatible string
2021-06-18 6:54 [PATCH v2 00/11] Add imx8ulp basic dtsi support Jacky Bai
2021-06-18 6:54 ` [PATCH v2 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string Jacky Bai
@ 2021-06-18 6:54 ` Jacky Bai
2021-06-18 6:54 ` [PATCH v2 03/11] dt-bindings: mmc: imx-esdhc: " Jacky Bai
` (7 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Jacky Bai @ 2021-06-18 6:54 UTC (permalink / raw)
To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel
Add the compatible for i.MX8ULP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
- v2 changes:
no
---
Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
index 29b9447f3b84..0875753c7d15 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
@@ -19,7 +19,9 @@ properties:
- fsl,imx7ulp-lpi2c
- fsl,imx8qm-lpi2c
- items:
- - const: fsl,imx8qxp-lpi2c
+ - enum:
+ - fsl,imx8qxp-lpi2c
+ - fsl,imx8ulp-lpi2c
- const: fsl,imx7ulp-lpi2c
reg:
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 03/11] dt-bindings: mmc: imx-esdhc: Add imx8ulp compatible string
2021-06-18 6:54 [PATCH v2 00/11] Add imx8ulp basic dtsi support Jacky Bai
2021-06-18 6:54 ` [PATCH v2 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string Jacky Bai
2021-06-18 6:54 ` [PATCH v2 02/11] dt-bindings: i2c: imx-lpi2c: " Jacky Bai
@ 2021-06-18 6:54 ` Jacky Bai
2021-06-18 6:54 ` [PATCH v2 04/11] dt-bindings: serial: fsl-lpuart: " Jacky Bai
` (6 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Jacky Bai @ 2021-06-18 6:54 UTC (permalink / raw)
To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel
The USDHC on i.MX8ULP is derived from i.MX8MM, it uses two
compatible strings, so update the compatible string for i.MX8ULP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
- v2 changes:
refine the commit message
---
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
index 369471814496..aeee2be1e36a 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
@@ -42,6 +42,10 @@ properties:
- fsl,imx8qm-usdhc
- fsl,imx8qxp-usdhc
- const: fsl,imx7d-usdhc
+ - items:
+ - enum:
+ - fsl,imx8ulp-usdhc
+ - const: fsl,imx8mm-usdhc
reg:
maxItems: 1
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 04/11] dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string
2021-06-18 6:54 [PATCH v2 00/11] Add imx8ulp basic dtsi support Jacky Bai
` (2 preceding siblings ...)
2021-06-18 6:54 ` [PATCH v2 03/11] dt-bindings: mmc: imx-esdhc: " Jacky Bai
@ 2021-06-18 6:54 ` Jacky Bai
2021-06-18 6:54 ` [PATCH v2 05/11] dt-bindings: spi: fsl-lpspi: " Jacky Bai
` (5 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Jacky Bai @ 2021-06-18 6:54 UTC (permalink / raw)
To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel
The lpuart on i.MX8ULP is derived from i.MX7ULP, it uses two compatible
strings, so update the compatible string for i.MX8ULP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
- v2 changes:
refine the commit messages
---
Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
index bd21060d26e0..5d3fde5d4d2b 100644
--- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
@@ -22,7 +22,9 @@ properties:
- fsl,imx7ulp-lpuart
- fsl,imx8qm-lpuart
- items:
- - const: fsl,imx8qxp-lpuart
+ - enum:
+ - fsl,imx8qxp-lpuart
+ - fsl,imx8ulp-lpuart
- const: fsl,imx7ulp-lpuart
reg:
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 05/11] dt-bindings: spi: fsl-lpspi: Add imx8ulp compatible string
2021-06-18 6:54 [PATCH v2 00/11] Add imx8ulp basic dtsi support Jacky Bai
` (3 preceding siblings ...)
2021-06-18 6:54 ` [PATCH v2 04/11] dt-bindings: serial: fsl-lpuart: " Jacky Bai
@ 2021-06-18 6:54 ` Jacky Bai
2021-06-18 6:54 ` [PATCH v2 06/11] dt-bindings: timer: tpm-timer: " Jacky Bai
` (4 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Jacky Bai @ 2021-06-18 6:54 UTC (permalink / raw)
To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel
The lpspi on i.MX8ULP is derived from i.MX7ULP, it uses two
compatible strings, so update the comaptible string for i.MX8ULP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
- v2 changes:
refine the commit message
---
.../devicetree/bindings/spi/spi-fsl-lpspi.yaml | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
index 312d8fee9dbb..1d46877fe46a 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
@@ -14,10 +14,13 @@ allOf:
properties:
compatible:
- enum:
- - fsl,imx7ulp-spi
- - fsl,imx8qxp-spi
-
+ oneOf:
+ - enum:
+ - fsl,imx7ulp-spi
+ - fsl,imx8qxp-spi
+ - items:
+ - const: fsl,imx8ulp-spi
+ - const: fsl,imx7ulp-spi
reg:
maxItems: 1
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 06/11] dt-bindings: timer: tpm-timer: Add imx8ulp compatible string
2021-06-18 6:54 [PATCH v2 00/11] Add imx8ulp basic dtsi support Jacky Bai
` (4 preceding siblings ...)
2021-06-18 6:54 ` [PATCH v2 05/11] dt-bindings: spi: fsl-lpspi: " Jacky Bai
@ 2021-06-18 6:54 ` Jacky Bai
2021-06-18 6:54 ` [PATCH v2 07/11] dt-bindings: watchdog: imx7ulp-wdt: " Jacky Bai
` (3 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Jacky Bai @ 2021-06-18 6:54 UTC (permalink / raw)
To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel
The tpm timer on i.MX8ULP is derived from i.MX7ULP, it use two
compatible strings, so update the compatible string for it.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
- v2 changes:
refine the commit message
---
Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
index edd9585f6726..f69773a8e4b9 100644
--- a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
@@ -19,7 +19,11 @@ description: |
properties:
compatible:
- const: fsl,imx7ulp-tpm
+ oneOf:
+ - const: fsl,imx7ulp-tpm
+ - items:
+ - const: fsl,imx8ulp-tpm
+ - const: fsl,imx7ulp-tpm
reg:
maxItems: 1
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 07/11] dt-bindings: watchdog: imx7ulp-wdt: Add imx8ulp compatible string
2021-06-18 6:54 [PATCH v2 00/11] Add imx8ulp basic dtsi support Jacky Bai
` (5 preceding siblings ...)
2021-06-18 6:54 ` [PATCH v2 06/11] dt-bindings: timer: tpm-timer: " Jacky Bai
@ 2021-06-18 6:54 ` Jacky Bai
2021-06-18 6:54 ` [PATCH v2 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk Jacky Bai
` (2 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Jacky Bai @ 2021-06-18 6:54 UTC (permalink / raw)
To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel
The wdog on i.MX8ULP is derived from i.MX7ULP, it uses two compatible
strings, so update the compatible string for i.MX8ULP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
- v2 changes:
refine the commit message
---
.../devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
index 51d6d482bbc2..fb603a20e396 100644
--- a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
@@ -14,8 +14,11 @@ allOf:
properties:
compatible:
- enum:
- - fsl,imx7ulp-wdt
+ oneOf:
+ - const: fsl,imx7ulp-wdt
+ - items:
+ - const: fsl,imx8ulp-wdt
+ - const: fsl,imx7ulp-wdt
reg:
maxItems: 1
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk
2021-06-18 6:54 [PATCH v2 00/11] Add imx8ulp basic dtsi support Jacky Bai
` (6 preceding siblings ...)
2021-06-18 6:54 ` [PATCH v2 07/11] dt-bindings: watchdog: imx7ulp-wdt: " Jacky Bai
@ 2021-06-18 6:54 ` Jacky Bai
2021-06-18 6:54 ` [PATCH v2 09/11] dt-bindings: clock: Add imx8ulp clock support Jacky Bai
2021-06-18 6:54 ` [PATCH v2 11/11] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board Jacky Bai
9 siblings, 0 replies; 13+ messages in thread
From: Jacky Bai @ 2021-06-18 6:54 UTC (permalink / raw)
To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel
Add the dt binding for i.MX8ULP EVK board.
i.MX 8ULP is part of the ULP family with emphasis on extreme
low-power techniques using the 28 nm fully depleted silicon on
insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be
based on asymmetric architecture, however will add a third DSP
domain for advanced voice/audio capability and a Graphics domain
where it is possible to access graphics resources from the
application side or the realtime side.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
- v2 changes:
no
---
Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index fce2a8670b49..e68a1b43b144 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -788,6 +788,12 @@ properties:
- const: toradex,colibri-imx8x
- const: fsl,imx8qxp
+ - description: i.MX8ULP based Boards
+ items:
+ - enum:
+ - fsl,imx8ulp-evk # i.MX8ULP EVK Board
+ - const: fsl,imx8ulp
+
- description:
Freescale Vybrid Platform Device Tree Bindings
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 09/11] dt-bindings: clock: Add imx8ulp clock support
2021-06-18 6:54 [PATCH v2 00/11] Add imx8ulp basic dtsi support Jacky Bai
` (7 preceding siblings ...)
2021-06-18 6:54 ` [PATCH v2 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk Jacky Bai
@ 2021-06-18 6:54 ` Jacky Bai
2021-06-24 21:36 ` Rob Herring
2021-06-18 6:54 ` [PATCH v2 11/11] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board Jacky Bai
9 siblings, 1 reply; 13+ messages in thread
From: Jacky Bai @ 2021-06-18 6:54 UTC (permalink / raw)
To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel
Add the clock dt-binding file for i.MX8ULP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
- v2 changes:
update the license
---
.../bindings/clock/imx8ulp-clock.yaml | 72 +++++
include/dt-bindings/clock/imx8ulp-clock.h | 261 ++++++++++++++++++
2 files changed, 333 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
new file mode 100644
index 000000000000..b47d09ed4a57
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx8ulp-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8ULP Clock Control Module Binding
+
+maintainers:
+ - Jacky Bai <ping.bai@nxp.com>
+
+description: |
+ On i.MX8ULP, The clock sources generation, distribution and management is
+ under the control of several CGCs & PCCs modules. The CGC modules generate
+ and distribute clocks on the device. PCC modules control clock selection,
+ optional division and clock gating mode for peripherals
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8ulp-cgc1
+ - fsl,imx8ulp-cgc2
+ - fsl,imx8ulp-pcc3
+ - fsl,imx8ulp-pcc4
+ - fsl,imx8ulp-pcc5
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description:
+ specify the external clocks used by the CGC module, the clocks
+ are rosc, sosc, frosc, lposc
+ maxItems: 4
+
+ clock-names:
+ description:
+ specify the external clocks names used by the CGC module. the valid
+ clock names should rosc, sosc, frosc, lposc.
+ maxItems: 4
+
+ '#clock-cells':
+ const: 1
+ description:
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8ulp-clock.h
+ for the full list of i.MX8ULP clock IDs.
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+ clock-controller@292c0000 {
+ compatible = "fsl,imx8ulp-cgc1";
+ reg = <0x292c0000 0x10000>;
+ clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
+ clock-names = "rosc", "sosc", "frosc", "lposc";
+ #clock-cells = <1>;
+ };
+
+ - |
+ clock-controller@292d0000 {
+ compatible = "fsl,imx8ulp-pcc3";
+ reg = <0x292d0000 0x10000>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h
new file mode 100644
index 000000000000..5bd2044633d3
--- /dev/null
+++ b/include/dt-bindings/clock/imx8ulp-clock.h
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H
+#define __DT_BINDINGS_CLOCK_IMX8ULP_H
+
+#define IMX8ULP_CLK_DUMMY 0
+#define IMX8ULP_CLK_ROSC 1
+#define IMX8ULP_CLK_FROSC 2
+#define IMX8ULP_CLK_LPOSC 3
+#define IMX8ULP_CLK_SOSC 4
+
+/* CGC1 */
+#define IMX8ULP_CLK_SPLL2 5
+#define IMX8ULP_CLK_SPLL3 6
+#define IMX8ULP_CLK_A35_SEL 7
+#define IMX8ULP_CLK_A35_DIV 8
+#define IMX8ULP_CLK_SPLL2_PRE_SEL 9
+#define IMX8ULP_CLK_SPLL3_PRE_SEL 10
+#define IMX8ULP_CLK_SPLL3_PFD0 11
+#define IMX8ULP_CLK_SPLL3_PFD1 12
+#define IMX8ULP_CLK_SPLL3_PFD2 13
+#define IMX8ULP_CLK_SPLL3_PFD3 14
+#define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15
+#define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16
+#define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17
+#define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18
+#define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19
+#define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20
+#define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21
+#define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22
+#define IMX8ULP_CLK_NIC_SEL 23
+#define IMX8ULP_CLK_NIC_AD_DIVPLAT 24
+#define IMX8ULP_CLK_NIC_PER_DIVPLAT 25
+#define IMX8ULP_CLK_XBAR_SEL 26
+#define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27
+#define IMX8ULP_CLK_XBAR_DIVBUS 28
+#define IMX8ULP_CLK_XBAR_AD_SLOW 29
+#define IMX8ULP_CLK_SOSC_DIV1 30
+#define IMX8ULP_CLK_SOSC_DIV2 31
+#define IMX8ULP_CLK_SOSC_DIV3 32
+#define IMX8ULP_CLK_FROSC_DIV1 33
+#define IMX8ULP_CLK_FROSC_DIV2 34
+#define IMX8ULP_CLK_FROSC_DIV3 35
+#define IMX8ULP_CLK_SPLL3_VCODIV 36
+#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37
+#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38
+#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39
+#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40
+#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41
+#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42
+#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43
+#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44
+#define IMX8ULP_CLK_SOSC_DIV1_GATE 45
+#define IMX8ULP_CLK_SOSC_DIV2_GATE 46
+#define IMX8ULP_CLK_SOSC_DIV3_GATE 47
+#define IMX8ULP_CLK_FROSC_DIV1_GATE 48
+#define IMX8ULP_CLK_FROSC_DIV2_GATE 49
+#define IMX8ULP_CLK_FROSC_DIV3_GATE 50
+#define IMX8ULP_CLK_SAI4_SEL 51
+#define IMX8ULP_CLK_SAI5_SEL 52
+#define IMX8ULP_CLK_AUD_CLK1 53
+#define IMX8ULP_CLK_ARM 54
+#define IMX8ULP_CLK_ENET_TS_SEL 55
+
+#define IMX8ULP_CLK_CGC1_END 56
+
+/* CGC2 */
+#define IMX8ULP_CLK_PLL4_PRE_SEL 0
+#define IMX8ULP_CLK_PLL4 1
+#define IMX8ULP_CLK_PLL4_VCODIV 2
+#define IMX8ULP_CLK_DDR_SEL 3
+#define IMX8ULP_CLK_DDR_DIV 4
+#define IMX8ULP_CLK_LPAV_AXI_SEL 5
+#define IMX8ULP_CLK_LPAV_AXI_DIV 6
+#define IMX8ULP_CLK_LPAV_AHB_DIV 7
+#define IMX8ULP_CLK_LPAV_BUS_DIV 8
+#define IMX8ULP_CLK_PLL4_PFD0 9
+#define IMX8ULP_CLK_PLL4_PFD1 10
+#define IMX8ULP_CLK_PLL4_PFD2 11
+#define IMX8ULP_CLK_PLL4_PFD3 12
+#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13
+#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14
+#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15
+#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16
+#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17
+#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18
+#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19
+#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20
+#define IMX8ULP_CLK_PLL4_PFD0_DIV1 21
+#define IMX8ULP_CLK_PLL4_PFD0_DIV2 22
+#define IMX8ULP_CLK_PLL4_PFD1_DIV1 23
+#define IMX8ULP_CLK_PLL4_PFD1_DIV2 24
+#define IMX8ULP_CLK_PLL4_PFD2_DIV1 25
+#define IMX8ULP_CLK_PLL4_PFD2_DIV2 26
+#define IMX8ULP_CLK_PLL4_PFD3_DIV1 27
+#define IMX8ULP_CLK_PLL4_PFD3_DIV2 28
+#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29
+#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30
+#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31
+#define IMX8ULP_CLK_CGC2_SOSC_DIV1 32
+#define IMX8ULP_CLK_CGC2_SOSC_DIV2 33
+#define IMX8ULP_CLK_CGC2_SOSC_DIV3 34
+#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35
+#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36
+#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37
+#define IMX8ULP_CLK_CGC2_FROSC_DIV1 38
+#define IMX8ULP_CLK_CGC2_FROSC_DIV2 39
+#define IMX8ULP_CLK_CGC2_FROSC_DIV3 40
+#define IMX8ULP_CLK_AUD_CLK2 41
+#define IMX8ULP_CLK_SAI6_SEL 42
+#define IMX8ULP_CLK_SAI7_SEL 43
+#define IMX8ULP_CLK_SPDIF_SEL 44
+#define IMX8ULP_CLK_HIFI_SEL 45
+#define IMX8ULP_CLK_HIFI_DIVCORE 46
+#define IMX8ULP_CLK_HIFI_DIVPLAT 47
+#define IMX8ULP_CLK_DSI_PHY_REF 48
+
+#define IMX8ULP_CLK_CGC2_END 49
+
+/* PCC3 */
+#define IMX8ULP_CLK_WDOG3 0
+#define IMX8ULP_CLK_WDOG4 1
+#define IMX8ULP_CLK_LPIT1 2
+#define IMX8ULP_CLK_TPM4 3
+#define IMX8ULP_CLK_TPM5 4
+#define IMX8ULP_CLK_FLEXIO1 5
+#define IMX8ULP_CLK_I3C2 6
+#define IMX8ULP_CLK_LPI2C4 7
+#define IMX8ULP_CLK_LPI2C5 8
+#define IMX8ULP_CLK_LPUART4 9
+#define IMX8ULP_CLK_LPUART5 10
+#define IMX8ULP_CLK_LPSPI4 11
+#define IMX8ULP_CLK_LPSPI5 12
+#define IMX8ULP_CLK_DMA1_MP 13
+#define IMX8ULP_CLK_DMA1_CH0 14
+#define IMX8ULP_CLK_DMA1_CH1 15
+#define IMX8ULP_CLK_DMA1_CH2 16
+#define IMX8ULP_CLK_DMA1_CH3 17
+#define IMX8ULP_CLK_DMA1_CH4 18
+#define IMX8ULP_CLK_DMA1_CH5 19
+#define IMX8ULP_CLK_DMA1_CH6 20
+#define IMX8ULP_CLK_DMA1_CH7 21
+#define IMX8ULP_CLK_DMA1_CH8 22
+#define IMX8ULP_CLK_DMA1_CH9 23
+#define IMX8ULP_CLK_DMA1_CH10 24
+#define IMX8ULP_CLK_DMA1_CH11 25
+#define IMX8ULP_CLK_DMA1_CH12 26
+#define IMX8ULP_CLK_DMA1_CH13 27
+#define IMX8ULP_CLK_DMA1_CH14 28
+#define IMX8ULP_CLK_DMA1_CH15 29
+#define IMX8ULP_CLK_DMA1_CH16 30
+#define IMX8ULP_CLK_DMA1_CH17 31
+#define IMX8ULP_CLK_DMA1_CH18 32
+#define IMX8ULP_CLK_DMA1_CH19 33
+#define IMX8ULP_CLK_DMA1_CH20 34
+#define IMX8ULP_CLK_DMA1_CH21 35
+#define IMX8ULP_CLK_DMA1_CH22 36
+#define IMX8ULP_CLK_DMA1_CH23 37
+#define IMX8ULP_CLK_DMA1_CH24 38
+#define IMX8ULP_CLK_DMA1_CH25 39
+#define IMX8ULP_CLK_DMA1_CH26 40
+#define IMX8ULP_CLK_DMA1_CH27 41
+#define IMX8ULP_CLK_DMA1_CH28 42
+#define IMX8ULP_CLK_DMA1_CH29 43
+#define IMX8ULP_CLK_DMA1_CH30 44
+#define IMX8ULP_CLK_DMA1_CH31 45
+#define IMX8ULP_CLK_MU3_A 46
+
+#define IMX8ULP_CLK_PCC3_END 47
+
+/* PCC4 */
+#define IMX8ULP_CLK_FLEXSPI2 0
+#define IMX8ULP_CLK_TPM6 1
+#define IMX8ULP_CLK_TPM7 2
+#define IMX8ULP_CLK_LPI2C6 3
+#define IMX8ULP_CLK_LPI2C7 4
+#define IMX8ULP_CLK_LPUART6 5
+#define IMX8ULP_CLK_LPUART7 6
+#define IMX8ULP_CLK_SAI4 7
+#define IMX8ULP_CLK_SAI5 8
+#define IMX8ULP_CLK_PCTLE 9
+#define IMX8ULP_CLK_PCTLF 10
+#define IMX8ULP_CLK_USDHC0 11
+#define IMX8ULP_CLK_USDHC1 12
+#define IMX8ULP_CLK_USDHC2 13
+#define IMX8ULP_CLK_USB0 14
+#define IMX8ULP_CLK_USB0_PHY 15
+#define IMX8ULP_CLK_USB1 16
+#define IMX8ULP_CLK_USB1_PHY 17
+#define IMX8ULP_CLK_USB_XBAR 18
+#define IMX8ULP_CLK_ENET 19
+#define IMX8ULP_CLK_SFA1 20
+#define IMX8ULP_CLK_RGPIOE 21
+#define IMX8ULP_CLK_RGPIOF 22
+
+#define IMX8ULP_CLK_PCC4_END 23
+
+/* PCC5 */
+#define IMX8ULP_CLK_TPM8 0
+#define IMX8ULP_CLK_SAI6 1
+#define IMX8ULP_CLK_SAI7 2
+#define IMX8ULP_CLK_SPDIF 3
+#define IMX8ULP_CLK_ISI 4
+#define IMX8ULP_CLK_CSI_REGS 5
+#define IMX8ULP_CLK_PCTLD 6
+#define IMX8ULP_CLK_CSI 7
+#define IMX8ULP_CLK_DSI 8
+#define IMX8ULP_CLK_WDOG5 9
+#define IMX8ULP_CLK_EPDC 10
+#define IMX8ULP_CLK_PXP 11
+#define IMX8ULP_CLK_SFA2 12
+#define IMX8ULP_CLK_GPU2D 13
+#define IMX8ULP_CLK_GPU3D 14
+#define IMX8ULP_CLK_DC_NANO 15
+#define IMX8ULP_CLK_CSI_CLK_UI 16
+#define IMX8ULP_CLK_CSI_CLK_ESC 17
+#define IMX8ULP_CLK_RGPIOD 18
+#define IMX8ULP_CLK_DMA2_MP 19
+#define IMX8ULP_CLK_DMA2_CH0 20
+#define IMX8ULP_CLK_DMA2_CH1 21
+#define IMX8ULP_CLK_DMA2_CH2 22
+#define IMX8ULP_CLK_DMA2_CH3 23
+#define IMX8ULP_CLK_DMA2_CH4 24
+#define IMX8ULP_CLK_DMA2_CH5 25
+#define IMX8ULP_CLK_DMA2_CH6 26
+#define IMX8ULP_CLK_DMA2_CH7 27
+#define IMX8ULP_CLK_DMA2_CH8 28
+#define IMX8ULP_CLK_DMA2_CH9 29
+#define IMX8ULP_CLK_DMA2_CH10 30
+#define IMX8ULP_CLK_DMA2_CH11 31
+#define IMX8ULP_CLK_DMA2_CH12 32
+#define IMX8ULP_CLK_DMA2_CH13 33
+#define IMX8ULP_CLK_DMA2_CH14 34
+#define IMX8ULP_CLK_DMA2_CH15 35
+#define IMX8ULP_CLK_DMA2_CH16 36
+#define IMX8ULP_CLK_DMA2_CH17 37
+#define IMX8ULP_CLK_DMA2_CH18 38
+#define IMX8ULP_CLK_DMA2_CH19 39
+#define IMX8ULP_CLK_DMA2_CH20 40
+#define IMX8ULP_CLK_DMA2_CH21 41
+#define IMX8ULP_CLK_DMA2_CH22 42
+#define IMX8ULP_CLK_DMA2_CH23 43
+#define IMX8ULP_CLK_DMA2_CH24 44
+#define IMX8ULP_CLK_DMA2_CH25 45
+#define IMX8ULP_CLK_DMA2_CH26 46
+#define IMX8ULP_CLK_DMA2_CH27 47
+#define IMX8ULP_CLK_DMA2_CH28 48
+#define IMX8ULP_CLK_DMA2_CH29 49
+#define IMX8ULP_CLK_DMA2_CH30 50
+#define IMX8ULP_CLK_DMA2_CH31 51
+#define IMX8ULP_CLK_MU2_B 52
+#define IMX8ULP_CLK_MU3_B 53
+#define IMX8ULP_CLK_AVD_SIM 54
+#define IMX8ULP_CLK_DSI_TX_ESC 55
+
+#define IMX8ULP_CLK_PCC5_END 56
+
+#endif
--
2.26.2
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 11/11] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board
2021-06-18 6:54 [PATCH v2 00/11] Add imx8ulp basic dtsi support Jacky Bai
` (8 preceding siblings ...)
2021-06-18 6:54 ` [PATCH v2 09/11] dt-bindings: clock: Add imx8ulp clock support Jacky Bai
@ 2021-06-18 6:54 ` Jacky Bai
9 siblings, 0 replies; 13+ messages in thread
From: Jacky Bai @ 2021-06-18 6:54 UTC (permalink / raw)
To: robh+dt, shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong
Cc: festevam, kernel, linux-imx, devicetree, linux-arm-kernel
Add the basic dts file for i.MX8ULP EVK board.
Only the necessary devices for minimal system boot up are enabled:
enet, emmc, usb, console uart.
some of the devices' pin status may lost during low power mode,
so additional sleep pinctrl properties are included by default.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
- v2 changes:
add the memory node place holder
update the license
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 148 ++++++++++++++++++
2 files changed, 149 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 25806c4924cb..8c24a05d55af 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -65,5 +65,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
new file mode 100644
index 000000000000..de84f29c12ce
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8ulp.dtsi"
+
+/ {
+ model = "NXP i.MX8ULP EVK";
+ compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
+
+ chosen {
+ stdout-path = &lpuart5;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy {
+ reg = <1>;
+ micrel,led-mode = <1>;
+ };
+ };
+};
+
+&lpuart5 {
+ /* console */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpuart5>;
+ pinctrl-1 = <&pinctrl_lpuart5>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_otgid1>;
+ pinctrl-1 = <&pinctrl_otgid1>;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
+
+&usbmisc1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_otgid2>;
+ pinctrl-1 = <&pinctrl_otgid2>;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&usbmisc2 {
+ status = "okay";
+};
+
+&usdhc0 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ non-removable;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&iomuxc1 {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX8ULP_PAD_PTE15__ENET0_MDC 0x43
+ MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
+ MX8ULP_PAD_PTE17__ENET0_RXER 0x43
+ MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
+ MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
+ MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
+ MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
+ MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
+ MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
+ MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
+ MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
+ >;
+ };
+
+ pinctrl_lpuart5: lpuart5grp {
+ fsl,pins = <
+ MX8ULP_PAD_PTF14__LPUART5_TX 0x3
+ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
+ >;
+ };
+
+ pinctrl_otgid1: usb1grp {
+ fsl,pins = <
+ MX8ULP_PAD_PTF2__USB0_ID 0x10003
+ >;
+ };
+
+ pinctrl_otgid2: usb2grp {
+ fsl,pins = <
+ MX8ULP_PAD_PTD23__USB1_ID 0x10003
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
+ MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
+ MX8ULP_PAD_PTD10__SDHC0_D0 0x43
+ MX8ULP_PAD_PTD9__SDHC0_D1 0x43
+ MX8ULP_PAD_PTD8__SDHC0_D2 0x43
+ MX8ULP_PAD_PTD7__SDHC0_D3 0x43
+ MX8ULP_PAD_PTD6__SDHC0_D4 0x43
+ MX8ULP_PAD_PTD5__SDHC0_D5 0x43
+ MX8ULP_PAD_PTD4__SDHC0_D6 0x43
+ MX8ULP_PAD_PTD3__SDHC0_D7 0x43
+ MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
+ >;
+ };
+};
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 09/11] dt-bindings: clock: Add imx8ulp clock support
2021-06-18 6:54 ` [PATCH v2 09/11] dt-bindings: clock: Add imx8ulp clock support Jacky Bai
@ 2021-06-24 21:36 ` Rob Herring
2021-06-25 0:30 ` Jacky Bai
0 siblings, 1 reply; 13+ messages in thread
From: Rob Herring @ 2021-06-24 21:36 UTC (permalink / raw)
To: Jacky Bai
Cc: shawnguo, sboyd, s.hauer, linus.walleij, aisheng.dong, festevam,
kernel, linux-imx, devicetree, linux-arm-kernel
On Fri, Jun 18, 2021 at 02:54:21PM +0800, Jacky Bai wrote:
> Add the clock dt-binding file for i.MX8ULP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> ---
> - v2 changes:
> update the license
> ---
> .../bindings/clock/imx8ulp-clock.yaml | 72 +++++
> include/dt-bindings/clock/imx8ulp-clock.h | 261 ++++++++++++++++++
> 2 files changed, 333 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h
>
> diff --git a/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> new file mode 100644
> index 000000000000..b47d09ed4a57
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Sigh, like all the others: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/imx8ulp-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX8ULP Clock Control Module Binding
> +
> +maintainers:
> + - Jacky Bai <ping.bai@nxp.com>
> +
> +description: |
> + On i.MX8ULP, The clock sources generation, distribution and management is
> + under the control of several CGCs & PCCs modules. The CGC modules generate
> + and distribute clocks on the device. PCC modules control clock selection,
> + optional division and clock gating mode for peripherals
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8ulp-cgc1
> + - fsl,imx8ulp-cgc2
> + - fsl,imx8ulp-pcc3
> + - fsl,imx8ulp-pcc4
> + - fsl,imx8ulp-pcc5
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + description:
> + specify the external clocks used by the CGC module, the clocks
> + are rosc, sosc, frosc, lposc
> + maxItems: 4
> +
> + clock-names:
> + description:
> + specify the external clocks names used by the CGC module. the valid
> + clock names should rosc, sosc, frosc, lposc.
> + maxItems: 4
> +
> + '#clock-cells':
> + const: 1
> + description:
> + The clock consumer should specify the desired clock by having the clock
> + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8ulp-clock.h
> + for the full list of i.MX8ULP clock IDs.
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock Control Module node:
> + - |
> + clock-controller@292c0000 {
> + compatible = "fsl,imx8ulp-cgc1";
> + reg = <0x292c0000 0x10000>;
> + clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
> + clock-names = "rosc", "sosc", "frosc", "lposc";
> + #clock-cells = <1>;
> + };
> +
> + - |
> + clock-controller@292d0000 {
> + compatible = "fsl,imx8ulp-pcc3";
> + reg = <0x292d0000 0x10000>;
> + #clock-cells = <1>;
> + };
> diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h
> new file mode 100644
> index 000000000000..5bd2044633d3
> --- /dev/null
> +++ b/include/dt-bindings/clock/imx8ulp-clock.h
> @@ -0,0 +1,261 @@
> +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H
> +#define __DT_BINDINGS_CLOCK_IMX8ULP_H
> +
> +#define IMX8ULP_CLK_DUMMY 0
> +#define IMX8ULP_CLK_ROSC 1
> +#define IMX8ULP_CLK_FROSC 2
> +#define IMX8ULP_CLK_LPOSC 3
> +#define IMX8ULP_CLK_SOSC 4
> +
> +/* CGC1 */
> +#define IMX8ULP_CLK_SPLL2 5
> +#define IMX8ULP_CLK_SPLL3 6
> +#define IMX8ULP_CLK_A35_SEL 7
> +#define IMX8ULP_CLK_A35_DIV 8
> +#define IMX8ULP_CLK_SPLL2_PRE_SEL 9
> +#define IMX8ULP_CLK_SPLL3_PRE_SEL 10
> +#define IMX8ULP_CLK_SPLL3_PFD0 11
> +#define IMX8ULP_CLK_SPLL3_PFD1 12
> +#define IMX8ULP_CLK_SPLL3_PFD2 13
> +#define IMX8ULP_CLK_SPLL3_PFD3 14
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22
> +#define IMX8ULP_CLK_NIC_SEL 23
> +#define IMX8ULP_CLK_NIC_AD_DIVPLAT 24
> +#define IMX8ULP_CLK_NIC_PER_DIVPLAT 25
> +#define IMX8ULP_CLK_XBAR_SEL 26
> +#define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27
> +#define IMX8ULP_CLK_XBAR_DIVBUS 28
> +#define IMX8ULP_CLK_XBAR_AD_SLOW 29
> +#define IMX8ULP_CLK_SOSC_DIV1 30
> +#define IMX8ULP_CLK_SOSC_DIV2 31
> +#define IMX8ULP_CLK_SOSC_DIV3 32
> +#define IMX8ULP_CLK_FROSC_DIV1 33
> +#define IMX8ULP_CLK_FROSC_DIV2 34
> +#define IMX8ULP_CLK_FROSC_DIV3 35
> +#define IMX8ULP_CLK_SPLL3_VCODIV 36
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37
> +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39
> +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41
> +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43
> +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44
> +#define IMX8ULP_CLK_SOSC_DIV1_GATE 45
> +#define IMX8ULP_CLK_SOSC_DIV2_GATE 46
> +#define IMX8ULP_CLK_SOSC_DIV3_GATE 47
> +#define IMX8ULP_CLK_FROSC_DIV1_GATE 48
> +#define IMX8ULP_CLK_FROSC_DIV2_GATE 49
> +#define IMX8ULP_CLK_FROSC_DIV3_GATE 50
> +#define IMX8ULP_CLK_SAI4_SEL 51
> +#define IMX8ULP_CLK_SAI5_SEL 52
> +#define IMX8ULP_CLK_AUD_CLK1 53
> +#define IMX8ULP_CLK_ARM 54
> +#define IMX8ULP_CLK_ENET_TS_SEL 55
> +
> +#define IMX8ULP_CLK_CGC1_END 56
> +
> +/* CGC2 */
> +#define IMX8ULP_CLK_PLL4_PRE_SEL 0
> +#define IMX8ULP_CLK_PLL4 1
> +#define IMX8ULP_CLK_PLL4_VCODIV 2
> +#define IMX8ULP_CLK_DDR_SEL 3
> +#define IMX8ULP_CLK_DDR_DIV 4
> +#define IMX8ULP_CLK_LPAV_AXI_SEL 5
> +#define IMX8ULP_CLK_LPAV_AXI_DIV 6
> +#define IMX8ULP_CLK_LPAV_AHB_DIV 7
> +#define IMX8ULP_CLK_LPAV_BUS_DIV 8
> +#define IMX8ULP_CLK_PLL4_PFD0 9
> +#define IMX8ULP_CLK_PLL4_PFD1 10
> +#define IMX8ULP_CLK_PLL4_PFD2 11
> +#define IMX8ULP_CLK_PLL4_PFD3 12
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV1 21
> +#define IMX8ULP_CLK_PLL4_PFD0_DIV2 22
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV1 23
> +#define IMX8ULP_CLK_PLL4_PFD1_DIV2 24
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV1 25
> +#define IMX8ULP_CLK_PLL4_PFD2_DIV2 26
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV1 27
> +#define IMX8ULP_CLK_PLL4_PFD3_DIV2 28
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV1 32
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV2 33
> +#define IMX8ULP_CLK_CGC2_SOSC_DIV3 34
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV1 38
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV2 39
> +#define IMX8ULP_CLK_CGC2_FROSC_DIV3 40
> +#define IMX8ULP_CLK_AUD_CLK2 41
> +#define IMX8ULP_CLK_SAI6_SEL 42
> +#define IMX8ULP_CLK_SAI7_SEL 43
> +#define IMX8ULP_CLK_SPDIF_SEL 44
> +#define IMX8ULP_CLK_HIFI_SEL 45
> +#define IMX8ULP_CLK_HIFI_DIVCORE 46
> +#define IMX8ULP_CLK_HIFI_DIVPLAT 47
> +#define IMX8ULP_CLK_DSI_PHY_REF 48
> +
> +#define IMX8ULP_CLK_CGC2_END 49
> +
> +/* PCC3 */
> +#define IMX8ULP_CLK_WDOG3 0
> +#define IMX8ULP_CLK_WDOG4 1
> +#define IMX8ULP_CLK_LPIT1 2
> +#define IMX8ULP_CLK_TPM4 3
> +#define IMX8ULP_CLK_TPM5 4
> +#define IMX8ULP_CLK_FLEXIO1 5
> +#define IMX8ULP_CLK_I3C2 6
> +#define IMX8ULP_CLK_LPI2C4 7
> +#define IMX8ULP_CLK_LPI2C5 8
> +#define IMX8ULP_CLK_LPUART4 9
> +#define IMX8ULP_CLK_LPUART5 10
> +#define IMX8ULP_CLK_LPSPI4 11
> +#define IMX8ULP_CLK_LPSPI5 12
> +#define IMX8ULP_CLK_DMA1_MP 13
> +#define IMX8ULP_CLK_DMA1_CH0 14
> +#define IMX8ULP_CLK_DMA1_CH1 15
> +#define IMX8ULP_CLK_DMA1_CH2 16
> +#define IMX8ULP_CLK_DMA1_CH3 17
> +#define IMX8ULP_CLK_DMA1_CH4 18
> +#define IMX8ULP_CLK_DMA1_CH5 19
> +#define IMX8ULP_CLK_DMA1_CH6 20
> +#define IMX8ULP_CLK_DMA1_CH7 21
> +#define IMX8ULP_CLK_DMA1_CH8 22
> +#define IMX8ULP_CLK_DMA1_CH9 23
> +#define IMX8ULP_CLK_DMA1_CH10 24
> +#define IMX8ULP_CLK_DMA1_CH11 25
> +#define IMX8ULP_CLK_DMA1_CH12 26
> +#define IMX8ULP_CLK_DMA1_CH13 27
> +#define IMX8ULP_CLK_DMA1_CH14 28
> +#define IMX8ULP_CLK_DMA1_CH15 29
> +#define IMX8ULP_CLK_DMA1_CH16 30
> +#define IMX8ULP_CLK_DMA1_CH17 31
> +#define IMX8ULP_CLK_DMA1_CH18 32
> +#define IMX8ULP_CLK_DMA1_CH19 33
> +#define IMX8ULP_CLK_DMA1_CH20 34
> +#define IMX8ULP_CLK_DMA1_CH21 35
> +#define IMX8ULP_CLK_DMA1_CH22 36
> +#define IMX8ULP_CLK_DMA1_CH23 37
> +#define IMX8ULP_CLK_DMA1_CH24 38
> +#define IMX8ULP_CLK_DMA1_CH25 39
> +#define IMX8ULP_CLK_DMA1_CH26 40
> +#define IMX8ULP_CLK_DMA1_CH27 41
> +#define IMX8ULP_CLK_DMA1_CH28 42
> +#define IMX8ULP_CLK_DMA1_CH29 43
> +#define IMX8ULP_CLK_DMA1_CH30 44
> +#define IMX8ULP_CLK_DMA1_CH31 45
> +#define IMX8ULP_CLK_MU3_A 46
> +
> +#define IMX8ULP_CLK_PCC3_END 47
> +
> +/* PCC4 */
> +#define IMX8ULP_CLK_FLEXSPI2 0
> +#define IMX8ULP_CLK_TPM6 1
> +#define IMX8ULP_CLK_TPM7 2
> +#define IMX8ULP_CLK_LPI2C6 3
> +#define IMX8ULP_CLK_LPI2C7 4
> +#define IMX8ULP_CLK_LPUART6 5
> +#define IMX8ULP_CLK_LPUART7 6
> +#define IMX8ULP_CLK_SAI4 7
> +#define IMX8ULP_CLK_SAI5 8
> +#define IMX8ULP_CLK_PCTLE 9
> +#define IMX8ULP_CLK_PCTLF 10
> +#define IMX8ULP_CLK_USDHC0 11
> +#define IMX8ULP_CLK_USDHC1 12
> +#define IMX8ULP_CLK_USDHC2 13
> +#define IMX8ULP_CLK_USB0 14
> +#define IMX8ULP_CLK_USB0_PHY 15
> +#define IMX8ULP_CLK_USB1 16
> +#define IMX8ULP_CLK_USB1_PHY 17
> +#define IMX8ULP_CLK_USB_XBAR 18
> +#define IMX8ULP_CLK_ENET 19
> +#define IMX8ULP_CLK_SFA1 20
> +#define IMX8ULP_CLK_RGPIOE 21
> +#define IMX8ULP_CLK_RGPIOF 22
> +
> +#define IMX8ULP_CLK_PCC4_END 23
> +
> +/* PCC5 */
> +#define IMX8ULP_CLK_TPM8 0
> +#define IMX8ULP_CLK_SAI6 1
> +#define IMX8ULP_CLK_SAI7 2
> +#define IMX8ULP_CLK_SPDIF 3
> +#define IMX8ULP_CLK_ISI 4
> +#define IMX8ULP_CLK_CSI_REGS 5
> +#define IMX8ULP_CLK_PCTLD 6
> +#define IMX8ULP_CLK_CSI 7
> +#define IMX8ULP_CLK_DSI 8
> +#define IMX8ULP_CLK_WDOG5 9
> +#define IMX8ULP_CLK_EPDC 10
> +#define IMX8ULP_CLK_PXP 11
> +#define IMX8ULP_CLK_SFA2 12
> +#define IMX8ULP_CLK_GPU2D 13
> +#define IMX8ULP_CLK_GPU3D 14
> +#define IMX8ULP_CLK_DC_NANO 15
> +#define IMX8ULP_CLK_CSI_CLK_UI 16
> +#define IMX8ULP_CLK_CSI_CLK_ESC 17
> +#define IMX8ULP_CLK_RGPIOD 18
> +#define IMX8ULP_CLK_DMA2_MP 19
> +#define IMX8ULP_CLK_DMA2_CH0 20
> +#define IMX8ULP_CLK_DMA2_CH1 21
> +#define IMX8ULP_CLK_DMA2_CH2 22
> +#define IMX8ULP_CLK_DMA2_CH3 23
> +#define IMX8ULP_CLK_DMA2_CH4 24
> +#define IMX8ULP_CLK_DMA2_CH5 25
> +#define IMX8ULP_CLK_DMA2_CH6 26
> +#define IMX8ULP_CLK_DMA2_CH7 27
> +#define IMX8ULP_CLK_DMA2_CH8 28
> +#define IMX8ULP_CLK_DMA2_CH9 29
> +#define IMX8ULP_CLK_DMA2_CH10 30
> +#define IMX8ULP_CLK_DMA2_CH11 31
> +#define IMX8ULP_CLK_DMA2_CH12 32
> +#define IMX8ULP_CLK_DMA2_CH13 33
> +#define IMX8ULP_CLK_DMA2_CH14 34
> +#define IMX8ULP_CLK_DMA2_CH15 35
> +#define IMX8ULP_CLK_DMA2_CH16 36
> +#define IMX8ULP_CLK_DMA2_CH17 37
> +#define IMX8ULP_CLK_DMA2_CH18 38
> +#define IMX8ULP_CLK_DMA2_CH19 39
> +#define IMX8ULP_CLK_DMA2_CH20 40
> +#define IMX8ULP_CLK_DMA2_CH21 41
> +#define IMX8ULP_CLK_DMA2_CH22 42
> +#define IMX8ULP_CLK_DMA2_CH23 43
> +#define IMX8ULP_CLK_DMA2_CH24 44
> +#define IMX8ULP_CLK_DMA2_CH25 45
> +#define IMX8ULP_CLK_DMA2_CH26 46
> +#define IMX8ULP_CLK_DMA2_CH27 47
> +#define IMX8ULP_CLK_DMA2_CH28 48
> +#define IMX8ULP_CLK_DMA2_CH29 49
> +#define IMX8ULP_CLK_DMA2_CH30 50
> +#define IMX8ULP_CLK_DMA2_CH31 51
> +#define IMX8ULP_CLK_MU2_B 52
> +#define IMX8ULP_CLK_MU3_B 53
> +#define IMX8ULP_CLK_AVD_SIM 54
> +#define IMX8ULP_CLK_DSI_TX_ESC 55
> +
> +#define IMX8ULP_CLK_PCC5_END 56
> +
> +#endif
> --
> 2.26.2
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v2 09/11] dt-bindings: clock: Add imx8ulp clock support
2021-06-24 21:36 ` Rob Herring
@ 2021-06-25 0:30 ` Jacky Bai
0 siblings, 0 replies; 13+ messages in thread
From: Jacky Bai @ 2021-06-25 0:30 UTC (permalink / raw)
To: Rob Herring
Cc: shawnguo, sboyd, s.hauer, linus.walleij, Aisheng Dong, festevam,
kernel, dl-linux-imx, devicetree, linux-arm-kernel
> Subject: Re: [PATCH v2 09/11] dt-bindings: clock: Add imx8ulp clock support
>
> On Fri, Jun 18, 2021 at 02:54:21PM +0800, Jacky Bai wrote:
> > Add the clock dt-binding file for i.MX8ULP.
> >
> > Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> > ---
> > - v2 changes:
> > update the license
> > ---
> > .../bindings/clock/imx8ulp-clock.yaml | 72 +++++
> > include/dt-bindings/clock/imx8ulp-clock.h | 261
> ++++++++++++++++++
> > 2 files changed, 333 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> > create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h
> >
> > diff --git
> > a/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> > b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> > new file mode 100644
> > index 000000000000..b47d09ed4a57
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml
> > @@ -0,0 +1,72 @@
> > +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>
> Sigh, like all the others: (GPL-2.0-only OR BSD-2-Clause)
>
Sorry, will fix in V3.
BR
Jacky Bai
> > +%YAML 1.2
> > +---
> > +$id:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fschemas%2Fclock%2Fimx8ulp-clock.yaml%23&data=04
> %7C01
> >
> +%7Cping.bai%40nxp.com%7Cd2d93de7b8ef4010c62208d9375829f5%7C686
> ea1d3bc
> >
> +2b4c6fa92cd99c5c301635%7C0%7C0%7C637601674066509898%7CUnkno
> wn%7CTWFpb
> >
> +GZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVC
> I6Mn
> >
> +0%3D%7C1000&sdata=GwgrgPsHMzRPxHYkfAZzREFLwxol2qMEm0765
> G6QEn0%3D&
> > +amp;reserved=0
> > +$schema:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cpi
> ng.bai%
> >
> +40nxp.com%7Cd2d93de7b8ef4010c62208d9375829f5%7C686ea1d3bc2b4c
> 6fa92cd9
> >
> +9c5c301635%7C0%7C0%7C637601674066519854%7CUnknown%7CTWFpb
> GZsb3d8eyJWI
> >
> +joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7
> C1000&
> >
> +amp;sdata=j1Dv0n2aPGvyXt4WgIxb84NUneh2UEL4GYue8lQR5Ro%3D&
> ;reserved
> > +=0
> > +
> > +title: NXP i.MX8ULP Clock Control Module Binding
> > +
> > +maintainers:
> > + - Jacky Bai <ping.bai@nxp.com>
> > +
> > +description: |
> > + On i.MX8ULP, The clock sources generation, distribution and
> > +management is
> > + under the control of several CGCs & PCCs modules. The CGC modules
> > +generate
> > + and distribute clocks on the device. PCC modules control clock
> > +selection,
> > + optional division and clock gating mode for peripherals
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - fsl,imx8ulp-cgc1
> > + - fsl,imx8ulp-cgc2
> > + - fsl,imx8ulp-pcc3
> > + - fsl,imx8ulp-pcc4
> > + - fsl,imx8ulp-pcc5
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + description:
> > + specify the external clocks used by the CGC module, the clocks
> > + are rosc, sosc, frosc, lposc
> > + maxItems: 4
> > +
> > + clock-names:
> > + description:
> > + specify the external clocks names used by the CGC module. the
> valid
> > + clock names should rosc, sosc, frosc, lposc.
> > + maxItems: 4
> > +
> > + '#clock-cells':
> > + const: 1
> > + description:
> > + The clock consumer should specify the desired clock by having the
> clock
> > + ID in its "clocks" phandle cell. See
> include/dt-bindings/clock/imx8ulp-clock.h
> > + for the full list of i.MX8ULP clock IDs.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - '#clock-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + # Clock Control Module node:
> > + - |
> > + clock-controller@292c0000 {
> > + compatible = "fsl,imx8ulp-cgc1";
> > + reg = <0x292c0000 0x10000>;
> > + clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
> > + clock-names = "rosc", "sosc", "frosc", "lposc";
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + clock-controller@292d0000 {
> > + compatible = "fsl,imx8ulp-pcc3";
> > + reg = <0x292d0000 0x10000>;
> > + #clock-cells = <1>;
> > + };
> > diff --git a/include/dt-bindings/clock/imx8ulp-clock.h
> > b/include/dt-bindings/clock/imx8ulp-clock.h
> > new file mode 100644
> > index 000000000000..5bd2044633d3
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/imx8ulp-clock.h
> > @@ -0,0 +1,261 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
> > +/*
> > + * Copyright 2021 NXP
> > + */
> > +
> > +#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H #define
> > +__DT_BINDINGS_CLOCK_IMX8ULP_H
> > +
> > +#define IMX8ULP_CLK_DUMMY 0
> > +#define IMX8ULP_CLK_ROSC 1
> > +#define IMX8ULP_CLK_FROSC 2
> > +#define IMX8ULP_CLK_LPOSC 3
> > +#define IMX8ULP_CLK_SOSC 4
> > +
> > +/* CGC1 */
> > +#define IMX8ULP_CLK_SPLL2 5
> > +#define IMX8ULP_CLK_SPLL3 6
> > +#define IMX8ULP_CLK_A35_SEL 7
> > +#define IMX8ULP_CLK_A35_DIV 8
> > +#define IMX8ULP_CLK_SPLL2_PRE_SEL 9
> > +#define IMX8ULP_CLK_SPLL3_PRE_SEL 10
> > +#define IMX8ULP_CLK_SPLL3_PFD0 11
> > +#define IMX8ULP_CLK_SPLL3_PFD1 12
> > +#define IMX8ULP_CLK_SPLL3_PFD2 13
> > +#define IMX8ULP_CLK_SPLL3_PFD3 14
> > +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15
> > +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16
> > +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17
> > +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18
> > +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19
> > +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20
> > +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21
> > +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22
> > +#define IMX8ULP_CLK_NIC_SEL 23
> > +#define IMX8ULP_CLK_NIC_AD_DIVPLAT 24
> > +#define IMX8ULP_CLK_NIC_PER_DIVPLAT 25
> > +#define IMX8ULP_CLK_XBAR_SEL 26
> > +#define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27
> > +#define IMX8ULP_CLK_XBAR_DIVBUS 28
> > +#define IMX8ULP_CLK_XBAR_AD_SLOW 29
> > +#define IMX8ULP_CLK_SOSC_DIV1 30
> > +#define IMX8ULP_CLK_SOSC_DIV2 31
> > +#define IMX8ULP_CLK_SOSC_DIV3 32
> > +#define IMX8ULP_CLK_FROSC_DIV1 33
> > +#define IMX8ULP_CLK_FROSC_DIV2 34
> > +#define IMX8ULP_CLK_FROSC_DIV3 35
> > +#define IMX8ULP_CLK_SPLL3_VCODIV 36
> > +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37
> > +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38
> > +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39
> > +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40
> > +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41
> > +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42
> > +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43
> > +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44
> > +#define IMX8ULP_CLK_SOSC_DIV1_GATE 45
> > +#define IMX8ULP_CLK_SOSC_DIV2_GATE 46
> > +#define IMX8ULP_CLK_SOSC_DIV3_GATE 47
> > +#define IMX8ULP_CLK_FROSC_DIV1_GATE 48
> > +#define IMX8ULP_CLK_FROSC_DIV2_GATE 49
> > +#define IMX8ULP_CLK_FROSC_DIV3_GATE 50
> > +#define IMX8ULP_CLK_SAI4_SEL 51
> > +#define IMX8ULP_CLK_SAI5_SEL 52
> > +#define IMX8ULP_CLK_AUD_CLK1 53
> > +#define IMX8ULP_CLK_ARM 54
> > +#define IMX8ULP_CLK_ENET_TS_SEL 55
> > +
> > +#define IMX8ULP_CLK_CGC1_END 56
> > +
> > +/* CGC2 */
> > +#define IMX8ULP_CLK_PLL4_PRE_SEL 0
> > +#define IMX8ULP_CLK_PLL4 1
> > +#define IMX8ULP_CLK_PLL4_VCODIV 2
> > +#define IMX8ULP_CLK_DDR_SEL 3
> > +#define IMX8ULP_CLK_DDR_DIV 4
> > +#define IMX8ULP_CLK_LPAV_AXI_SEL 5
> > +#define IMX8ULP_CLK_LPAV_AXI_DIV 6
> > +#define IMX8ULP_CLK_LPAV_AHB_DIV 7
> > +#define IMX8ULP_CLK_LPAV_BUS_DIV 8
> > +#define IMX8ULP_CLK_PLL4_PFD0 9
> > +#define IMX8ULP_CLK_PLL4_PFD1 10
> > +#define IMX8ULP_CLK_PLL4_PFD2 11
> > +#define IMX8ULP_CLK_PLL4_PFD3 12
> > +#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13
> > +#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14
> > +#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15
> > +#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16
> > +#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17
> > +#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18
> > +#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19
> > +#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20
> > +#define IMX8ULP_CLK_PLL4_PFD0_DIV1 21
> > +#define IMX8ULP_CLK_PLL4_PFD0_DIV2 22
> > +#define IMX8ULP_CLK_PLL4_PFD1_DIV1 23
> > +#define IMX8ULP_CLK_PLL4_PFD1_DIV2 24
> > +#define IMX8ULP_CLK_PLL4_PFD2_DIV1 25
> > +#define IMX8ULP_CLK_PLL4_PFD2_DIV2 26
> > +#define IMX8ULP_CLK_PLL4_PFD3_DIV1 27
> > +#define IMX8ULP_CLK_PLL4_PFD3_DIV2 28
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV1 32
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV2 33
> > +#define IMX8ULP_CLK_CGC2_SOSC_DIV3 34
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV1 38
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV2 39
> > +#define IMX8ULP_CLK_CGC2_FROSC_DIV3 40
> > +#define IMX8ULP_CLK_AUD_CLK2 41
> > +#define IMX8ULP_CLK_SAI6_SEL 42
> > +#define IMX8ULP_CLK_SAI7_SEL 43
> > +#define IMX8ULP_CLK_SPDIF_SEL 44
> > +#define IMX8ULP_CLK_HIFI_SEL 45
> > +#define IMX8ULP_CLK_HIFI_DIVCORE 46
> > +#define IMX8ULP_CLK_HIFI_DIVPLAT 47
> > +#define IMX8ULP_CLK_DSI_PHY_REF 48
> > +
> > +#define IMX8ULP_CLK_CGC2_END 49
> > +
> > +/* PCC3 */
> > +#define IMX8ULP_CLK_WDOG3 0
> > +#define IMX8ULP_CLK_WDOG4 1
> > +#define IMX8ULP_CLK_LPIT1 2
> > +#define IMX8ULP_CLK_TPM4 3
> > +#define IMX8ULP_CLK_TPM5 4
> > +#define IMX8ULP_CLK_FLEXIO1 5
> > +#define IMX8ULP_CLK_I3C2 6
> > +#define IMX8ULP_CLK_LPI2C4 7
> > +#define IMX8ULP_CLK_LPI2C5 8
> > +#define IMX8ULP_CLK_LPUART4 9
> > +#define IMX8ULP_CLK_LPUART5 10
> > +#define IMX8ULP_CLK_LPSPI4 11
> > +#define IMX8ULP_CLK_LPSPI5 12
> > +#define IMX8ULP_CLK_DMA1_MP 13
> > +#define IMX8ULP_CLK_DMA1_CH0 14
> > +#define IMX8ULP_CLK_DMA1_CH1 15
> > +#define IMX8ULP_CLK_DMA1_CH2 16
> > +#define IMX8ULP_CLK_DMA1_CH3 17
> > +#define IMX8ULP_CLK_DMA1_CH4 18
> > +#define IMX8ULP_CLK_DMA1_CH5 19
> > +#define IMX8ULP_CLK_DMA1_CH6 20
> > +#define IMX8ULP_CLK_DMA1_CH7 21
> > +#define IMX8ULP_CLK_DMA1_CH8 22
> > +#define IMX8ULP_CLK_DMA1_CH9 23
> > +#define IMX8ULP_CLK_DMA1_CH10 24
> > +#define IMX8ULP_CLK_DMA1_CH11 25
> > +#define IMX8ULP_CLK_DMA1_CH12 26
> > +#define IMX8ULP_CLK_DMA1_CH13 27
> > +#define IMX8ULP_CLK_DMA1_CH14 28
> > +#define IMX8ULP_CLK_DMA1_CH15 29
> > +#define IMX8ULP_CLK_DMA1_CH16 30
> > +#define IMX8ULP_CLK_DMA1_CH17 31
> > +#define IMX8ULP_CLK_DMA1_CH18 32
> > +#define IMX8ULP_CLK_DMA1_CH19 33
> > +#define IMX8ULP_CLK_DMA1_CH20 34
> > +#define IMX8ULP_CLK_DMA1_CH21 35
> > +#define IMX8ULP_CLK_DMA1_CH22 36
> > +#define IMX8ULP_CLK_DMA1_CH23 37
> > +#define IMX8ULP_CLK_DMA1_CH24 38
> > +#define IMX8ULP_CLK_DMA1_CH25 39
> > +#define IMX8ULP_CLK_DMA1_CH26 40
> > +#define IMX8ULP_CLK_DMA1_CH27 41
> > +#define IMX8ULP_CLK_DMA1_CH28 42
> > +#define IMX8ULP_CLK_DMA1_CH29 43
> > +#define IMX8ULP_CLK_DMA1_CH30 44
> > +#define IMX8ULP_CLK_DMA1_CH31 45
> > +#define IMX8ULP_CLK_MU3_A 46
> > +
> > +#define IMX8ULP_CLK_PCC3_END 47
> > +
> > +/* PCC4 */
> > +#define IMX8ULP_CLK_FLEXSPI2 0
> > +#define IMX8ULP_CLK_TPM6 1
> > +#define IMX8ULP_CLK_TPM7 2
> > +#define IMX8ULP_CLK_LPI2C6 3
> > +#define IMX8ULP_CLK_LPI2C7 4
> > +#define IMX8ULP_CLK_LPUART6 5
> > +#define IMX8ULP_CLK_LPUART7 6
> > +#define IMX8ULP_CLK_SAI4 7
> > +#define IMX8ULP_CLK_SAI5 8
> > +#define IMX8ULP_CLK_PCTLE 9
> > +#define IMX8ULP_CLK_PCTLF 10
> > +#define IMX8ULP_CLK_USDHC0 11
> > +#define IMX8ULP_CLK_USDHC1 12
> > +#define IMX8ULP_CLK_USDHC2 13
> > +#define IMX8ULP_CLK_USB0 14
> > +#define IMX8ULP_CLK_USB0_PHY 15
> > +#define IMX8ULP_CLK_USB1 16
> > +#define IMX8ULP_CLK_USB1_PHY 17
> > +#define IMX8ULP_CLK_USB_XBAR 18
> > +#define IMX8ULP_CLK_ENET 19
> > +#define IMX8ULP_CLK_SFA1 20
> > +#define IMX8ULP_CLK_RGPIOE 21
> > +#define IMX8ULP_CLK_RGPIOF 22
> > +
> > +#define IMX8ULP_CLK_PCC4_END 23
> > +
> > +/* PCC5 */
> > +#define IMX8ULP_CLK_TPM8 0
> > +#define IMX8ULP_CLK_SAI6 1
> > +#define IMX8ULP_CLK_SAI7 2
> > +#define IMX8ULP_CLK_SPDIF 3
> > +#define IMX8ULP_CLK_ISI 4
> > +#define IMX8ULP_CLK_CSI_REGS 5
> > +#define IMX8ULP_CLK_PCTLD 6
> > +#define IMX8ULP_CLK_CSI 7
> > +#define IMX8ULP_CLK_DSI 8
> > +#define IMX8ULP_CLK_WDOG5 9
> > +#define IMX8ULP_CLK_EPDC 10
> > +#define IMX8ULP_CLK_PXP 11
> > +#define IMX8ULP_CLK_SFA2 12
> > +#define IMX8ULP_CLK_GPU2D 13
> > +#define IMX8ULP_CLK_GPU3D 14
> > +#define IMX8ULP_CLK_DC_NANO 15
> > +#define IMX8ULP_CLK_CSI_CLK_UI 16
> > +#define IMX8ULP_CLK_CSI_CLK_ESC 17
> > +#define IMX8ULP_CLK_RGPIOD 18
> > +#define IMX8ULP_CLK_DMA2_MP 19
> > +#define IMX8ULP_CLK_DMA2_CH0 20
> > +#define IMX8ULP_CLK_DMA2_CH1 21
> > +#define IMX8ULP_CLK_DMA2_CH2 22
> > +#define IMX8ULP_CLK_DMA2_CH3 23
> > +#define IMX8ULP_CLK_DMA2_CH4 24
> > +#define IMX8ULP_CLK_DMA2_CH5 25
> > +#define IMX8ULP_CLK_DMA2_CH6 26
> > +#define IMX8ULP_CLK_DMA2_CH7 27
> > +#define IMX8ULP_CLK_DMA2_CH8 28
> > +#define IMX8ULP_CLK_DMA2_CH9 29
> > +#define IMX8ULP_CLK_DMA2_CH10 30
> > +#define IMX8ULP_CLK_DMA2_CH11 31
> > +#define IMX8ULP_CLK_DMA2_CH12 32
> > +#define IMX8ULP_CLK_DMA2_CH13 33
> > +#define IMX8ULP_CLK_DMA2_CH14 34
> > +#define IMX8ULP_CLK_DMA2_CH15 35
> > +#define IMX8ULP_CLK_DMA2_CH16 36
> > +#define IMX8ULP_CLK_DMA2_CH17 37
> > +#define IMX8ULP_CLK_DMA2_CH18 38
> > +#define IMX8ULP_CLK_DMA2_CH19 39
> > +#define IMX8ULP_CLK_DMA2_CH20 40
> > +#define IMX8ULP_CLK_DMA2_CH21 41
> > +#define IMX8ULP_CLK_DMA2_CH22 42
> > +#define IMX8ULP_CLK_DMA2_CH23 43
> > +#define IMX8ULP_CLK_DMA2_CH24 44
> > +#define IMX8ULP_CLK_DMA2_CH25 45
> > +#define IMX8ULP_CLK_DMA2_CH26 46
> > +#define IMX8ULP_CLK_DMA2_CH27 47
> > +#define IMX8ULP_CLK_DMA2_CH28 48
> > +#define IMX8ULP_CLK_DMA2_CH29 49
> > +#define IMX8ULP_CLK_DMA2_CH30 50
> > +#define IMX8ULP_CLK_DMA2_CH31 51
> > +#define IMX8ULP_CLK_MU2_B 52
> > +#define IMX8ULP_CLK_MU3_B 53
> > +#define IMX8ULP_CLK_AVD_SIM 54
> > +#define IMX8ULP_CLK_DSI_TX_ESC 55
> > +
> > +#define IMX8ULP_CLK_PCC5_END 56
> > +
> > +#endif
> > --
> > 2.26.2
> >
> >
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^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-06-25 0:32 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-18 6:54 [PATCH v2 00/11] Add imx8ulp basic dtsi support Jacky Bai
2021-06-18 6:54 ` [PATCH v2 01/11] dt-bindings: gpio: gpio-vf610: Add imx8ulp compatible string Jacky Bai
2021-06-18 6:54 ` [PATCH v2 02/11] dt-bindings: i2c: imx-lpi2c: " Jacky Bai
2021-06-18 6:54 ` [PATCH v2 03/11] dt-bindings: mmc: imx-esdhc: " Jacky Bai
2021-06-18 6:54 ` [PATCH v2 04/11] dt-bindings: serial: fsl-lpuart: " Jacky Bai
2021-06-18 6:54 ` [PATCH v2 05/11] dt-bindings: spi: fsl-lpspi: " Jacky Bai
2021-06-18 6:54 ` [PATCH v2 06/11] dt-bindings: timer: tpm-timer: " Jacky Bai
2021-06-18 6:54 ` [PATCH v2 07/11] dt-bindings: watchdog: imx7ulp-wdt: " Jacky Bai
2021-06-18 6:54 ` [PATCH v2 08/11] dt-bindings: arm: fsl: Add binding for imx8ulp evk Jacky Bai
2021-06-18 6:54 ` [PATCH v2 09/11] dt-bindings: clock: Add imx8ulp clock support Jacky Bai
2021-06-24 21:36 ` Rob Herring
2021-06-25 0:30 ` Jacky Bai
2021-06-18 6:54 ` [PATCH v2 11/11] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board Jacky Bai
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