* [v3,1/3] dt-bindings: mediatek: mt8195: update mtk-wdt document
2021-06-23 9:29 [v3,0/3] watchdog: mt8195: add wdt support Christine Zhu
@ 2021-06-23 9:29 ` Christine Zhu
2021-06-23 9:48 ` Chen-Yu Tsai
2021-06-23 9:29 ` [v3, 2/3] dt-bindings: reset: mt8195: add toprgu reset-controller head file Christine Zhu
2021-06-23 9:29 ` [v3,3/3] watchdog: mediatek: mt8195: add wdt support Christine Zhu
2 siblings, 1 reply; 5+ messages in thread
From: Christine Zhu @ 2021-06-23 9:29 UTC (permalink / raw)
To: wim, linux, robh+dt, matthias.bgg
Cc: srv_heupstream, linux-mediatek, linux-arm-kernel, linux-kernel,
linux-watchdog, devicetree, seiya.wang, christine.zhu
From: "christine.zhu" <Christine.Zhu@mediatek.com>
Update mtk-wdt document for MT8195 platform.
Signed-off-by: christine.zhu <Christine.Zhu@mediatek.com>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index e36ba60de829..d15a321b22bc 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -13,6 +13,7 @@ Required properties:
"mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
+ "mediatek,mt8195-wdt": for MT8195
- reg : Specifies base physical address and size of the registers.
--
2.18.0
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* Re: [v3,1/3] dt-bindings: mediatek: mt8195: update mtk-wdt document
2021-06-23 9:29 ` [v3,1/3] dt-bindings: mediatek: mt8195: update mtk-wdt document Christine Zhu
@ 2021-06-23 9:48 ` Chen-Yu Tsai
0 siblings, 0 replies; 5+ messages in thread
From: Chen-Yu Tsai @ 2021-06-23 9:48 UTC (permalink / raw)
To: Christine Zhu
Cc: wim, linux, Rob Herring, Matthias Brugger, srv_heupstream,
linux-mediatek, linux-arm-kernel, linux-kernel, linux-watchdog,
devicetree, seiya.wang
Hi,
On Wed, Jun 23, 2021 at 5:30 PM Christine Zhu
<Christine.Zhu@mediatek.com> wrote:
>
> From: "christine.zhu" <Christine.Zhu@mediatek.com>
>
> Update mtk-wdt document for MT8195 platform.
>
> Signed-off-by: christine.zhu <Christine.Zhu@mediatek.com>
Please fix your name formatting in your Signed-off-bys and author
for all the patches, and in your overall git setup.
It should read "Christine Zhu", like your sender info on this
email, not "christine.zhu" like an account name.
ChenYu
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* [v3, 2/3] dt-bindings: reset: mt8195: add toprgu reset-controller head file
2021-06-23 9:29 [v3,0/3] watchdog: mt8195: add wdt support Christine Zhu
2021-06-23 9:29 ` [v3,1/3] dt-bindings: mediatek: mt8195: update mtk-wdt document Christine Zhu
@ 2021-06-23 9:29 ` Christine Zhu
2021-06-23 9:29 ` [v3,3/3] watchdog: mediatek: mt8195: add wdt support Christine Zhu
2 siblings, 0 replies; 5+ messages in thread
From: Christine Zhu @ 2021-06-23 9:29 UTC (permalink / raw)
To: wim, linux, robh+dt, matthias.bgg
Cc: srv_heupstream, linux-mediatek, linux-arm-kernel, linux-kernel,
linux-watchdog, devicetree, seiya.wang, christine.zhu
From: "christine.zhu" <Christine.Zhu@mediatek.com>
Add toprgu reset-controller head file for MT8195 platform.
Signed-off-by: christine.zhu <Christine.Zhu@mediatek.com>
---
.../reset-controller/mt8195-resets.h | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 include/dt-bindings/reset-controller/mt8195-resets.h
diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset-controller/mt8195-resets.h
new file mode 100644
index 000000000000..7ec27a64afc7
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8195-resets.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Crystal Guo <crystal.guo@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8195
+
+#define MT8195_TOPRGU_CONN_MCU_SW_RST 0
+#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1
+#define MT8195_TOPRGU_APU_SW_RST 2
+#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6
+#define MT8195_TOPRGU_MMSYS_SW_RST 7
+#define MT8195_TOPRGU_MFG_SW_RST 8
+#define MT8195_TOPRGU_VENC_SW_RST 9
+#define MT8195_TOPRGU_VDEC_SW_RST 10
+#define MT8195_TOPRGU_IMG_SW_RST 11
+#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13
+#define MT8195_TOPRGU_AUDIO_SW_RST 14
+#define MT8195_TOPRGU_CAMSYS_SW_RST 15
+#define MT8195_TOPRGU_EDPTX_SW_RST 16
+#define MT8195_TOPRGU_ADSPSYS_SW_RST 21
+#define MT8195_TOPRGU_DPTX_SW_RST 22
+#define MT8195_TOPRGU_SPMI_MST_SW_RST 23
+
+#define MT8195_TOPRGU_SW_RST_NUM 16
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
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* [v3,3/3] watchdog: mediatek: mt8195: add wdt support
2021-06-23 9:29 [v3,0/3] watchdog: mt8195: add wdt support Christine Zhu
2021-06-23 9:29 ` [v3,1/3] dt-bindings: mediatek: mt8195: update mtk-wdt document Christine Zhu
2021-06-23 9:29 ` [v3, 2/3] dt-bindings: reset: mt8195: add toprgu reset-controller head file Christine Zhu
@ 2021-06-23 9:29 ` Christine Zhu
2 siblings, 0 replies; 5+ messages in thread
From: Christine Zhu @ 2021-06-23 9:29 UTC (permalink / raw)
To: wim, linux, robh+dt, matthias.bgg
Cc: srv_heupstream, linux-mediatek, linux-arm-kernel, linux-kernel,
linux-watchdog, devicetree, seiya.wang, christine.zhu
From: "christine.zhu" <Christine.Zhu@mediatek.com>
Support MT8195 watchdog device.
Signed-off-by: christine.zhu <Christine.Zhu@mediatek.com>
---
drivers/watchdog/mtk_wdt.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index 97ca993bd009..8231cb9cf5f9 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -12,6 +12,7 @@
#include <dt-bindings/reset-controller/mt2712-resets.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
#include <dt-bindings/reset-controller/mt8192-resets.h>
+#include <dt-bindings/reset-controller/mt8195-resets.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
@@ -81,6 +82,10 @@ static const struct mtk_wdt_data mt8192_data = {
.toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
};
+static const struct mtk_wdt_data mt8195_data = {
+ .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
+};
+
static int toprgu_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
@@ -341,6 +346,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = {
{ .compatible = "mediatek,mt6589-wdt" },
{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
+ { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
--
2.18.0
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