* [PATCH v8 01/13] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-19 15:00 ` Chun-Kuang Hu
2021-08-19 2:23 ` [PATCH v8 02/13] dt-bindings: mediatek: display: split each block to individual yaml jason-jh.lin
` (11 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
1. There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
Each of them is bound to a display pipeline, so add their
definition in mtk-mmsys documentation with 2 compatibles.
2. Add description for power-domain property.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
this patch is base on [1][2]
[1] dt-bindings: arm: mediatek: mmsys: convert to YAML format
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210519161847.3747352-1-fparent@baylibre.com/
[2] dt-bindings: arm: mediatek: mmsys: add MT8365 SoC binding
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210519161847.3747352-2-fparent@baylibre.com/
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 2d4ff0ce387b..68cb330d7595 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -30,6 +30,8 @@ properties:
- mediatek,mt8173-mmsys
- mediatek,mt8183-mmsys
- mediatek,mt8365-mmsys
+ - mediatek,mt8195-vdosys0
+ - mediatek,mt8195-vdosys1
- const: syscon
- items:
- const: mediatek,mt7623-mmsys
@@ -39,6 +41,12 @@ properties:
reg:
maxItems: 1
+ power-domains:
+ description:
+ A phandle and PM domain specifier as defined by bindings
+ of the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
"#clock-cells":
const: 1
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v8 01/13] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
2021-08-19 2:23 ` [PATCH v8 01/13] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
@ 2021-08-19 15:00 ` Chun-Kuang Hu
2021-08-24 16:11 ` Jason-JH Lin
0 siblings, 1 reply; 28+ messages in thread
From: Chun-Kuang Hu @ 2021-08-19 15:00 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao,
Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, Hsin-Yi Wang, Yongqiang Niu,
Jitao shi, Nancy Lin, singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道：
>
> 1. There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
> Each of them is bound to a display pipeline, so add their
> definition in mtk-mmsys documentation with 2 compatibles.
>
> 2. Add description for power-domain property.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> this patch is base on [1][2]
>
> [1] dt-bindings: arm: mediatek: mmsys: convert to YAML format
> - https://patchwork.kernel.org/project/linux-mediatek/patch/20210519161847.3747352-1-fparent@baylibre.com/
> [2] dt-bindings: arm: mediatek: mmsys: add MT8365 SoC binding
> - https://patchwork.kernel.org/project/linux-mediatek/patch/20210519161847.3747352-2-fparent@baylibre.com/
> ---
> .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index 2d4ff0ce387b..68cb330d7595 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -30,6 +30,8 @@ properties:
> - mediatek,mt8173-mmsys
> - mediatek,mt8183-mmsys
> - mediatek,mt8365-mmsys
> + - mediatek,mt8195-vdosys0
> + - mediatek,mt8195-vdosys1
> - const: syscon
> - items:
> - const: mediatek,mt7623-mmsys
> @@ -39,6 +41,12 @@ properties:
> reg:
> maxItems: 1
>
> + power-domains:
> + description:
> + A phandle and PM domain specifier as defined by bindings
> + of the power controller specified by phandle. See
> + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
This patch is about mt8195, but mt8173 mmsys also has power domain. So
move this part to another patch.
Regards,
Chun-Kuang.
> "#clock-cells":
> const: 1
>
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v8 01/13] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
2021-08-19 15:00 ` Chun-Kuang Hu
@ 2021-08-24 16:11 ` Jason-JH Lin
0 siblings, 0 replies; 28+ messages in thread
From: Jason-JH Lin @ 2021-08-24 16:11 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, fshao, Philipp Zabel,
Enric Balletbo i Serra, David Airlie, Daniel Vetter,
Fabien Parent, Hsin-Yi Wang, Yongqiang Niu, Jitao shi, Nancy Lin,
singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi Chun-Kuang,
Thanks for the review.
On Thu, 2021-08-19 at 23:00 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道：
> >
> > 1. There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
> > Each of them is bound to a display pipeline, so add their
> > definition in mtk-mmsys documentation with 2 compatibles.
> >
> > 2. Add description for power-domain property.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > this patch is base on [1][2]
> >
> > [1] dt-bindings: arm: mediatek: mmsys: convert to YAML format
> > -
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210519161847.3747352-1-fparent@baylibre.com/__;!!CTRNKA9wMg0ARbw!w8o5bmoiLe92jLT1-_lV_0q9mlcvIOcACUoTI-VjaVv3tGtKr414AQyDnf1ywivw9BHJ$
> >
> > [2] dt-bindings: arm: mediatek: mmsys: add MT8365 SoC binding
> > -
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210519161847.3747352-2-fparent@baylibre.com/__;!!CTRNKA9wMg0ARbw!w8o5bmoiLe92jLT1-_lV_0q9mlcvIOcACUoTI-VjaVv3tGtKr414AQyDnf1ywmNF79JZ$
> >
> > ---
> > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 8
> > ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > index 2d4ff0ce387b..68cb330d7595 100644
> > ---
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > @@ -30,6 +30,8 @@ properties:
> > - mediatek,mt8173-mmsys
> > - mediatek,mt8183-mmsys
> > - mediatek,mt8365-mmsys
> > + - mediatek,mt8195-vdosys0
> > + - mediatek,mt8195-vdosys1
> > - const: syscon
> > - items:
> > - const: mediatek,mt7623-mmsys
> > @@ -39,6 +41,12 @@ properties:
> > reg:
> > maxItems: 1
> >
> > + power-domains:
> > + description:
> > + A phandle and PM domain specifier as defined by bindings
> > + of the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml
> > for details.
> > +
>
> This patch is about mt8195, but mt8173 mmsys also has power domain.
> So
> move this part to another patch.
>
> Regards,
> Chun-Kuang.
>
OK, I'll move this part to another patch.
Regards,
Jason-JH.Lin
>
> > "#clock-cells":
> > const: 1
> >
> > --
> > 2.18.0
> >
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v8 02/13] dt-bindings: mediatek: display: split each block to individual yaml
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 01/13] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 03/13] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding jason-jh.lin
` (10 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
1. Remove mediatek,dislpay.txt
2. Split each display function block to individual yaml file.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../display/mediatek/mediatek,aal.yaml | 75 ++++++
.../display/mediatek/mediatek,ccorr.yaml | 69 ++++++
.../display/mediatek/mediatek,color.yaml | 84 +++++++
.../display/mediatek/mediatek,disp.txt | 219 ------------------
.../display/mediatek/mediatek,dither.yaml | 70 ++++++
.../display/mediatek/mediatek,gamma.yaml | 71 ++++++
.../display/mediatek/mediatek,merge.yaml | 57 +++++
.../display/mediatek/mediatek,mutex.yaml | 77 ++++++
.../display/mediatek/mediatek,od.yaml | 52 +++++
.../display/mediatek/mediatek,ovl-2l.yaml | 86 +++++++
.../display/mediatek/mediatek,ovl.yaml | 96 ++++++++
.../display/mediatek/mediatek,rdma.yaml | 110 +++++++++
.../display/mediatek/mediatek,split.yaml | 56 +++++
.../display/mediatek/mediatek,ufoe.yaml | 59 +++++
.../display/mediatek/mediatek,wdma.yaml | 86 +++++++
15 files changed, 1048 insertions(+), 219 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
new file mode 100644
index 000000000000..7be772d77e36
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display adaptive ambient light processor
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display adaptive ambient light processor, namely AAL,
+ is responsible for backlight power saving and sunlight visibility improving.
+ AAL device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-aal
+ - items:
+ - enum:
+ - mediatek,mt2712-disp-aal
+ - mediatek,mt8183-disp-aal
+ - enum:
+ - mediatek,mt8173-disp-aal
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: AAL Clock
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ aal@14015000 {
+ compatible = "mediatek,mt8173-disp-aal";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_AAL>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
new file mode 100644
index 000000000000..5a1c27d6b3e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek Ddsplay color correction
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display color correction, namely CCORR, reproduces correct color
+ on panels with different color gamut.
+ CCORR device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8183-disp-ccorr
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: CCORR Clock
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ ccorr0: ccorr@1400f000 {
+ compatible = "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+ }
+;
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
new file mode 100644
index 000000000000..9a3edf6f0b8e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display color processor
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek color processor, namely COLOR, provides hue, luma and
+ saturation adjustments to get better picture quality and to have one panel
+ resemble the other in their output characteristics.
+ COLOR device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt2701-disp-color
+ - items:
+ - const: mediatek,mt8167-disp-color
+ - items:
+ - const: mediatek,mt8173-disp-color
+ - items:
+ - enum:
+ - mediatek,mt7623-disp-color
+ - mediatek,mt2712-disp-color
+ - enum:
+ - mediatek,mt2701-disp-color
+ - items:
+ - enum:
+ - mediatek,mt8183-disp-color
+ - enum:
+ - mediatek,mt8173-disp-color
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: COLOR Clock
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ color0: color@14013000 {
+ compatible = "mediatek,mt8173-disp-color";
+ reg = <0 0x14013000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
deleted file mode 100644
index fbb59c9ddda6..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ /dev/null
@@ -1,219 +0,0 @@
-Mediatek display subsystem
-==========================
-
-The Mediatek display subsystem consists of various DISP function blocks in the
-MMSYS register space. The connections between them can be configured by output
-and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
-of frame signal are distributed to the other function blocks by a DISP_MUTEX
-function block.
-
-All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
-For a description of the MMSYS_CONFIG binding, see
-Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
-
-DISP function blocks
-====================
-
-A display stream starts at a source function block that reads pixel data from
-memory and ends with a sink function block that drives pixels on a display
-interface, or writes pixels back to memory. All DISP function blocks have
-their own register space, interrupt, and clock gate. The blocks that can
-access memory additionally have to list the IOMMU and local arbiter they are
-connected to.
-
-For a description of the display interface sink function blocks, see
-Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
-Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
-
-Required properties (all function blocks):
-- compatible: "mediatek,<chip>-disp-<function>", one of
- "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
- "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
- "mediatek,<chip>-disp-rdma" - read DMA / line buffer
- "mediatek,<chip>-disp-wdma" - write DMA
- "mediatek,<chip>-disp-ccorr" - color correction
- "mediatek,<chip>-disp-color" - color processor
- "mediatek,<chip>-disp-dither" - dither
- "mediatek,<chip>-disp-aal" - adaptive ambient light controller
- "mediatek,<chip>-disp-gamma" - gamma correction
- "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
- "mediatek,<chip>-disp-postmask" - control round corner for display frame
- "mediatek,<chip>-disp-split" - split stream to two encoders
- "mediatek,<chip>-disp-ufoe" - data compression engine
- "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
- "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
- "mediatek,<chip>-disp-mutex" - display mutex
- "mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
-- reg: Physical base address and length of the function block register space
-- interrupts: The interrupt signal from the function block (required, except for
- merge and split function blocks).
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- For most function blocks this is just a single clock input. Only the DSI and
- DPI controller nodes have multiple clock inputs. These are documented in
- mediatek,dsi.txt and mediatek,dpi.txt, respectively.
- An exception is that the mt8183 mutex is always free running with no clocks property.
-
-Required properties (DMA function blocks):
-- compatible: Should be one of
- "mediatek,<chip>-disp-ovl"
- "mediatek,<chip>-disp-rdma"
- "mediatek,<chip>-disp-wdma"
- the supported chips are mt2701, mt8167 and mt8173.
-- larb: Should contain a phandle pointing to the local arbiter device as defined
- in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
-- iommus: Should point to the respective IOMMU block with master port as
- argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
- for details.
-
-Optional properties (RDMA function blocks):
-- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
- property to the corresponding rdma
- the value is the Max value which defined in hardware data sheet.
- mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
- mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
- mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
-
-Examples:
-
-mmsys: clock-controller@14000000 {
- compatible = "mediatek,mt8173-mmsys", "syscon";
- reg = <0 0x14000000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- #clock-cells = <1>;
-};
-
-ovl0: ovl@1400c000 {
- compatible = "mediatek,mt8173-disp-ovl";
- reg = <0 0x1400c000 0 0x1000>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OVL0>;
- iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
-};
-
-ovl1: ovl@1400d000 {
- compatible = "mediatek,mt8173-disp-ovl";
- reg = <0 0x1400d000 0 0x1000>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OVL1>;
- iommus = <&iommu M4U_PORT_DISP_OVL1>;
- mediatek,larb = <&larb4>;
-};
-
-rdma0: rdma@1400e000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x1400e000 0 0x1000>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA0>;
- iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
- mediatek,rdma-fifosize = <8192>;
-};
-
-rdma1: rdma@1400f000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x1400f000 0 0x1000>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA1>;
- iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb4>;
-};
-
-rdma2: rdma@14010000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x14010000 0 0x1000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA2>;
- iommus = <&iommu M4U_PORT_DISP_RDMA2>;
- mediatek,larb = <&larb4>;
-};
-
-wdma0: wdma@14011000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14011000 0 0x1000>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA0>;
- iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,larb = <&larb0>;
-};
-
-wdma1: wdma@14012000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14012000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA1>;
- iommus = <&iommu M4U_PORT_DISP_WDMA1>;
- mediatek,larb = <&larb4>;
-};
-
-color0: color@14013000 {
- compatible = "mediatek,mt8173-disp-color";
- reg = <0 0x14013000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_COLOR0>;
-};
-
-color1: color@14014000 {
- compatible = "mediatek,mt8173-disp-color";
- reg = <0 0x14014000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_COLOR1>;
-};
-
-aal@14015000 {
- compatible = "mediatek,mt8173-disp-aal";
- reg = <0 0x14015000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_AAL>;
-};
-
-gamma@14016000 {
- compatible = "mediatek,mt8173-disp-gamma";
- reg = <0 0x14016000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_GAMMA>;
-};
-
-ufoe@1401a000 {
- compatible = "mediatek,mt8173-disp-ufoe";
- reg = <0 0x1401a000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_UFOE>;
-};
-
-dsi0: dsi@1401b000 {
- /* See mediatek,dsi.txt for details */
-};
-
-dpi0: dpi@1401d000 {
- /* See mediatek,dpi.txt for details */
-};
-
-mutex: mutex@14020000 {
- compatible = "mediatek,mt8173-disp-mutex";
- reg = <0 0x14020000 0 0x1000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_MUTEX_32K>;
-};
-
-od@14023000 {
- compatible = "mediatek,mt8173-disp-od";
- reg = <0 0x14023000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OD>;
-};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
new file mode 100644
index 000000000000..20419f876410
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display dither processor
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display dither processor, namely DITHER, works by approximating
+ unavailable colors with available colors and by mixing and matching available
+ colors to mimic unavailable ones.
+ DITHER device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8183-disp-dither
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: DITHER Clock
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ dither0: dither@14012000 {
+ compatible = "mediatek,mt8183-disp-dither";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
new file mode 100644
index 000000000000..e2a1fc218e4f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display gamma correction
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display gamma correction, namely GAMMA, provides a nonlinear operation
+ used to adjust luminance in display system.
+ GAMMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-gamma
+ - items:
+ - const: mediatek,mt8183-disp-gamma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: GAMMA Clock
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ gamma@14016000 {
+ compatible = "mediatek,mt8173-disp-gamma";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
new file mode 100644
index 000000000000..4cdce11d7fcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display merge
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display merge engine is used to merge two slice-per-line inputs
+ into one side-by-side output.
+ MERGE device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-merge
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: MERGE Clock
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ merge@14017000 {
+ compatible = "mediatek,mt8173-disp-merge";
+ reg = <0 0x14017000 0 0x1000>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_MERGE>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
new file mode 100644
index 000000000000..aaba6bbfb4da
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display mutex
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display mutex is used to send the triggers signals called
+ Start Of Frame (SOF)/ Error Of Frame (EOF) to each sub-modules on the
+ display data path.
+ MUTEX device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt2701-disp-mutex
+ - items:
+ - const: mediatek,mt2712-disp-mutex
+ - items:
+ - const: mediatek,mt8167-disp-mutex
+ - items:
+ - const: mediatek,mt8173-disp-mutex
+ - items:
+ - const: mediatek,mt8183-disp-mutex
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: MUTEX Clock
+
+ mediatek,gce-events:
+ description:
+ The event id which is mapping to the specific hardware event signal to gce.
+ The event id is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ mutex: mutex@14020000 {
+ compatible = "mediatek,mt8173-disp-mutex";
+ reg = <0 0x14020000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
+ <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
new file mode 100644
index 000000000000..bcf3fddd9231
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display overdirve
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display overdrive, namely OD, increases the transition values
+ of pixels between consecutive frames to make LCD rotate faster.
+ OD device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt2712-disp-od
+ - items:
+ - const: mediatek,mt8173-disp-od
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: OVL Clock
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ od@14023000 {
+ compatible = "mediatek,mt8173-disp-od";
+ reg = <0 0x14023000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_OD>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
new file mode 100644
index 000000000000..6255074bf415
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display overlay 2 layer
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display overlay provides 2 more layer for OVL.
+ OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8183-disp-ovl-2l
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: OVL-2L Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,larb:
+ description:
+ This property should contain a phandle pointing to the local arbiter deviceas defined in
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+ It must sort according to the local arbiter index, like larb0, larb1, larb2...
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 32
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+
+ ovl_2l0: ovl@14009000 {
+ compatible = "mediatek,mt8183-disp-ovl-2l";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
+ mediatek,larb = <&larb0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
new file mode 100644
index 000000000000..833b0ca09b21
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display overlay
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display overlay, namely OVL, can do alpha blending from the memory.
+ OVL device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt2701-disp-ovl
+ - items:
+ - const: mediatek,mt8173-disp-ovl
+ - items:
+ - const: mediatek,mt8183-disp-ovl
+ - items:
+ - enum:
+ - mediatek,mt7623-disp-ovl
+ - mediatek,mt2712-disp-ovl
+ - enum:
+ - mediatek,mt2701-disp-ovl
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: OVL Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,larb:
+ description:
+ This property should contain a phandle pointing to the local arbiter deviceas defined in
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+ It must sort according to the local arbiter index, like larb0, larb1, larb2...
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 32
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+ - iommu
+
+additionalProperties: false
+
+examples:
+ - |
+
+ ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
new file mode 100644
index 000000000000..ce3bcca30609
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display RDMA
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display RDMA stands for Read Direct Memory Access.
+ It provides real time data to the back-end panel driver, such as DSI,
+ DPI and DP_INTF.
+ It contains one line buffer to store the sufficient pixel data.
+ RDMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt2701-disp-rdma
+ - items:
+ - const: mediatek,mt8173-disp-rdma
+ - items:
+ - const: mediatek,mt8183-disp-rdma
+ - items:
+ - enum:
+ - mediatek,mt7623-disp-rdma
+ - mediatek,mt2712-disp-rdma
+ - enum:
+ - mediatek,mt2701-disp-rdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: RDMA Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,larb:
+ description:
+ This property should contain a phandle pointing to the local arbiter deviceas defined in
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+ It must sort according to the local arbiter index, like larb0, larb1, larb2...
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 32
+
+ mediatek,rdma-fifo-size:
+ description:
+ rdma fifo size may be different even in same SOC, add this property to the
+ corresponding rdma.
+ The value below is the Max value which defined in hardware data sheet
+ mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
+ mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
+ mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [8192, 5120, 2048]
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+
+ rdma0: rdma@1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,rdma-fifosize = <8192>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
new file mode 100644
index 000000000000..d751e0a0c3a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display split
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display split engine is used to split stream to two encoders.
+ SPLIT device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-split
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: SPLIT Clock
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ split0: split@14018000 {
+ compatible = "mediatek,mt8173-disp-split";
+ reg = <0 0x14018000 0 0x1000>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
new file mode 100644
index 000000000000..d0249333a2bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display UFOe
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The Mediatek display UFOe stands for Unified Frame Optimization engine.
+ UFOe can cut the data rate for DSI port which may lead to reduce power consumption.
+ UFOe device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-ufoe
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: UFOe Clock
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ ufoe@1401a000 {
+ compatible = "mediatek,mt8173-disp-ufoe";
+ reg = <0 0x1401a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_UFOE>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
new file mode 100644
index 000000000000..d7a3ba497fb9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display WDMA
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The mediatek display WDMA stands for Write Direct Memory Access.
+ It can write the data in display pipeline into DRAM.
+ WDMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8173-disp-wdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: WDMA Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,larb:
+ description:
+ This property should contain a phandle pointing to the local arbiter deviceas defined in
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+ It must sort according to the local arbiter index, like larb0, larb1, larb2...
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 32
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+
+ wdma0: wdma@14011000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+ };
+
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v8 03/13] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 01/13] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 02/13] dt-bindings: mediatek: display: split each block to individual yaml jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-21 23:14 ` Chun-Kuang Hu
2021-08-19 2:23 ` [PATCH v8 04/13] dt-bindings: mediatek: display: add " jason-jh.lin
` (9 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
1. Add mediatek,dsc.yaml to describe DSC module in details.
2. Add mt8195 SoC binding to mediatek,dsc.yaml.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../display/mediatek/mediatek,dsc.yaml | 69 +++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
new file mode 100644
index 000000000000..f94a95c6a1c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display DSC controller
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+
+description: |
+ The DSC standard is a specification of the algorithms used for
+ compressing and decompressing image display streams, including
+ the specification of the syntax and semantics of the compressed
+ video bit stream. DSC is designed for real-time systems with
+ real-time compression, transmission, decompression and Display.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-disp-dsc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: DSC Wrapper Clock
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ dsc0: disp_dsc_wrap@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v8 03/13] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding
2021-08-19 2:23 ` [PATCH v8 03/13] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding jason-jh.lin
@ 2021-08-21 23:14 ` Chun-Kuang Hu
2021-08-24 17:59 ` [PATCH v8 03/13] dt-bindings: mediatek: add mediatek,dsc.yaml " Jason-JH Lin
0 siblings, 1 reply; 28+ messages in thread
From: Chun-Kuang Hu @ 2021-08-21 23:14 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao,
Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, Hsin-Yi Wang, Yongqiang Niu,
Jitao shi, Nancy Lin, singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道：
>
> 1. Add mediatek,dsc.yaml to describe DSC module in details.
> 2. Add mt8195 SoC binding to mediatek,dsc.yaml.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> .../display/mediatek/mediatek,dsc.yaml | 69 +++++++++++++++++++
> 1 file changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
> new file mode 100644
> index 000000000000..f94a95c6a1c5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
> @@ -0,0 +1,69 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: mediatek display DSC controller
> +
> +maintainers:
> + - CK Hu <ck.hu@mediatek.com>
According to [1], the maintainer should be
Chun-Kuang Hu <chunkuang.hu@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>
[1] https://www.kernel.org/doc/html/latest/process/maintainers.html
> +
> +description: |
> + The DSC standard is a specification of the algorithms used for
> + compressing and decompressing image display streams, including
> + the specification of the syntax and semantics of the compressed
> + video bit stream. DSC is designed for real-time systems with
> + real-time compression, transmission, decompression and Display.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: mediatek,mt8195-disp-dsc
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: DSC Wrapper Clock
> +
> + power-domains:
> + description: A phandle and PM domain specifier as defined by bindings of
> + the power controller specified by phandle. See
> + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> + mediatek,gce-client-reg:
> + description:
> + The register of display function block to be set by gce. There are 4 arguments,
> + such as gce node, subsys id, offset and register size. The subsys id that is
> + mapping to the register of display function blocks is defined in the gce header
> + include/include/dt-bindings/gce/<chip>-gce.h of each chips.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - power-domains
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + dsc0: disp_dsc_wrap@1c009000 {
> + compatible = "mediatek,mt8195-disp-dsc";
> + reg = <0 0x1c009000 0 0x1000>;
> + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
> + };
> +
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v8 03/13] dt-bindings: mediatek: add mediatek,dsc.yaml for mt8195 SoC binding
2021-08-21 23:14 ` Chun-Kuang Hu
@ 2021-08-24 17:59 ` Jason-JH Lin
0 siblings, 0 replies; 28+ messages in thread
From: Jason-JH Lin @ 2021-08-24 17:59 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, fshao, Philipp Zabel,
Enric Balletbo i Serra, David Airlie, Daniel Vetter,
Fabien Parent, Hsin-Yi Wang, Yongqiang Niu, Jitao shi, Nancy Lin,
singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi Chun-Kuang,
Thanks for the review.
On Sun, 2021-08-22 at 07:14 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道：
> >
> > 1. Add mediatek,dsc.yaml to describe DSC module in details.
> > 2. Add mt8195 SoC binding to mediatek,dsc.yaml.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > .../display/mediatek/mediatek,dsc.yaml | 69
> > +++++++++++++++++++
> > 1 file changed, 69 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yam
> > l
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.y
> > aml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.y
> > aml
> > new file mode 100644
> > index 000000000000..f94a95c6a1c5
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.y
> > aml
> > @@ -0,0 +1,69 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml*__;Iw!!CTRNKA9wMg0ARbw!2qwvJnFTgJzfk1n0OVXqGlPjYco2bBUZtWFzb4n8gzHXyFFJZ7MT4QWO4RDznHmSWyiO$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2qwvJnFTgJzfk1n0OVXqGlPjYco2bBUZtWFzb4n8gzHXyFFJZ7MT4QWO4RDznNC1w7FX$
> >
> > +
> > +title: mediatek display DSC controller
> > +
> > +maintainers:
> > + - CK Hu <ck.hu@mediatek.com>
>
> According to [1], the maintainer should be
>
> Chun-Kuang Hu <chunkuang.hu@kernel.org>, Philipp Zabel <
> p.zabel@pengutronix.de>
>
> [1]
> https://urldefense.com/v3/__https://www.kernel.org/doc/html/latest/process/maintainers.html__;!!CTRNKA9wMg0ARbw!2qwvJnFTgJzfk1n0OVXqGlPjYco2bBUZtWFzb4n8gzHXyFFJZ7MT4QWO4RDznMdx7tAe$
>
OK, I'll fix it and also the [PATCH v8 02/13] in this series.
Regards,
Jason-JH.Lin
>
> > +
> > +description: |
> > + The DSC standard is a specification of the algorithms used for
> > + compressing and decompressing image display streams, including
> > + the specification of the syntax and semantics of the compressed
> > + video bit stream. DSC is designed for real-time systems with
> > + real-time compression, transmission, decompression and Display.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: mediatek,mt8195-disp-dsc
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: DSC Wrapper Clock
> > +
> > + power-domains:
> > + description: A phandle and PM domain specifier as defined by
> > bindings of
> > + the power controller specified by phandle. See
> > + Documentation/devicetree/bindings/power/power-domain.yaml
> > for details.
> > +
> > + mediatek,gce-client-reg:
> > + description:
> > + The register of display function block to be set by gce.
> > There are 4 arguments,
> > + such as gce node, subsys id, offset and register size. The
> > subsys id that is
> > + mapping to the register of display function blocks is
> > defined in the gce header
> > + include/include/dt-bindings/gce/<chip>-gce.h of each
> > chips.
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + dsc0: disp_dsc_wrap@1c009000 {
> > + compatible = "mediatek,mt8195-disp-dsc";
> > + reg = <0 0x1c009000 0 0x1000>;
> > + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
> > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000
> > 0x1000>;
> > + };
> > +
> > --
> > 2.18.0
> >
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v8 04/13] dt-bindings: mediatek: display: add mt8195 SoC binding
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (2 preceding siblings ...)
2021-08-19 2:23 ` [PATCH v8 03/13] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 05/13] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
` (8 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
1. Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
MUTEX, OVL and RDMA yaml schema.
2. Add MERGE additional property description for mt8195
- async clock
- fifo setting enable
- reset controller
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../display/mediatek/mediatek,aal.yaml | 1 +
.../display/mediatek/mediatek,ccorr.yaml | 5 +++
.../display/mediatek/mediatek,color.yaml | 1 +
.../display/mediatek/mediatek,dither.yaml | 5 +++
.../display/mediatek/mediatek,gamma.yaml | 5 +++
.../display/mediatek/mediatek,merge.yaml | 40 +++++++++++++++++++
.../display/mediatek/mediatek,mutex.yaml | 2 +
.../display/mediatek/mediatek,ovl.yaml | 5 +++
.../display/mediatek/mediatek,rdma.yaml | 2 +
9 files changed, 66 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
index 7be772d77e36..e1820238db43 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -25,6 +25,7 @@ properties:
- enum:
- mediatek,mt2712-disp-aal
- mediatek,mt8183-disp-aal
+ - mediatek,mt8195-disp-aal
- enum:
- mediatek,mt8173-disp-aal
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index 5a1c27d6b3e2..4c556a2bc64a 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -21,6 +21,11 @@ properties:
oneOf:
- items:
- const: mediatek,mt8183-disp-ccorr
+ - items:
+ - enum:
+ - mediatek,mt8195-disp-ccorr
+ - enum:
+ - mediatek,mt8183-disp-ccorr
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
index 9a3edf6f0b8e..a13096196a0c 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -35,6 +35,7 @@ properties:
- items:
- enum:
- mediatek,mt8183-disp-color
+ - mediatek,mt8195-disp-color
- enum:
- mediatek,mt8173-disp-color
reg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
index 20419f876410..e89fe7393291 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -22,6 +22,11 @@ properties:
oneOf:
- items:
- const: mediatek,mt8183-disp-dither
+ - items:
+ - enum:
+ - mediatek,mt8195-disp-dither
+ - enum:
+ - mediatek,mt8183-disp-dither
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
index e2a1fc218e4f..dc78d6d05dee 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -23,6 +23,11 @@ properties:
- const: mediatek,mt8173-disp-gamma
- items:
- const: mediatek,mt8183-disp-gamma
+ - items:
+ - enum:
+ - mediatek,mt8195-disp-gamma
+ - enum:
+ - mediatek,mt8183-disp-gamma
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 4cdce11d7fcd..1a27b037086b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -21,6 +21,8 @@ properties:
oneOf:
- items:
- const: mediatek,mt8173-disp-merge
+ - items:
+ - const: mediatek,mt8195-disp-merge
reg:
maxItems: 1
@@ -36,6 +38,31 @@ properties:
clocks:
items:
- description: MERGE Clock
+ - description: MERGE Async Clock
+ Controlling the synchronous process between MERGE and other display function
+ blocks cross clock domain.
+
+ mediatek,merge-fifo-en:
+ description:
+ The setting of merge fifo is mainly provided for the display latency buffer.
+ to ensure that the back-end panel display data will not be underrun,
+ a little more data is needed in the fifo. According to the merge fifo settings,
+ when the water level is detected to be insufficient, it will trigger RDMA sending
+ ultra and preulra command to SMI to speed up the data rate.
+ type: boolean
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+ resets:
+ description: reset controller
+ See Documentation/devicetree/bindings/reset/reset.txt for details.
required:
- compatible
@@ -55,3 +82,16 @@ examples:
clocks = <&mmsys CLK_MM_DISP_MERGE>;
};
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+ };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
index aaba6bbfb4da..0dced7a53329 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
@@ -30,6 +30,8 @@ properties:
- const: mediatek,mt8173-disp-mutex
- items:
- const: mediatek,mt8183-disp-mutex
+ - items:
+ - const: mediatek,mt8195-disp-mutex
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index 833b0ca09b21..1973eee4244f 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -31,6 +31,11 @@ properties:
- mediatek,mt2712-disp-ovl
- enum:
- mediatek,mt2701-disp-ovl
+ - items:
+ - enum:
+ - mediatek,mt8195-disp-ovl
+ - enum:
+ - mediatek,mt8183-disp-ovl
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index ce3bcca30609..847bc55252ca 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -27,6 +27,8 @@ properties:
- const: mediatek,mt8173-disp-rdma
- items:
- const: mediatek,mt8183-disp-rdma
+ - items:
+ - const: mediatek,mt8195-disp-rdma
- items:
- enum:
- mediatek,mt7623-disp-rdma
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v8 05/13] arm64: dts: mt8195: add display node for vdosys0
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (3 preceding siblings ...)
2021-08-19 2:23 ` [PATCH v8 04/13] dt-bindings: mediatek: display: add " jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 06/13] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
` (7 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
Add display node for vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is based on [1][2][3]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2]arm64: dts: mt8195: add IOMMU and smi nodes
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3]arm64: dts: mt8195: add gce node
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 +++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 47c44cb77da0..b4558a223b37 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1153,9 +1153,120 @@
#clock-cells = <1>;
};
+ ovl0: disp_ovl@1c000000 {
+ compatible = "mediatek,mt8195-disp-ovl",
+ "mediatek,mt8183-disp-ovl";
+ reg = <0 0x1c000000 0 0x1000>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
+ };
+
+ rdma0: disp_rdma@1c002000 {
+ compatible = "mediatek,mt8195-disp-rdma";
+ reg = <0 0x1c002000 0 0x1000>;
+ interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
+ };
+
+ color0: disp_color@1c003000 {
+ compatible = "mediatek,mt8195-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1c003000 0 0x1000>;
+ interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
+ };
+
+ ccorr0: disp_ccorr@1c004000 {
+ compatible = "mediatek,mt8195-disp-ccorr",
+ "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1c004000 0 0x1000>;
+ interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
+ };
+
+ aal0: disp_aal@1c005000 {
+ compatible = "mediatek,mt8195-disp-aal",
+ "mediatek,mt8173-disp-aal";
+ reg = <0 0x1c005000 0 0x1000>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
+ };
+
+ gamma0: disp_gamma@1c006000 {
+ compatible = "mediatek,mt8195-disp-gamma",
+ "mediatek,mt8173-disp-gamma";
+ reg = <0 0x1c006000 0 0x1000>;
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
+ };
+
+ dither0: disp_dither@1c007000 {
+ compatible = "mediatek,mt8195-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1c007000 0 0x1000>;
+ interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
+ };
+
+ dsc0: disp_dsc_wrap@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
+ merge0: disp_vpp_merge0@1c014000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c014000 0 0x1000>;
+ interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
+ };
+
+ mutex: disp_mutex0@1c016000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c016000 0 0x1000>;
+ reg-names = "vdo0_mutex";
+ interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+ clock-names = "vdo0_mutex";
+ mediatek,gce-events =
+ <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+ };
+
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-vdosys0", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
+ mboxes = <&gce1 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
};
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v8 06/13] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (4 preceding siblings ...)
2021-08-19 2:23 ` [PATCH v8 05/13] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 07/13] soc: mediatek: add mtk-mutex " jason-jh.lin
` (6 subsequent siblings)
12 siblings, 0 replies; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1][2]
[1] soc: mediatek: mmsys: add MT8365 support
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210519161847.3747352-3-fparent@baylibre.com/
[2] soc: mmsys: mediatek: add mask to mmsys routes
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210729070549.5514-1-linux@fw-web.de/
The vdosys1 impelmentation patch [3] will base on this patch
[3] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210722094551.15255-8-nancy.lin@mediatek.com/
---
drivers/soc/mediatek/mt8195-mmsys.h | 114 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 11 +++
include/linux/soc/mediatek/mtk-mmsys.h | 9 ++
3 files changed, 134 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..0c97a5f016c1
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN 0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
+
+#define MT8195_VDO0_SEL_IN 0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE (1 << 22)
+
+#define MT8195_VDO0_SEL_OUT 0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0 (1 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT,
+ MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE,
+ MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0,
+ MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT,
+ MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0,
+ MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN,
+ MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSI0,
+ MT8195_SOUT_DISP_DITHER0_TO_DSI0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0,
+ MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index a78e88f27b62..ce6cc2f49e7d 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -14,6 +14,7 @@
#include "mt8167-mmsys.h"
#include "mt8183-mmsys.h"
#include "mt8365-mmsys.h"
+#include "mt8195-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
@@ -59,6 +60,12 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .clk_driver = "clk-mt8195-vdo0",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -171,6 +178,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..6d6ece48b61e 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,13 +17,22 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
DDP_COMPONENT_DSI3,
DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_MERGE1,
+ DDP_COMPONENT_MERGE2,
+ DDP_COMPONENT_MERGE3,
+ DDP_COMPONENT_MERGE4,
+ DDP_COMPONENT_MERGE5,
DDP_COMPONENT_OD0,
DDP_COMPONENT_OD1,
DDP_COMPONENT_OVL0,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v8 07/13] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (5 preceding siblings ...)
2021-08-19 2:23 ` [PATCH v8 06/13] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-19 15:12 ` Chun-Kuang Hu
2021-08-19 2:23 ` [PATCH v8 08/13] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c jason-jh.lin
` (5 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 98 +++++++++++++++++++++++++++++++-
1 file changed, 95 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..c177156ee2fa 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
#define MT8183_MUTEX0_MOD0 0x30
#define MT8183_MUTEX0_SOF0 0x2c
+#define MT8195_DISP_MUTEX0_MOD0 0x30
+#define MT8195_DISP_MUTEX0_SOF 0x2c
+
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
@@ -67,6 +70,36 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT8195_MUTEX_MOD_DISP_OVL0 0
+#define MT8195_MUTEX_MOD_DISP_WDMA0 1
+#define MT8195_MUTEX_MOD_DISP_RDMA0 2
+#define MT8195_MUTEX_MOD_DISP_COLOR0 3
+#define MT8195_MUTEX_MOD_DISP_CCORR0 4
+#define MT8195_MUTEX_MOD_DISP_AAL0 5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
+#define MT8195_MUTEX_MOD_DISP_DITHER0 7
+#define MT8195_MUTEX_MOD_DISP_DSI0 8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
+#define MT8195_MUTEX_MOD_DISP_OVL1 10
+#define MT8195_MUTEX_MOD_DISP_WDMA1 11
+#define MT8195_MUTEX_MOD_DISP_RDMA1 12
+#define MT8195_MUTEX_MOD_DISP_COLOR1 13
+#define MT8195_MUTEX_MOD_DISP_CCORR1 14
+#define MT8195_MUTEX_MOD_DISP_AAL1 15
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
+#define MT8195_MUTEX_MOD_DISP_DITHER1 17
+#define MT8195_MUTEX_MOD_DISP_DSI1 18
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
+#define MT8195_MUTEX_MOD_DISP_PWM0 27
+#define MT8195_MUTEX_MOD_DISP_PWM1 28
+
#define MT2712_MUTEX_MOD_DISP_PWM2 10
#define MT2712_MUTEX_MOD_DISP_OVL0 11
#define MT2712_MUTEX_MOD_DISP_OVL1 12
@@ -101,12 +134,27 @@
#define MT2712_MUTEX_SOF_DSI3 6
#define MT8167_MUTEX_SOF_DPI0 2
#define MT8167_MUTEX_SOF_DPI1 3
+
#define MT8183_MUTEX_SOF_DSI0 1
#define MT8183_MUTEX_SOF_DPI0 2
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_SOF_DSI0 1
+#define MT8195_MUTEX_SOF_DSI1 2
+#define MT8195_MUTEX_SOF_DP_INTF0 3
+#define MT8195_MUTEX_SOF_DP_INTF1 4
+#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
+
+#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
+
struct mtk_mutex {
int id;
bool claimed;
@@ -120,6 +168,9 @@ enum mtk_mutex_sof_id {
MUTEX_SOF_DPI1,
MUTEX_SOF_DSI2,
MUTEX_SOF_DSI3,
+ MUTEX_SOF_DP_INTF0,
+ MUTEX_SOF_DP_INTF1,
+ DDP_MUTEX_SOF_MAX,
};
struct mtk_mutex_data {
@@ -214,7 +265,23 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+ [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+ [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+ [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -224,7 +291,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -232,12 +299,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
};
/* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
};
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+ [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+ [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+ [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+ [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+ [MUTEX_SOF_DP_INTF0] =
+ MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+ [MUTEX_SOF_DP_INTF1] =
+ MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -275,6 +354,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.no_clk = true,
};
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+ .mutex_mod = mt8195_mutex_mod,
+ .mutex_sof = mt8195_mutex_sof,
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
struct mtk_mutex *mtk_mutex_get(struct device *dev)
{
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -347,6 +433,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF0:
+ sof_id = MUTEX_SOF_DP_INTF0;
+ break;
default:
if (mtx->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -386,6 +475,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF0:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -507,6 +597,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8173_mutex_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = &mt8183_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = &mt8195_mutex_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v8 07/13] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2021-08-19 2:23 ` [PATCH v8 07/13] soc: mediatek: add mtk-mutex " jason-jh.lin
@ 2021-08-19 15:12 ` Chun-Kuang Hu
2021-08-24 17:47 ` Jason-JH Lin
0 siblings, 1 reply; 28+ messages in thread
From: Chun-Kuang Hu @ 2021-08-19 15:12 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao,
Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, Hsin-Yi Wang, Yongqiang Niu,
Jitao shi, Nancy Lin, singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道：
>
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 98 +++++++++++++++++++++++++++++++-
> 1 file changed, 95 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2e4bcc300576..c177156ee2fa 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
> #define MT8183_MUTEX0_MOD0 0x30
> #define MT8183_MUTEX0_SOF0 0x2c
>
> +#define MT8195_DISP_MUTEX0_MOD0 0x30
> +#define MT8195_DISP_MUTEX0_SOF 0x2c
> +
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> @@ -67,6 +70,36 @@
> #define MT8173_MUTEX_MOD_DISP_PWM1 24
> #define MT8173_MUTEX_MOD_DISP_OD 25
>
> +#define MT8195_MUTEX_MOD_DISP_OVL0 0
> +#define MT8195_MUTEX_MOD_DISP_WDMA0 1
> +#define MT8195_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8195_MUTEX_MOD_DISP_COLOR0 3
> +#define MT8195_MUTEX_MOD_DISP_CCORR0 4
> +#define MT8195_MUTEX_MOD_DISP_AAL0 5
> +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
> +#define MT8195_MUTEX_MOD_DISP_DITHER0 7
> +#define MT8195_MUTEX_MOD_DISP_DSI0 8
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
> +#define MT8195_MUTEX_MOD_DISP_OVL1 10
> +#define MT8195_MUTEX_MOD_DISP_WDMA1 11
> +#define MT8195_MUTEX_MOD_DISP_RDMA1 12
> +#define MT8195_MUTEX_MOD_DISP_COLOR1 13
> +#define MT8195_MUTEX_MOD_DISP_CCORR1 14
> +#define MT8195_MUTEX_MOD_DISP_AAL1 15
> +#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
> +#define MT8195_MUTEX_MOD_DISP_DITHER1 17
> +#define MT8195_MUTEX_MOD_DISP_DSI1 18
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
> +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
> +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
> +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
> +#define MT8195_MUTEX_MOD_DISP_PWM0 27
> +#define MT8195_MUTEX_MOD_DISP_PWM1 28
> +
> #define MT2712_MUTEX_MOD_DISP_PWM2 10
> #define MT2712_MUTEX_MOD_DISP_OVL0 11
> #define MT2712_MUTEX_MOD_DISP_OVL1 12
> @@ -101,12 +134,27 @@
> #define MT2712_MUTEX_SOF_DSI3 6
> #define MT8167_MUTEX_SOF_DPI0 2
> #define MT8167_MUTEX_SOF_DPI1 3
> +
> #define MT8183_MUTEX_SOF_DSI0 1
> #define MT8183_MUTEX_SOF_DPI0 2
>
> #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
>
> +#define MT8195_MUTEX_SOF_DSI0 1
> +#define MT8195_MUTEX_SOF_DSI1 2
> +#define MT8195_MUTEX_SOF_DP_INTF0 3
> +#define MT8195_MUTEX_SOF_DP_INTF1 4
> +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
> +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
> +
> +#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
> +#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
> +#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
> +#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
> +
> struct mtk_mutex {
> int id;
> bool claimed;
> @@ -120,6 +168,9 @@ enum mtk_mutex_sof_id {
> MUTEX_SOF_DPI1,
> MUTEX_SOF_DSI2,
> MUTEX_SOF_DSI3,
> + MUTEX_SOF_DP_INTF0,
> + MUTEX_SOF_DP_INTF1,
> + DDP_MUTEX_SOF_MAX,
> };
>
> struct mtk_mutex_data {
> @@ -214,7 +265,23 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> };
>
> -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
> + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> + [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> + [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
> +};
> +
> +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
> @@ -224,7 +291,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> };
>
> -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> @@ -232,12 +299,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> };
>
> /* Add EOF setting so overlay hardware can receive frame done irq */
> -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> };
>
> +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
> + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
> + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
> + [MUTEX_SOF_DP_INTF0] =
> + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
> + [MUTEX_SOF_DP_INTF1] =
> + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
Why do you or EOF?
Regards,
Chun-Kuang.
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -275,6 +354,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> .no_clk = true,
> };
>
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> + .mutex_mod = mt8195_mutex_mod,
> + .mutex_sof = mt8195_mutex_sof,
> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -347,6 +433,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DPI1:
> sof_id = MUTEX_SOF_DPI1;
> break;
> + case DDP_COMPONENT_DP_INTF0:
> + sof_id = MUTEX_SOF_DP_INTF0;
> + break;
How about MUTEX_SOF_DP_INTF1?
> default:
> if (mtx->data->mutex_mod[id] < 32) {
> offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> @@ -386,6 +475,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DSI3:
> case DDP_COMPONENT_DPI0:
> case DDP_COMPONENT_DPI1:
> + case DDP_COMPONENT_DP_INTF0:
Ditto.
Regards,
Chun-Kuang.
> writel_relaxed(MUTEX_SOF_SINGLE_MODE,
> mtx->regs +
> DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
> @@ -507,6 +597,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8173_mutex_driver_data},
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = &mt8183_mutex_driver_data},
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = &mt8195_mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
> --
> 2.18.0
>
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v8 07/13] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2021-08-19 15:12 ` Chun-Kuang Hu
@ 2021-08-24 17:47 ` Jason-JH Lin
0 siblings, 0 replies; 28+ messages in thread
From: Jason-JH Lin @ 2021-08-24 17:47 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, fshao, Philipp Zabel,
Enric Balletbo i Serra, David Airlie, Daniel Vetter,
Fabien Parent, Hsin-Yi Wang, Yongqiang Niu, Jitao shi, Nancy Lin,
singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi Chun-Kuang,
Thanks for the review.
On Thu, 2021-08-19 at 23:12 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道：
> >
> > Add mtk-mutex support for mt8195 vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 98
> > +++++++++++++++++++++++++++++++-
> > 1 file changed, 95 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index 2e4bcc300576..c177156ee2fa 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -17,6 +17,9 @@
> > #define MT8183_MUTEX0_MOD0 0x30
> > #define MT8183_MUTEX0_SOF0 0x2c
> >
> > +#define MT8195_DISP_MUTEX0_MOD0 0x30
> > +#define MT8195_DISP_MUTEX0_SOF 0x2c
> > +
> > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> > @@ -67,6 +70,36 @@
> > #define MT8173_MUTEX_MOD_DISP_PWM1 24
> > #define MT8173_MUTEX_MOD_DISP_OD 25
> >
> > +#define MT8195_MUTEX_MOD_DISP_OVL0 0
> > +#define MT8195_MUTEX_MOD_DISP_WDMA0 1
> > +#define MT8195_MUTEX_MOD_DISP_RDMA0 2
> > +#define MT8195_MUTEX_MOD_DISP_COLOR0 3
> > +#define MT8195_MUTEX_MOD_DISP_CCORR0 4
> > +#define MT8195_MUTEX_MOD_DISP_AAL0 5
> > +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
> > +#define MT8195_MUTEX_MOD_DISP_DITHER0 7
> > +#define MT8195_MUTEX_MOD_DISP_DSI0 8
> > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
> > +#define MT8195_MUTEX_MOD_DISP_OVL1 10
> > +#define MT8195_MUTEX_MOD_DISP_WDMA1 11
> > +#define MT8195_MUTEX_MOD_DISP_RDMA1 12
> > +#define MT8195_MUTEX_MOD_DISP_COLOR1 13
> > +#define MT8195_MUTEX_MOD_DISP_CCORR1 14
> > +#define MT8195_MUTEX_MOD_DISP_AAL1 15
> > +#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
> > +#define MT8195_MUTEX_MOD_DISP_DITHER1 17
> > +#define MT8195_MUTEX_MOD_DISP_DSI1 18
> > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
> > +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
> > +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
> > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
> > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
> > +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
> > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
> > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
> > +#define MT8195_MUTEX_MOD_DISP_PWM0 27
> > +#define MT8195_MUTEX_MOD_DISP_PWM1 28
> > +
> > #define MT2712_MUTEX_MOD_DISP_PWM2 10
> > #define MT2712_MUTEX_MOD_DISP_OVL0 11
> > #define MT2712_MUTEX_MOD_DISP_OVL1 12
> > @@ -101,12 +134,27 @@
> > #define MT2712_MUTEX_SOF_DSI3 6
> > #define MT8167_MUTEX_SOF_DPI0 2
> > #define MT8167_MUTEX_SOF_DPI1 3
> > +
> > #define MT8183_MUTEX_SOF_DSI0 1
> > #define MT8183_MUTEX_SOF_DPI0 2
> >
> > #define
> > MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> > #define
> > MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
> >
> > +#define MT8195_MUTEX_SOF_DSI0 1
> > +#define MT8195_MUTEX_SOF_DSI1 2
> > +#define MT8195_MUTEX_SOF_DP_INTF0 3
> > +#define MT8195_MUTEX_SOF_DP_INTF1 4
> > +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
> > +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital
> > video out */
> > +
> > +#define
> > MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
> > +#define
> > MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
> > +#define
> > MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0
> > << 7)
> > +#define
> > MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1
> > << 7)
> > +#define
> > MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
> > +#define
> > MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
> > +
> > struct mtk_mutex {
> > int id;
> > bool claimed;
> > @@ -120,6 +168,9 @@ enum mtk_mutex_sof_id {
> > MUTEX_SOF_DPI1,
> > MUTEX_SOF_DSI2,
> > MUTEX_SOF_DSI3,
> > + MUTEX_SOF_DP_INTF0,
> > + MUTEX_SOF_DP_INTF1,
> > + DDP_MUTEX_SOF_MAX,
> > };
> >
> > struct mtk_mutex_data {
> > @@ -214,7 +265,23 @@ static const unsigned int
> > mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> > };
> >
> > -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] =
> > {
> > + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
> > + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
> > + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
> > + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
> > + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> > + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> > + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> > + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> > + [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> > + [DDP_COMPONENT_DSC0] =
> > MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> > + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> > + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> > + [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
> > +};
> > +
> > +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> > [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
> > @@ -224,7 +291,7 @@ static const unsigned int
> > mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> > };
> >
> > -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> > [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> > @@ -232,12 +299,24 @@ static const unsigned int
> > mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > };
> >
> > /* Add EOF setting so overlay hardware can receive frame done irq
> > */
> > -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> > [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 |
> > MT8183_MUTEX_EOF_DPI0,
> > };
> >
> > +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 |
> > MT8195_MUTEX_EOF_DSI0,
> > + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 |
> > MT8195_MUTEX_EOF_DSI1,
> > + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 |
> > MT8195_MUTEX_EOF_DPI0,
> > + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 |
> > MT8195_MUTEX_EOF_DPI1,
> > + [MUTEX_SOF_DP_INTF0] =
> > + MT8195_MUTEX_SOF_DP_INTF0 |
> > MT8195_MUTEX_EOF_DP_INTF0,
> > + [MUTEX_SOF_DP_INTF1] =
> > + MT8195_MUTEX_SOF_DP_INTF1 |
> > MT8195_MUTEX_EOF_DP_INTF1,
>
> Why do you or EOF?
>
> Regards,
> Chun-Kuang.
>
The value of mt8195_mutex_sof will be set into this register,
#define MT8195_DISP_MUTEX0_SOF 0x2c
which is providing the source module selection of SOF(Start of Frame)
and EOF(End of Frame) in current stream(MUTEX).
MUTEX will send the EOF trigger signal to all sourcesub-module whose
EOF is selected in this register.
So I think we should or EOF to make sure sub-module cloud get both SOF
and EOF trigger signal for status checking, error handling or
debugging.
> > +};
> > +
> > static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> > .mutex_mod = mt2701_mutex_mod,
> > .mutex_sof = mt2712_mutex_sof,
> > @@ -275,6 +354,13 @@ static const struct mtk_mutex_data
> > mt8183_mutex_driver_data = {
> > .no_clk = true,
> > };
> >
> > +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> > + .mutex_mod = mt8195_mutex_mod,
> > + .mutex_sof = mt8195_mutex_sof,
> > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > +};
> > +
> > struct mtk_mutex *mtk_mutex_get(struct device *dev)
> > {
> > struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> > @@ -347,6 +433,9 @@ void mtk_mutex_add_comp(struct mtk_mutex
> > *mutex,
> > case DDP_COMPONENT_DPI1:
> > sof_id = MUTEX_SOF_DPI1;
> > break;
> > + case DDP_COMPONENT_DP_INTF0:
> > + sof_id = MUTEX_SOF_DP_INTF0;
> > + break;
>
> How about MUTEX_SOF_DP_INTF1?
MUTEX_SOF_DP_INTF1 won't use in vdosys0, so it will be added at the
patch [1] in vdosys1 series.
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210818091847.8060-12-nancy.lin@mediatek.com/
>
> > default:
> > if (mtx->data->mutex_mod[id] < 32) {
> > offset = DISP_REG_MUTEX_MOD(mtx->data-
> > >mutex_mod_reg,
> > @@ -386,6 +475,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex
> > *mutex,
> > case DDP_COMPONENT_DSI3:
> > case DDP_COMPONENT_DPI0:
> > case DDP_COMPONENT_DPI1:
> > + case DDP_COMPONENT_DP_INTF0:
>
> Ditto.
>
> Regards,
> Chun-Kuang.
>
Ditto.
Regards,
Jason-JH.Lin
> > writel_relaxed(MUTEX_SOF_SINGLE_MODE,
> > mtx->regs +
> > DISP_REG_MUTEX_SOF(mtx->data-
> > >mutex_sof_reg,
> > @@ -507,6 +597,8 @@ static const struct of_device_id
> > mutex_driver_dt_match[] = {
> > .data = &mt8173_mutex_driver_data},
> > { .compatible = "mediatek,mt8183-disp-mutex",
> > .data = &mt8183_mutex_driver_data},
> > + { .compatible = "mediatek,mt8195-disp-mutex",
> > + .data = &mt8195_mutex_driver_data},
> > {},
> > };
> > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
> > --
> > 2.18.0
> >
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v8 08/13] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (6 preceding siblings ...)
2021-08-19 2:23 ` [PATCH v8 07/13] soc: mediatek: add mtk-mutex " jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-19 15:14 ` Chun-Kuang Hu
2021-08-19 2:23 ` [PATCH v8 09/13] drm/mediatek: rename the define of register offset jason-jh.lin
` (4 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
Remove the unsed define in mtk_drm_ddp_comp.c
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e17fc4..aaa7450b3e2b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -21,8 +21,6 @@
#include "mtk_drm_crtc.h"
#define DISP_OD_EN 0x0000
-#define DISP_OD_INTEN 0x0008
-#define DISP_OD_INTSTA 0x000c
#define DISP_OD_CFG 0x0020
#define DISP_OD_SIZE 0x0030
#define DISP_DITHER_5 0x0114
@@ -42,8 +40,6 @@
#define DITHER_ENGINE_EN BIT(1)
#define DISP_DITHER_SIZE 0x0030
-#define LUT_10BIT_MASK 0x03ff
-
#define OD_RELAYMODE BIT(0)
#define UFO_BYPASS BIT(2)
@@ -52,18 +48,12 @@
#define DISP_DITHERING BIT(2)
#define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
-#define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24)
#define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
-#define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16)
#define DITHER_NEW_BIT_MODE BIT(0)
#define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
-#define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24)
#define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
-#define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16)
#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
-#define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8)
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
-#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
struct mtk_ddp_comp_dev {
struct clk *clk;
--
2.18.0
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v8 08/13] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c
2021-08-19 2:23 ` [PATCH v8 08/13] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c jason-jh.lin
@ 2021-08-19 15:14 ` Chun-Kuang Hu
0 siblings, 0 replies; 28+ messages in thread
From: Chun-Kuang Hu @ 2021-08-19 15:14 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao,
Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, Hsin-Yi Wang, Yongqiang Niu,
Jitao shi, Nancy Lin, singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道：
>
> Remove the unsed define in mtk_drm_ddp_comp.c
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 75bc00e17fc4..aaa7450b3e2b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -21,8 +21,6 @@
> #include "mtk_drm_crtc.h"
>
> #define DISP_OD_EN 0x0000
> -#define DISP_OD_INTEN 0x0008
> -#define DISP_OD_INTSTA 0x000c
> #define DISP_OD_CFG 0x0020
> #define DISP_OD_SIZE 0x0030
> #define DISP_DITHER_5 0x0114
> @@ -42,8 +40,6 @@
> #define DITHER_ENGINE_EN BIT(1)
> #define DISP_DITHER_SIZE 0x0030
>
> -#define LUT_10BIT_MASK 0x03ff
> -
> #define OD_RELAYMODE BIT(0)
>
> #define UFO_BYPASS BIT(2)
> @@ -52,18 +48,12 @@
>
> #define DISP_DITHERING BIT(2)
> #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
> -#define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24)
> #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
> -#define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16)
> #define DITHER_NEW_BIT_MODE BIT(0)
> #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
> -#define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24)
> #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
> -#define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16)
> #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
> -#define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8)
> #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
> -#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
>
> struct mtk_ddp_comp_dev {
> struct clk *clk;
> --
> 2.18.0
>
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v8 09/13] drm/mediatek: rename the define of register offset
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (7 preceding siblings ...)
2021-08-19 2:23 ` [PATCH v8 08/13] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-19 15:17 ` Chun-Kuang Hu
2021-08-19 2:23 ` [PATCH v8 10/13] drm/mediatek: adjust to the alphabetic order for mediatek-drm jason-jh.lin
` (3 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
Add DISP_REG prefix for the define of register offset to
make the difference from the define of register value.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 57 +++++++++++----------
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index aaa7450b3e2b..93beb980414f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -20,25 +20,25 @@
#include "mtk_drm_ddp_comp.h"
#include "mtk_drm_crtc.h"
-#define DISP_OD_EN 0x0000
-#define DISP_OD_CFG 0x0020
-#define DISP_OD_SIZE 0x0030
-#define DISP_DITHER_5 0x0114
-#define DISP_DITHER_7 0x011c
-#define DISP_DITHER_15 0x013c
-#define DISP_DITHER_16 0x0140
+#define DISP_REG_OD_EN 0x0000
+#define DISP_REG_OD_CFG 0x0020
+#define DISP_REG_OD_SIZE 0x0030
+#define DISP_REG_DITHER_5 0x0114
+#define DISP_REG_DITHER_7 0x011c
+#define DISP_REG_DITHER_15 0x013c
+#define DISP_REG_DITHER_16 0x0140
#define DISP_REG_UFO_START 0x0000
-#define DISP_AAL_EN 0x0000
-#define DISP_AAL_SIZE 0x0030
+#define DISP_REG_AAL_EN 0x0000
+#define DISP_REG_AAL_SIZE 0x0030
-#define DISP_DITHER_EN 0x0000
+#define DISP_REG_DITHER_EN 0x0000
#define DITHER_EN BIT(0)
-#define DISP_DITHER_CFG 0x0020
+#define DISP_REG_DITHER_CFG 0x0020
#define DITHER_RELAY_MODE BIT(0)
#define DITHER_ENGINE_EN BIT(1)
-#define DISP_DITHER_SIZE 0x0030
+#define DISP_REG_DITHER_SIZE 0x0030
#define OD_RELAYMODE BIT(0)
@@ -129,19 +129,19 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
return;
if (bpc >= MTK_MIN_BPC) {
- mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
- mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
+ mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
+ mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
mtk_ddp_write(cmdq_pkt,
DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
DITHER_NEW_BIT_MODE,
- cmdq_reg, regs, DISP_DITHER_15);
+ cmdq_reg, regs, DISP_REG_DITHER_15);
mtk_ddp_write(cmdq_pkt,
DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
- cmdq_reg, regs, DISP_DITHER_16);
+ cmdq_reg, regs, DISP_REG_DITHER_16);
mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
}
}
@@ -161,16 +161,16 @@ static void mtk_od_config(struct device *dev, unsigned int w,
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
- mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
- mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
+ mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
+ mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
}
static void mtk_od_start(struct device *dev)
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- writel(1, priv->regs + DISP_OD_EN);
+ writel(1, priv->regs + DISP_REG_OD_EN);
}
static void mtk_ufoe_start(struct device *dev)
@@ -186,7 +186,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w,
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_AAL_SIZE);
}
static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
@@ -200,14 +200,14 @@ static void mtk_aal_start(struct device *dev)
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- writel(AAL_EN, priv->regs + DISP_AAL_EN);
+ writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
}
static void mtk_aal_stop(struct device *dev)
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
+ writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
}
static void mtk_dither_config(struct device *dev, unsigned int w,
@@ -216,9 +216,10 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
- mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
- mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
+ mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DITHER_CFG);
+ mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
DITHER_ENGINE_EN, cmdq_pkt);
}
@@ -226,14 +227,14 @@ static void mtk_dither_start(struct device *dev)
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
+ writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
}
static void mtk_dither_stop(struct device *dev)
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
+ writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
}
static const struct mtk_ddp_comp_funcs ddp_aal = {
--
2.18.0
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^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v8 09/13] drm/mediatek: rename the define of register offset
2021-08-19 2:23 ` [PATCH v8 09/13] drm/mediatek: rename the define of register offset jason-jh.lin
@ 2021-08-19 15:17 ` Chun-Kuang Hu
0 siblings, 0 replies; 28+ messages in thread
From: Chun-Kuang Hu @ 2021-08-19 15:17 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao,
Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, Hsin-Yi Wang, Yongqiang Niu,
Jitao shi, Nancy Lin, singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道：
>
> Add DISP_REG prefix for the define of register offset to
> make the difference from the define of register value.
>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 57 +++++++++++----------
> 1 file changed, 29 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index aaa7450b3e2b..93beb980414f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -20,25 +20,25 @@
> #include "mtk_drm_ddp_comp.h"
> #include "mtk_drm_crtc.h"
>
> -#define DISP_OD_EN 0x0000
> -#define DISP_OD_CFG 0x0020
> -#define DISP_OD_SIZE 0x0030
> -#define DISP_DITHER_5 0x0114
> -#define DISP_DITHER_7 0x011c
> -#define DISP_DITHER_15 0x013c
> -#define DISP_DITHER_16 0x0140
> +#define DISP_REG_OD_EN 0x0000
> +#define DISP_REG_OD_CFG 0x0020
> +#define DISP_REG_OD_SIZE 0x0030
> +#define DISP_REG_DITHER_5 0x0114
> +#define DISP_REG_DITHER_7 0x011c
> +#define DISP_REG_DITHER_15 0x013c
> +#define DISP_REG_DITHER_16 0x0140
>
> #define DISP_REG_UFO_START 0x0000
>
> -#define DISP_AAL_EN 0x0000
> -#define DISP_AAL_SIZE 0x0030
> +#define DISP_REG_AAL_EN 0x0000
> +#define DISP_REG_AAL_SIZE 0x0030
>
> -#define DISP_DITHER_EN 0x0000
> +#define DISP_REG_DITHER_EN 0x0000
> #define DITHER_EN BIT(0)
> -#define DISP_DITHER_CFG 0x0020
> +#define DISP_REG_DITHER_CFG 0x0020
> #define DITHER_RELAY_MODE BIT(0)
> #define DITHER_ENGINE_EN BIT(1)
> -#define DISP_DITHER_SIZE 0x0030
> +#define DISP_REG_DITHER_SIZE 0x0030
>
> #define OD_RELAYMODE BIT(0)
>
> @@ -129,19 +129,19 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
> return;
>
> if (bpc >= MTK_MIN_BPC) {
> - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_NEW_BIT_MODE,
> - cmdq_reg, regs, DISP_DITHER_15);
> + cmdq_reg, regs, DISP_REG_DITHER_15);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> - cmdq_reg, regs, DISP_DITHER_16);
> + cmdq_reg, regs, DISP_REG_DITHER_16);
> mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
> }
> }
> @@ -161,16 +161,16 @@ static void mtk_od_config(struct device *dev, unsigned int w,
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
> - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
> - mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
> + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
> + mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> }
>
> static void mtk_od_start(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel(1, priv->regs + DISP_OD_EN);
> + writel(1, priv->regs + DISP_REG_OD_EN);
> }
>
> static void mtk_ufoe_start(struct device *dev)
> @@ -186,7 +186,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w,
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_AAL_SIZE);
> }
>
> static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> @@ -200,14 +200,14 @@ static void mtk_aal_start(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel(AAL_EN, priv->regs + DISP_AAL_EN);
> + writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
> }
>
> static void mtk_aal_stop(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
> + writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
> }
>
> static void mtk_dither_config(struct device *dev, unsigned int w,
> @@ -216,9 +216,10 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
> - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> - mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
> + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
> + DISP_REG_DITHER_CFG);
> + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
> DITHER_ENGINE_EN, cmdq_pkt);
> }
>
> @@ -226,14 +227,14 @@ static void mtk_dither_start(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
> + writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
> }
>
> static void mtk_dither_stop(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
> + writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> }
>
> static const struct mtk_ddp_comp_funcs ddp_aal = {
> --
> 2.18.0
>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v8 10/13] drm/mediatek: adjust to the alphabetic order for mediatek-drm
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (8 preceding siblings ...)
2021-08-19 2:23 ` [PATCH v8 09/13] drm/mediatek: rename the define of register offset jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-19 23:14 ` Chun-Kuang Hu
2021-08-19 2:23 ` [PATCH v8 11/13] drm/mediatek: add DSC support " jason-jh.lin
` (2 subsequent siblings)
12 siblings, 1 reply; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
Adjust to the alphabetic order for the define, function, struct
and array in mediatek-drm driver
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 133 ++++++++++----------
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 22 ++--
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 76 +++++------
3 files changed, 115 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 93beb980414f..28bc42fd0b8a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -20,17 +20,9 @@
#include "mtk_drm_ddp_comp.h"
#include "mtk_drm_crtc.h"
-#define DISP_REG_OD_EN 0x0000
-#define DISP_REG_OD_CFG 0x0020
-#define DISP_REG_OD_SIZE 0x0030
-#define DISP_REG_DITHER_5 0x0114
-#define DISP_REG_DITHER_7 0x011c
-#define DISP_REG_DITHER_15 0x013c
-#define DISP_REG_DITHER_16 0x0140
-
-#define DISP_REG_UFO_START 0x0000
#define DISP_REG_AAL_EN 0x0000
+#define AAL_EN BIT(0)
#define DISP_REG_AAL_SIZE 0x0030
#define DISP_REG_DITHER_EN 0x0000
@@ -38,23 +30,29 @@
#define DISP_REG_DITHER_CFG 0x0020
#define DITHER_RELAY_MODE BIT(0)
#define DITHER_ENGINE_EN BIT(1)
-#define DISP_REG_DITHER_SIZE 0x0030
-
-#define OD_RELAYMODE BIT(0)
-
-#define UFO_BYPASS BIT(2)
-
-#define AAL_EN BIT(0)
#define DISP_DITHERING BIT(2)
+#define DISP_REG_DITHER_SIZE 0x0030
+#define DISP_REG_DITHER_5 0x0114
+#define DISP_REG_DITHER_7 0x011c
+#define DISP_REG_DITHER_15 0x013c
#define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
#define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
#define DITHER_NEW_BIT_MODE BIT(0)
+#define DISP_REG_DITHER_16 0x0140
#define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
#define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
+#define DISP_REG_OD_EN 0x0000
+#define DISP_REG_OD_CFG 0x0020
+#define OD_RELAYMODE BIT(0)
+#define DISP_REG_OD_SIZE 0x0030
+
+#define DISP_REG_UFO_START 0x0000
+#define UFO_BYPASS BIT(2)
+
struct mtk_ddp_comp_dev {
struct clk *clk;
void __iomem *regs;
@@ -106,20 +104,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
#endif
}
-static int mtk_ddp_clk_enable(struct device *dev)
-{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
- return clk_prepare_enable(priv->clk);
-}
-
-static void mtk_ddp_clk_disable(struct device *dev)
-{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
- clk_disable_unprepare(priv->clk);
-}
-
void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
unsigned int bpc, unsigned int cfg,
unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
@@ -146,38 +130,19 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
}
}
-static void mtk_dither_set(struct device *dev, unsigned int bpc,
- unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
-{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
- mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
- DISP_DITHERING, cmdq_pkt);
-}
-
-static void mtk_od_config(struct device *dev, unsigned int w,
- unsigned int h, unsigned int vrefresh,
- unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
-{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
- mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
- mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
- mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
-}
-static void mtk_od_start(struct device *dev)
+static int mtk_ddp_clk_enable(struct device *dev)
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- writel(1, priv->regs + DISP_REG_OD_EN);
+ return clk_prepare_enable(priv->clk);
}
-static void mtk_ufoe_start(struct device *dev)
+static void mtk_ddp_clk_disable(struct device *dev)
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
+ clk_disable_unprepare(priv->clk);
}
static void mtk_aal_config(struct device *dev, unsigned int w,
@@ -237,6 +202,40 @@ static void mtk_dither_stop(struct device *dev)
writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
}
+static void mtk_dither_set(struct device *dev, unsigned int bpc,
+ unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
+ DISP_DITHERING, cmdq_pkt);
+}
+
+static void mtk_od_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
+ mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
+ mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
+}
+
+static void mtk_od_start(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel(1, priv->regs + DISP_REG_OD_EN);
+}
+
+static void mtk_ufoe_start(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
+}
+
static const struct mtk_ddp_comp_funcs ddp_aal = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -331,22 +330,22 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
};
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
+ [MTK_DISP_AAL] = "aal",
+ [MTK_DISP_BLS] = "bls",
+ [MTK_DISP_CCORR] = "ccorr",
+ [MTK_DISP_COLOR] = "color",
+ [MTK_DISP_DITHER] = "dither",
+ [MTK_DISP_GAMMA] = "gamma",
+ [MTK_DISP_MUTEX] = "mutex",
+ [MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
+ [MTK_DISP_PWM] = "pwm",
[MTK_DISP_RDMA] = "rdma",
- [MTK_DISP_WDMA] = "wdma",
- [MTK_DISP_COLOR] = "color",
- [MTK_DISP_CCORR] = "ccorr",
- [MTK_DISP_AAL] = "aal",
- [MTK_DISP_GAMMA] = "gamma",
- [MTK_DISP_DITHER] = "dither",
[MTK_DISP_UFOE] = "ufoe",
- [MTK_DSI] = "dsi",
+ [MTK_DISP_WDMA] = "wdma",
[MTK_DPI] = "dpi",
- [MTK_DISP_PWM] = "pwm",
- [MTK_DISP_MUTEX] = "mutex",
- [MTK_DISP_OD] = "od",
- [MTK_DISP_BLS] = "bls",
+ [MTK_DSI] = "dsi",
};
struct mtk_ddp_comp_match {
@@ -500,12 +499,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_CCORR ||
type == MTK_DISP_COLOR ||
type == MTK_DISP_GAMMA ||
- type == MTK_DPI ||
- type == MTK_DSI ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
type == MTK_DISP_PWM ||
- type == MTK_DISP_RDMA)
+ type == MTK_DISP_RDMA ||
+ type == MTK_DPI ||
+ type == MTK_DSI)
return 0;
priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index bb914d976cf5..d317b944df66 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -18,22 +18,22 @@ struct mtk_plane_state;
struct drm_crtc_state;
enum mtk_ddp_comp_type {
- MTK_DISP_OVL,
- MTK_DISP_OVL_2L,
- MTK_DISP_RDMA,
- MTK_DISP_WDMA,
- MTK_DISP_COLOR,
+ MTK_DISP_AAL,
+ MTK_DISP_BLS,
MTK_DISP_CCORR,
+ MTK_DISP_COLOR,
MTK_DISP_DITHER,
- MTK_DISP_AAL,
MTK_DISP_GAMMA,
- MTK_DISP_UFOE,
- MTK_DSI,
- MTK_DPI,
- MTK_DISP_PWM,
MTK_DISP_MUTEX,
MTK_DISP_OD,
- MTK_DISP_BLS,
+ MTK_DISP_OVL,
+ MTK_DISP_OVL_2L,
+ MTK_DISP_PWM,
+ MTK_DISP_RDMA,
+ MTK_DISP_UFOE,
+ MTK_DISP_WDMA,
+ MTK_DPI,
+ MTK_DSI,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b46bdb8985da..a95dc1006b82 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -396,50 +396,20 @@ static const struct component_master_ops mtk_drm_ops = {
};
static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
- { .compatible = "mediatek,mt2701-disp-ovl",
- .data = (void *)MTK_DISP_OVL },
- { .compatible = "mediatek,mt8173-disp-ovl",
- .data = (void *)MTK_DISP_OVL },
- { .compatible = "mediatek,mt8183-disp-ovl",
- .data = (void *)MTK_DISP_OVL },
- { .compatible = "mediatek,mt8183-disp-ovl-2l",
- .data = (void *)MTK_DISP_OVL_2L },
- { .compatible = "mediatek,mt2701-disp-rdma",
- .data = (void *)MTK_DISP_RDMA },
- { .compatible = "mediatek,mt8173-disp-rdma",
- .data = (void *)MTK_DISP_RDMA },
- { .compatible = "mediatek,mt8183-disp-rdma",
- .data = (void *)MTK_DISP_RDMA },
- { .compatible = "mediatek,mt8173-disp-wdma",
- .data = (void *)MTK_DISP_WDMA },
+ { .compatible = "mediatek,mt8173-disp-aal",
+ .data = (void *)MTK_DISP_AAL},
{ .compatible = "mediatek,mt8183-disp-ccorr",
.data = (void *)MTK_DISP_CCORR },
{ .compatible = "mediatek,mt2701-disp-color",
.data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-disp-color",
.data = (void *)MTK_DISP_COLOR },
- { .compatible = "mediatek,mt8173-disp-aal",
- .data = (void *)MTK_DISP_AAL},
+ { .compatible = "mediatek,mt8183-disp-dither",
+ .data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8183-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
- { .compatible = "mediatek,mt8183-disp-dither",
- .data = (void *)MTK_DISP_DITHER },
- { .compatible = "mediatek,mt8173-disp-ufoe",
- .data = (void *)MTK_DISP_UFOE },
- { .compatible = "mediatek,mt2701-dsi",
- .data = (void *)MTK_DSI },
- { .compatible = "mediatek,mt8173-dsi",
- .data = (void *)MTK_DSI },
- { .compatible = "mediatek,mt8183-dsi",
- .data = (void *)MTK_DSI },
- { .compatible = "mediatek,mt2701-dpi",
- .data = (void *)MTK_DPI },
- { .compatible = "mediatek,mt8173-dpi",
- .data = (void *)MTK_DPI },
- { .compatible = "mediatek,mt8183-dpi",
- .data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -448,12 +418,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8173-disp-od",
+ .data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt2701-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8173-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8183-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8183-disp-ovl-2l",
+ .data = (void *)MTK_DISP_OVL_2L },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm",
.data = (void *)MTK_DISP_PWM },
- { .compatible = "mediatek,mt8173-disp-od",
- .data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt2701-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8173-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8183-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8173-disp-ufoe",
+ .data = (void *)MTK_DISP_UFOE },
+ { .compatible = "mediatek,mt8173-disp-wdma",
+ .data = (void *)MTK_DISP_WDMA },
+ { .compatible = "mediatek,mt2701-dpi",
+ .data = (void *)MTK_DPI },
+ { .compatible = "mediatek,mt8173-dpi",
+ .data = (void *)MTK_DPI },
+ { .compatible = "mediatek,mt8183-dpi",
+ .data = (void *)MTK_DPI },
+ { .compatible = "mediatek,mt2701-dsi",
+ .data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8173-dsi",
+ .data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8183-dsi",
+ .data = (void *)MTK_DSI },
{ }
};
@@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_RDMA ||
- comp_type == MTK_DSI ||
- comp_type == MTK_DPI) {
+ comp_type == MTK_DPI ||
+ comp_type == MTK_DSI) {
dev_info(dev, "Adding component match for %pOF\n",
node);
drm_of_component_match_add(dev, &match, compare_of,
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v8 10/13] drm/mediatek: adjust to the alphabetic order for mediatek-drm
2021-08-19 2:23 ` [PATCH v8 10/13] drm/mediatek: adjust to the alphabetic order for mediatek-drm jason-jh.lin
@ 2021-08-19 23:14 ` Chun-Kuang Hu
2021-08-24 17:55 ` Jason-JH Lin
0 siblings, 1 reply; 28+ messages in thread
From: Chun-Kuang Hu @ 2021-08-19 23:14 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao,
Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, Hsin-Yi Wang, Yongqiang Niu,
Jitao shi, Nancy Lin, singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:24寫道：
>
> Adjust to the alphabetic order for the define, function, struct
> and array in mediatek-drm driver
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 133 ++++++++++----------
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 22 ++--
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 76 +++++------
> 3 files changed, 115 insertions(+), 116 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 93beb980414f..28bc42fd0b8a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -20,17 +20,9 @@
> #include "mtk_drm_ddp_comp.h"
> #include "mtk_drm_crtc.h"
>
> -#define DISP_REG_OD_EN 0x0000
> -#define DISP_REG_OD_CFG 0x0020
> -#define DISP_REG_OD_SIZE 0x0030
> -#define DISP_REG_DITHER_5 0x0114
> -#define DISP_REG_DITHER_7 0x011c
> -#define DISP_REG_DITHER_15 0x013c
> -#define DISP_REG_DITHER_16 0x0140
> -
> -#define DISP_REG_UFO_START 0x0000
>
> #define DISP_REG_AAL_EN 0x0000
> +#define AAL_EN BIT(0)
> #define DISP_REG_AAL_SIZE 0x0030
>
> #define DISP_REG_DITHER_EN 0x0000
> @@ -38,23 +30,29 @@
> #define DISP_REG_DITHER_CFG 0x0020
> #define DITHER_RELAY_MODE BIT(0)
> #define DITHER_ENGINE_EN BIT(1)
> -#define DISP_REG_DITHER_SIZE 0x0030
> -
> -#define OD_RELAYMODE BIT(0)
> -
> -#define UFO_BYPASS BIT(2)
> -
> -#define AAL_EN BIT(0)
>
> #define DISP_DITHERING BIT(2)
> +#define DISP_REG_DITHER_SIZE 0x0030
> +#define DISP_REG_DITHER_5 0x0114
> +#define DISP_REG_DITHER_7 0x011c
> +#define DISP_REG_DITHER_15 0x013c
> #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
> #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
> #define DITHER_NEW_BIT_MODE BIT(0)
> +#define DISP_REG_DITHER_16 0x0140
> #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
> #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
> #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
> #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
>
> +#define DISP_REG_OD_EN 0x0000
> +#define DISP_REG_OD_CFG 0x0020
> +#define OD_RELAYMODE BIT(0)
> +#define DISP_REG_OD_SIZE 0x0030
> +
> +#define DISP_REG_UFO_START 0x0000
> +#define UFO_BYPASS BIT(2)
> +
> struct mtk_ddp_comp_dev {
> struct clk *clk;
> void __iomem *regs;
> @@ -106,20 +104,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> #endif
> }
>
> -static int mtk_ddp_clk_enable(struct device *dev)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> - return clk_prepare_enable(priv->clk);
> -}
> -
> -static void mtk_ddp_clk_disable(struct device *dev)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> - clk_disable_unprepare(priv->clk);
> -}
> -
I would like to place the same group together. mtk_ddp_clk_enable()
and mtk_ddp_clk_disable() are common function not belong to any sub
driver. So I would like keep these function here.
Regards,
Chun-Kuang.
> void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
> unsigned int bpc, unsigned int cfg,
> unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
> @@ -146,38 +130,19 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
> }
> }
>
> -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> - unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> - mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
> - DISP_DITHERING, cmdq_pkt);
> -}
> -
> -static void mtk_od_config(struct device *dev, unsigned int w,
> - unsigned int h, unsigned int vrefresh,
> - unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
> - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
> - mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> -}
>
> -static void mtk_od_start(struct device *dev)
> +static int mtk_ddp_clk_enable(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel(1, priv->regs + DISP_REG_OD_EN);
> + return clk_prepare_enable(priv->clk);
> }
>
> -static void mtk_ufoe_start(struct device *dev)
> +static void mtk_ddp_clk_disable(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> - writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> + clk_disable_unprepare(priv->clk);
> }
>
> static void mtk_aal_config(struct device *dev, unsigned int w,
> @@ -237,6 +202,40 @@ static void mtk_dither_stop(struct device *dev)
> writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> }
>
> +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> + unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
> + DISP_DITHERING, cmdq_pkt);
> +}
> +
> +static void mtk_od_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
> + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
> + mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> +}
> +
> +static void mtk_od_start(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel(1, priv->regs + DISP_REG_OD_EN);
> +}
> +
> +static void mtk_ufoe_start(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> +}
> +
> static const struct mtk_ddp_comp_funcs ddp_aal = {
> .clk_enable = mtk_ddp_clk_enable,
> .clk_disable = mtk_ddp_clk_disable,
> @@ -331,22 +330,22 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> };
>
> static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> + [MTK_DISP_AAL] = "aal",
> + [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_CCORR] = "ccorr",
> + [MTK_DISP_COLOR] = "color",
> + [MTK_DISP_DITHER] = "dither",
> + [MTK_DISP_GAMMA] = "gamma",
> + [MTK_DISP_MUTEX] = "mutex",
> + [MTK_DISP_OD] = "od",
> [MTK_DISP_OVL] = "ovl",
> [MTK_DISP_OVL_2L] = "ovl-2l",
> + [MTK_DISP_PWM] = "pwm",
> [MTK_DISP_RDMA] = "rdma",
> - [MTK_DISP_WDMA] = "wdma",
> - [MTK_DISP_COLOR] = "color",
> - [MTK_DISP_CCORR] = "ccorr",
> - [MTK_DISP_AAL] = "aal",
> - [MTK_DISP_GAMMA] = "gamma",
> - [MTK_DISP_DITHER] = "dither",
> [MTK_DISP_UFOE] = "ufoe",
> - [MTK_DSI] = "dsi",
> + [MTK_DISP_WDMA] = "wdma",
> [MTK_DPI] = "dpi",
> - [MTK_DISP_PWM] = "pwm",
> - [MTK_DISP_MUTEX] = "mutex",
> - [MTK_DISP_OD] = "od",
> - [MTK_DISP_BLS] = "bls",
> + [MTK_DSI] = "dsi",
> };
>
> struct mtk_ddp_comp_match {
> @@ -500,12 +499,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> type == MTK_DISP_CCORR ||
> type == MTK_DISP_COLOR ||
> type == MTK_DISP_GAMMA ||
> - type == MTK_DPI ||
> - type == MTK_DSI ||
> type == MTK_DISP_OVL ||
> type == MTK_DISP_OVL_2L ||
> type == MTK_DISP_PWM ||
> - type == MTK_DISP_RDMA)
> + type == MTK_DISP_RDMA ||
> + type == MTK_DPI ||
> + type == MTK_DSI)
> return 0;
>
> priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5..d317b944df66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -18,22 +18,22 @@ struct mtk_plane_state;
> struct drm_crtc_state;
>
> enum mtk_ddp_comp_type {
> - MTK_DISP_OVL,
> - MTK_DISP_OVL_2L,
> - MTK_DISP_RDMA,
> - MTK_DISP_WDMA,
> - MTK_DISP_COLOR,
> + MTK_DISP_AAL,
> + MTK_DISP_BLS,
> MTK_DISP_CCORR,
> + MTK_DISP_COLOR,
> MTK_DISP_DITHER,
> - MTK_DISP_AAL,
> MTK_DISP_GAMMA,
> - MTK_DISP_UFOE,
> - MTK_DSI,
> - MTK_DPI,
> - MTK_DISP_PWM,
> MTK_DISP_MUTEX,
> MTK_DISP_OD,
> - MTK_DISP_BLS,
> + MTK_DISP_OVL,
> + MTK_DISP_OVL_2L,
> + MTK_DISP_PWM,
> + MTK_DISP_RDMA,
> + MTK_DISP_UFOE,
> + MTK_DISP_WDMA,
> + MTK_DPI,
> + MTK_DSI,
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b46bdb8985da..a95dc1006b82 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -396,50 +396,20 @@ static const struct component_master_ops mtk_drm_ops = {
> };
>
> static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> - { .compatible = "mediatek,mt2701-disp-ovl",
> - .data = (void *)MTK_DISP_OVL },
> - { .compatible = "mediatek,mt8173-disp-ovl",
> - .data = (void *)MTK_DISP_OVL },
> - { .compatible = "mediatek,mt8183-disp-ovl",
> - .data = (void *)MTK_DISP_OVL },
> - { .compatible = "mediatek,mt8183-disp-ovl-2l",
> - .data = (void *)MTK_DISP_OVL_2L },
> - { .compatible = "mediatek,mt2701-disp-rdma",
> - .data = (void *)MTK_DISP_RDMA },
> - { .compatible = "mediatek,mt8173-disp-rdma",
> - .data = (void *)MTK_DISP_RDMA },
> - { .compatible = "mediatek,mt8183-disp-rdma",
> - .data = (void *)MTK_DISP_RDMA },
> - { .compatible = "mediatek,mt8173-disp-wdma",
> - .data = (void *)MTK_DISP_WDMA },
> + { .compatible = "mediatek,mt8173-disp-aal",
> + .data = (void *)MTK_DISP_AAL},
> { .compatible = "mediatek,mt8183-disp-ccorr",
> .data = (void *)MTK_DISP_CCORR },
> { .compatible = "mediatek,mt2701-disp-color",
> .data = (void *)MTK_DISP_COLOR },
> { .compatible = "mediatek,mt8173-disp-color",
> .data = (void *)MTK_DISP_COLOR },
> - { .compatible = "mediatek,mt8173-disp-aal",
> - .data = (void *)MTK_DISP_AAL},
> + { .compatible = "mediatek,mt8183-disp-dither",
> + .data = (void *)MTK_DISP_DITHER },
> { .compatible = "mediatek,mt8173-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> { .compatible = "mediatek,mt8183-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> - { .compatible = "mediatek,mt8183-disp-dither",
> - .data = (void *)MTK_DISP_DITHER },
> - { .compatible = "mediatek,mt8173-disp-ufoe",
> - .data = (void *)MTK_DISP_UFOE },
> - { .compatible = "mediatek,mt2701-dsi",
> - .data = (void *)MTK_DSI },
> - { .compatible = "mediatek,mt8173-dsi",
> - .data = (void *)MTK_DSI },
> - { .compatible = "mediatek,mt8183-dsi",
> - .data = (void *)MTK_DSI },
> - { .compatible = "mediatek,mt2701-dpi",
> - .data = (void *)MTK_DPI },
> - { .compatible = "mediatek,mt8173-dpi",
> - .data = (void *)MTK_DPI },
> - { .compatible = "mediatek,mt8183-dpi",
> - .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt2701-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2712-disp-mutex",
> @@ -448,12 +418,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8173-disp-od",
> + .data = (void *)MTK_DISP_OD },
> + { .compatible = "mediatek,mt2701-disp-ovl",
> + .data = (void *)MTK_DISP_OVL },
> + { .compatible = "mediatek,mt8173-disp-ovl",
> + .data = (void *)MTK_DISP_OVL },
> + { .compatible = "mediatek,mt8183-disp-ovl",
> + .data = (void *)MTK_DISP_OVL },
> + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> + .data = (void *)MTK_DISP_OVL_2L },
> { .compatible = "mediatek,mt2701-disp-pwm",
> .data = (void *)MTK_DISP_BLS },
> { .compatible = "mediatek,mt8173-disp-pwm",
> .data = (void *)MTK_DISP_PWM },
> - { .compatible = "mediatek,mt8173-disp-od",
> - .data = (void *)MTK_DISP_OD },
> + { .compatible = "mediatek,mt2701-disp-rdma",
> + .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8173-disp-rdma",
> + .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8183-disp-rdma",
> + .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8173-disp-ufoe",
> + .data = (void *)MTK_DISP_UFOE },
> + { .compatible = "mediatek,mt8173-disp-wdma",
> + .data = (void *)MTK_DISP_WDMA },
> + { .compatible = "mediatek,mt2701-dpi",
> + .data = (void *)MTK_DPI },
> + { .compatible = "mediatek,mt8173-dpi",
> + .data = (void *)MTK_DPI },
> + { .compatible = "mediatek,mt8183-dpi",
> + .data = (void *)MTK_DPI },
> + { .compatible = "mediatek,mt2701-dsi",
> + .data = (void *)MTK_DSI },
> + { .compatible = "mediatek,mt8173-dsi",
> + .data = (void *)MTK_DSI },
> + { .compatible = "mediatek,mt8183-dsi",
> + .data = (void *)MTK_DSI },
> { }
> };
>
> @@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> comp_type == MTK_DISP_RDMA ||
> - comp_type == MTK_DSI ||
> - comp_type == MTK_DPI) {
> + comp_type == MTK_DPI ||
> + comp_type == MTK_DSI) {
> dev_info(dev, "Adding component match for %pOF\n",
> node);
> drm_of_component_match_add(dev, &match, compare_of,
> --
> 2.18.0
>
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^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v8 10/13] drm/mediatek: adjust to the alphabetic order for mediatek-drm
2021-08-19 23:14 ` Chun-Kuang Hu
@ 2021-08-24 17:55 ` Jason-JH Lin
0 siblings, 0 replies; 28+ messages in thread
From: Jason-JH Lin @ 2021-08-24 17:55 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, fshao, Philipp Zabel,
Enric Balletbo i Serra, David Airlie, Daniel Vetter,
Fabien Parent, Hsin-Yi Wang, Yongqiang Niu, Jitao shi, Nancy Lin,
singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi Chun-Kuang,
Thanks for the review.
On Fri, 2021-08-20 at 07:14 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:24寫道：
> >
> > Adjust to the alphabetic order for the define, function, struct
> > and array in mediatek-drm driver
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 133 ++++++++++----
> > ------
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 22 ++--
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 76 +++++------
> > 3 files changed, 115 insertions(+), 116 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 93beb980414f..28bc42fd0b8a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -20,17 +20,9 @@
> > #include "mtk_drm_ddp_comp.h"
> > #include "mtk_drm_crtc.h"
> >
> > -#define DISP_REG_OD_EN 0x0000
> > -#define DISP_REG_OD_CFG 0x0020
> > -#define DISP_REG_OD_SIZE 0x0030
> > -#define DISP_REG_DITHER_5 0x0114
> > -#define DISP_REG_DITHER_7 0x011c
> > -#define DISP_REG_DITHER_15 0x013c
> > -#define DISP_REG_DITHER_16 0x0140
> > -
> > -#define DISP_REG_UFO_START 0x0000
> >
> > #define DISP_REG_AAL_EN 0x0000
> > +#define AAL_EN BIT(0)
> > #define DISP_REG_AAL_SIZE 0x0030
> >
> > #define DISP_REG_DITHER_EN 0x0000
> > @@ -38,23 +30,29 @@
> > #define DISP_REG_DITHER_CFG 0x0020
> > #define DITHER_RELAY_MODE BIT(0)
> > #define DITHER_ENGINE_EN BIT(1)
> > -#define DISP_REG_DITHER_SIZE 0x0030
> > -
> > -#define OD_RELAYMODE BIT(0)
> > -
> > -#define UFO_BYPASS BIT(2)
> > -
> > -#define AAL_EN BIT(0)
> >
> > #define DISP_DITHERING BIT(2)
> > +#define DISP_REG_DITHER_SIZE 0x0030
> > +#define DISP_REG_DITHER_5 0x0114
> > +#define DISP_REG_DITHER_7 0x011c
> > +#define DISP_REG_DITHER_15 0x013c
> > #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
> > #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
> > #define DITHER_NEW_BIT_MODE BIT(0)
> > +#define DISP_REG_DITHER_16 0x0140
> > #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
> > #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
> > #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
> > #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
> >
> > +#define DISP_REG_OD_EN 0x0000
> > +#define DISP_REG_OD_CFG 0x0020
> > +#define OD_RELAYMODE BIT(0)
> > +#define DISP_REG_OD_SIZE 0x0030
> > +
> > +#define DISP_REG_UFO_START 0x0000
> > +#define UFO_BYPASS BIT(2)
> > +
> > struct mtk_ddp_comp_dev {
> > struct clk *clk;
> > void __iomem *regs;
> > @@ -106,20 +104,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt
> > *cmdq_pkt, unsigned int value,
> > #endif
> > }
> >
> > -static int mtk_ddp_clk_enable(struct device *dev)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - return clk_prepare_enable(priv->clk);
> > -}
> > -
> > -static void mtk_ddp_clk_disable(struct device *dev)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - clk_disable_unprepare(priv->clk);
> > -}
> > -
>
> I would like to place the same group together. mtk_ddp_clk_enable()
> and mtk_ddp_clk_disable() are common function not belong to any sub
> driver. So I would like keep these function here.
>
> Regards,
> Chun-Kuang.
OK, I'll kepp them here.
Regards,
Jason-JH.Lin
>
> > void mtk_dither_set_common(void __iomem *regs, struct
> > cmdq_client_reg *cmdq_reg,
> > unsigned int bpc, unsigned int cfg,
> > unsigned int dither_en, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -146,38 +130,19 @@ void mtk_dither_set_common(void __iomem
> > *regs, struct cmdq_client_reg *cmdq_reg,
> > }
> > }
> >
> > -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > - unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > - DISP_DITHERING, cmdq_pkt);
> > -}
> > -
> > -static void mtk_od_config(struct device *dev, unsigned int w,
> > - unsigned int h, unsigned int vrefresh,
> > - unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_OD_SIZE);
> > - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_REG_OD_CFG);
> > - mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> > -}
> >
> > -static void mtk_od_start(struct device *dev)
> > +static int mtk_ddp_clk_enable(struct device *dev)
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - writel(1, priv->regs + DISP_REG_OD_EN);
> > + return clk_prepare_enable(priv->clk);
> > }
> >
> > -static void mtk_ufoe_start(struct device *dev)
> > +static void mtk_ddp_clk_disable(struct device *dev)
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> > + clk_disable_unprepare(priv->clk);
> > }
> >
> > static void mtk_aal_config(struct device *dev, unsigned int w,
> > @@ -237,6 +202,40 @@ static void mtk_dither_stop(struct device
> > *dev)
> > writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> > }
> >
> > +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > + unsigned int cfg, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > + DISP_DITHERING, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_OD_SIZE);
> > + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_REG_OD_CFG);
> > + mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_start(struct device *dev)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + writel(1, priv->regs + DISP_REG_OD_EN);
> > +}
> > +
> > +static void mtk_ufoe_start(struct device *dev)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> > +}
> > +
> > static const struct mtk_ddp_comp_funcs ddp_aal = {
> > .clk_enable = mtk_ddp_clk_enable,
> > .clk_disable = mtk_ddp_clk_disable,
> > @@ -331,22 +330,22 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ufoe = {
> > };
> >
> > static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX]
> > = {
> > + [MTK_DISP_AAL] = "aal",
> > + [MTK_DISP_BLS] = "bls",
> > + [MTK_DISP_CCORR] = "ccorr",
> > + [MTK_DISP_COLOR] = "color",
> > + [MTK_DISP_DITHER] = "dither",
> > + [MTK_DISP_GAMMA] = "gamma",
> > + [MTK_DISP_MUTEX] = "mutex",
> > + [MTK_DISP_OD] = "od",
> > [MTK_DISP_OVL] = "ovl",
> > [MTK_DISP_OVL_2L] = "ovl-2l",
> > + [MTK_DISP_PWM] = "pwm",
> > [MTK_DISP_RDMA] = "rdma",
> > - [MTK_DISP_WDMA] = "wdma",
> > - [MTK_DISP_COLOR] = "color",
> > - [MTK_DISP_CCORR] = "ccorr",
> > - [MTK_DISP_AAL] = "aal",
> > - [MTK_DISP_GAMMA] = "gamma",
> > - [MTK_DISP_DITHER] = "dither",
> > [MTK_DISP_UFOE] = "ufoe",
> > - [MTK_DSI] = "dsi",
> > + [MTK_DISP_WDMA] = "wdma",
> > [MTK_DPI] = "dpi",
> > - [MTK_DISP_PWM] = "pwm",
> > - [MTK_DISP_MUTEX] = "mutex",
> > - [MTK_DISP_OD] = "od",
> > - [MTK_DISP_BLS] = "bls",
> > + [MTK_DSI] = "dsi",
> > };
> >
> > struct mtk_ddp_comp_match {
> > @@ -500,12 +499,12 @@ int mtk_ddp_comp_init(struct device_node
> > *node, struct mtk_ddp_comp *comp,
> > type == MTK_DISP_CCORR ||
> > type == MTK_DISP_COLOR ||
> > type == MTK_DISP_GAMMA ||
> > - type == MTK_DPI ||
> > - type == MTK_DSI ||
> > type == MTK_DISP_OVL ||
> > type == MTK_DISP_OVL_2L ||
> > type == MTK_DISP_PWM ||
> > - type == MTK_DISP_RDMA)
> > + type == MTK_DISP_RDMA ||
> > + type == MTK_DPI ||
> > + type == MTK_DSI)
> > return 0;
> >
> > priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index bb914d976cf5..d317b944df66 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -18,22 +18,22 @@ struct mtk_plane_state;
> > struct drm_crtc_state;
> >
> > enum mtk_ddp_comp_type {
> > - MTK_DISP_OVL,
> > - MTK_DISP_OVL_2L,
> > - MTK_DISP_RDMA,
> > - MTK_DISP_WDMA,
> > - MTK_DISP_COLOR,
> > + MTK_DISP_AAL,
> > + MTK_DISP_BLS,
> > MTK_DISP_CCORR,
> > + MTK_DISP_COLOR,
> > MTK_DISP_DITHER,
> > - MTK_DISP_AAL,
> > MTK_DISP_GAMMA,
> > - MTK_DISP_UFOE,
> > - MTK_DSI,
> > - MTK_DPI,
> > - MTK_DISP_PWM,
> > MTK_DISP_MUTEX,
> > MTK_DISP_OD,
> > - MTK_DISP_BLS,
> > + MTK_DISP_OVL,
> > + MTK_DISP_OVL_2L,
> > + MTK_DISP_PWM,
> > + MTK_DISP_RDMA,
> > + MTK_DISP_UFOE,
> > + MTK_DISP_WDMA,
> > + MTK_DPI,
> > + MTK_DSI,
> > MTK_DDP_COMP_TYPE_MAX,
> > };
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index b46bdb8985da..a95dc1006b82 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -396,50 +396,20 @@ static const struct component_master_ops
> > mtk_drm_ops = {
> > };
> >
> > static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> > - { .compatible = "mediatek,mt2701-disp-ovl",
> > - .data = (void *)MTK_DISP_OVL },
> > - { .compatible = "mediatek,mt8173-disp-ovl",
> > - .data = (void *)MTK_DISP_OVL },
> > - { .compatible = "mediatek,mt8183-disp-ovl",
> > - .data = (void *)MTK_DISP_OVL },
> > - { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > - .data = (void *)MTK_DISP_OVL_2L },
> > - { .compatible = "mediatek,mt2701-disp-rdma",
> > - .data = (void *)MTK_DISP_RDMA },
> > - { .compatible = "mediatek,mt8173-disp-rdma",
> > - .data = (void *)MTK_DISP_RDMA },
> > - { .compatible = "mediatek,mt8183-disp-rdma",
> > - .data = (void *)MTK_DISP_RDMA },
> > - { .compatible = "mediatek,mt8173-disp-wdma",
> > - .data = (void *)MTK_DISP_WDMA },
> > + { .compatible = "mediatek,mt8173-disp-aal",
> > + .data = (void *)MTK_DISP_AAL},
> > { .compatible = "mediatek,mt8183-disp-ccorr",
> > .data = (void *)MTK_DISP_CCORR },
> > { .compatible = "mediatek,mt2701-disp-color",
> > .data = (void *)MTK_DISP_COLOR },
> > { .compatible = "mediatek,mt8173-disp-color",
> > .data = (void *)MTK_DISP_COLOR },
> > - { .compatible = "mediatek,mt8173-disp-aal",
> > - .data = (void *)MTK_DISP_AAL},
> > + { .compatible = "mediatek,mt8183-disp-dither",
> > + .data = (void *)MTK_DISP_DITHER },
> > { .compatible = "mediatek,mt8173-disp-gamma",
> > .data = (void *)MTK_DISP_GAMMA, },
> > { .compatible = "mediatek,mt8183-disp-gamma",
> > .data = (void *)MTK_DISP_GAMMA, },
> > - { .compatible = "mediatek,mt8183-disp-dither",
> > - .data = (void *)MTK_DISP_DITHER },
> > - { .compatible = "mediatek,mt8173-disp-ufoe",
> > - .data = (void *)MTK_DISP_UFOE },
> > - { .compatible = "mediatek,mt2701-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt8173-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt8183-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt2701-dpi",
> > - .data = (void *)MTK_DPI },
> > - { .compatible = "mediatek,mt8173-dpi",
> > - .data = (void *)MTK_DPI },
> > - { .compatible = "mediatek,mt8183-dpi",
> > - .data = (void *)MTK_DPI },
> > { .compatible = "mediatek,mt2701-disp-mutex",
> > .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt2712-disp-mutex",
> > @@ -448,12 +418,42 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt8183-disp-mutex",
> > .data = (void *)MTK_DISP_MUTEX },
> > + { .compatible = "mediatek,mt8173-disp-od",
> > + .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt2701-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8173-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8183-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > + .data = (void *)MTK_DISP_OVL_2L },
> > { .compatible = "mediatek,mt2701-disp-pwm",
> > .data = (void *)MTK_DISP_BLS },
> > { .compatible = "mediatek,mt8173-disp-pwm",
> > .data = (void *)MTK_DISP_PWM },
> > - { .compatible = "mediatek,mt8173-disp-od",
> > - .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt2701-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8173-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8183-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8173-disp-ufoe",
> > + .data = (void *)MTK_DISP_UFOE },
> > + { .compatible = "mediatek,mt8173-disp-wdma",
> > + .data = (void *)MTK_DISP_WDMA },
> > + { .compatible = "mediatek,mt2701-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt8173-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt8183-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt2701-dsi",
> > + .data = (void *)MTK_DSI },
> > + { .compatible = "mediatek,mt8173-dsi",
> > + .data = (void *)MTK_DSI },
> > + { .compatible = "mediatek,mt8183-dsi",
> > + .data = (void *)MTK_DSI },
> > { }
> > };
> >
> > @@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> > comp_type == MTK_DISP_OVL ||
> > comp_type == MTK_DISP_OVL_2L ||
> > comp_type == MTK_DISP_RDMA ||
> > - comp_type == MTK_DSI ||
> > - comp_type == MTK_DPI) {
> > + comp_type == MTK_DPI ||
> > + comp_type == MTK_DSI) {
> > dev_info(dev, "Adding component match for
> > %pOF\n",
> > node);
> > drm_of_component_match_add(dev, &match,
> > compare_of,
> > --
> > 2.18.0
> >
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v8 11/13] drm/mediatek: add DSC support for mediatek-drm
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (9 preceding siblings ...)
2021-08-19 2:23 ` [PATCH v8 10/13] drm/mediatek: adjust to the alphabetic order for mediatek-drm jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-19 23:16 ` Chun-Kuang Hu
2021-08-19 2:23 ` [PATCH v8 12/13] drm/mediatek: add MERGE " jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 13/13] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
12 siblings, 1 reply; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 46 +++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 28bc42fd0b8a..929630a6d832 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -45,6 +45,12 @@
#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
+#define DISP_REG_DSC_CON 0x0000
+#define DSC_EN BIT(0)
+#define DSC_DUAL_INOUT BIT(2)
+#define DSC_BYPASS BIT(4)
+#define DSC_UFOE_SEL BIT(16)
+
#define DISP_REG_OD_EN 0x0000
#define DISP_REG_OD_CFG 0x0020
#define OD_RELAYMODE BIT(0)
@@ -211,6 +217,35 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
DISP_DITHERING, cmdq_pkt);
}
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* dsc bypass mode */
+ mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_BYPASS);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_UFOE_SEL);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
static void mtk_od_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -274,6 +309,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
.stop = mtk_dpi_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+ .clk_enable = mtk_ddp_clk_enable,
+ .clk_disable = mtk_ddp_clk_disable,
+ .config = mtk_dsc_config,
+ .start = mtk_dsc_start,
+ .stop = mtk_dsc_stop,
+};
+
static const struct mtk_ddp_comp_funcs ddp_dsi = {
.start = mtk_dsi_ddp_start,
.stop = mtk_dsi_ddp_stop,
@@ -335,6 +378,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_CCORR] = "ccorr",
[MTK_DISP_COLOR] = "color",
[MTK_DISP_DITHER] = "dither",
+ [MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -364,6 +408,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
+ [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
+ [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index d317b944df66..560be6bc9d0e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_CCORR,
MTK_DISP_COLOR,
MTK_DISP_DITHER,
+ MTK_DISP_DSC,
MTK_DISP_GAMMA,
MTK_DISP_MUTEX,
MTK_DISP_OD,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v8 11/13] drm/mediatek: add DSC support for mediatek-drm
2021-08-19 2:23 ` [PATCH v8 11/13] drm/mediatek: add DSC support " jason-jh.lin
@ 2021-08-19 23:16 ` Chun-Kuang Hu
0 siblings, 0 replies; 28+ messages in thread
From: Chun-Kuang Hu @ 2021-08-19 23:16 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao,
Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, Hsin-Yi Wang, Yongqiang Niu,
Jitao shi, Nancy Lin, singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道：
>
> DSC is designed for real-time systems with real-time compression,
> transmission, decompression and display.
> The DSC standard is a specification of the algorithms used for
> compressing and decompressing image display streams, including
> the specification of the syntax and semantics of the compressed
> video bit stream.
>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 46 +++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> 2 files changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 28bc42fd0b8a..929630a6d832 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -45,6 +45,12 @@
> #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
> #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
>
> +#define DISP_REG_DSC_CON 0x0000
> +#define DSC_EN BIT(0)
> +#define DSC_DUAL_INOUT BIT(2)
> +#define DSC_BYPASS BIT(4)
> +#define DSC_UFOE_SEL BIT(16)
> +
> #define DISP_REG_OD_EN 0x0000
> #define DISP_REG_OD_CFG 0x0020
> #define OD_RELAYMODE BIT(0)
> @@ -211,6 +217,35 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
> DISP_DITHERING, cmdq_pkt);
> }
>
> +static void mtk_dsc_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + /* dsc bypass mode */
> + mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
> + DISP_REG_DSC_CON, DSC_BYPASS);
> + mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
> + DISP_REG_DSC_CON, DSC_UFOE_SEL);
> + mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
> + DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> +}
> +
> +static void mtk_dsc_start(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
> +}
> +
> +static void mtk_dsc_stop(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
> +}
> +
> static void mtk_od_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -274,6 +309,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
> .stop = mtk_dpi_stop,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> + .clk_enable = mtk_ddp_clk_enable,
> + .clk_disable = mtk_ddp_clk_disable,
> + .config = mtk_dsc_config,
> + .start = mtk_dsc_start,
> + .stop = mtk_dsc_stop,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_dsi = {
> .start = mtk_dsi_ddp_start,
> .stop = mtk_dsi_ddp_stop,
> @@ -335,6 +378,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_CCORR] = "ccorr",
> [MTK_DISP_COLOR] = "color",
> [MTK_DISP_DITHER] = "dither",
> + [MTK_DISP_DSC] = "dsc",
> [MTK_DISP_GAMMA] = "gamma",
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> @@ -364,6 +408,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
> [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
> + [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
> + [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
> [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
> [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index d317b944df66..560be6bc9d0e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_CCORR,
> MTK_DISP_COLOR,
> MTK_DISP_DITHER,
> + MTK_DISP_DSC,
> MTK_DISP_GAMMA,
> MTK_DISP_MUTEX,
> MTK_DISP_OD,
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v8 12/13] drm/mediatek: add MERGE support for mediatek-drm
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (10 preceding siblings ...)
2021-08-19 2:23 ` [PATCH v8 11/13] drm/mediatek: add DSC support " jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
2021-08-20 9:37 ` CK Hu
2021-08-20 15:43 ` Chun-Kuang Hu
2021-08-19 2:23 ` [PATCH v8 13/13] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
12 siblings, 2 replies; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 268 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
7 files changed, 297 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index dc54a7a69005..538e0087a44c 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -3,6 +3,7 @@
mediatek-drm-y := mtk_disp_ccorr.o \
mtk_disp_color.o \
mtk_disp_gamma.o \
+ mtk_disp_merge.o \
mtk_disp_ovl.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index cafd9df2d63b..f407cd9d873e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
void mtk_gamma_start(struct device *dev);
void mtk_gamma_stop(struct device *dev);
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..ebcb646bde9c
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL 0x000
+#define MERGE_EN 1
+#define DISP_REG_MERGE_CFG_0 0x010
+#define DISP_REG_MERGE_CFG_4 0x020
+#define DISP_REG_MERGE_CFG_10 0x038
+/* no swap */
+#define SWAP_MODE 0
+#define FLD_SWAP_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12 0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE 6
+#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24 0x070
+#define DISP_REG_MERGE_CFG_25 0x074
+#define DISP_REG_MERGE_CFG_36 0x0a0
+#define ULTRA_EN 1
+#define PREULTRA_EN 1
+#define HALT_FOR_DVFS_EN 0
+#define FLD_ULTRA_EN GENMASK(0, 0)
+#define FLD_PREULTRA_EN GENMASK(4, 4)
+#define FLD_HALT_FOR_DVFS_EN GENMASK(8, 8)
+#define DISP_REG_MERGE_CFG_37 0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE 3
+#define FLD_BUFFER_MODE GENMASK(1, 0)
+#define DISP_REG_MERGE_CFG_38 0x0a8
+#define FLD_VDE_BLOCK_ULTRA GENMASK(0, 0)
+#define FLD_VALID_TH_BLOCK_ULTRA GENMASK(4, 4)
+#define FLD_ULTRA_FIFO_VALID_TH GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_39 0x0ac
+#define FLD_NVDE_FORCE_PREULTRA GENMASK(8, 8)
+#define FLD_NVALID_TH_FORCE_PREULTRA GENMASK(12, 12)
+#define FLD_PREULTRA_FIFO_VALID_TH GENMASK(31, 16)
+
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40 0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW (6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH (8 * 594)
+#define FLD_ULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41 0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW (8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH (9 * 594)
+#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
+
+struct mtk_disp_merge {
+ void __iomem *regs;
+ struct clk *clk;
+ struct clk *async_clk;
+ struct cmdq_client_reg cmdq_reg;
+ bool fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+ struct cmdq_pkt *handle)
+{
+ mtk_ddp_write_mask(handle, ULTRA_EN | PREULTRA_EN << 4 | HALT_FOR_DVFS_EN << 8,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36,
+ FLD_ULTRA_EN | FLD_PREULTRA_EN | FLD_HALT_FOR_DVFS_EN);
+
+ mtk_ddp_write_mask(handle, BUFFER_MODE,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+ FLD_BUFFER_MODE);
+
+ mtk_ddp_write_mask(handle, 0,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_38,
+ FLD_VDE_BLOCK_ULTRA | FLD_VALID_TH_BLOCK_ULTRA |
+ FLD_ULTRA_FIFO_VALID_TH);
+
+ mtk_ddp_write_mask(handle, 0,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_39,
+ FLD_NVDE_FORCE_PREULTRA | FLD_NVALID_TH_FORCE_PREULTRA |
+ FLD_PREULTRA_FIFO_VALID_TH);
+
+ mtk_ddp_write_mask(handle, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+ FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+ mtk_ddp_write_mask(handle, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+ FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *handle)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+ unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+ if (!h || !w) {
+ dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+ return;
+ }
+
+ if (priv->fifo_en) {
+ mtk_merge_fifo_setting(priv, handle);
+ mode = CFG_10_10_2PI_2PO_BUF_MODE;
+ }
+
+ mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_0);
+ mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_4);
+ mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_24);
+ mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+ mtk_ddp_write_mask(handle, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+ mtk_ddp_write_mask(handle, mode, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+ int ret = 0;
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ pr_err("merge clk prepare enable failed\n");
+
+ if (priv->async_clk) {
+ ret = clk_prepare_enable(priv->async_clk);
+ if (ret)
+ pr_err("async clk prepare enable failed\n");
+ }
+
+ return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ if (priv->async_clk)
+ clk_disable_unprepare(priv->async_clk);
+
+ clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+ .bind = mtk_disp_merge_bind,
+ .unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_disp_merge *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap merge\n");
+ return PTR_ERR(priv->regs);
+ }
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get merge clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->async_clk = of_clk_get(dev->of_node, 1);
+ if (IS_ERR(priv->async_clk)) {
+ ret = PTR_ERR(priv->async_clk);
+ dev_dbg(dev, "No merge async clock: %d\n", ret);
+ priv->async_clk = NULL;
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ priv->fifo_en = of_property_read_bool(dev->of_node,
+ "mediatek,merge-fifo-en");
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_disp_merge_component_ops);
+ if (ret != 0)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-merge", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+ .probe = mtk_disp_merge_probe,
+ .remove = mtk_disp_merge_remove,
+ .driver = {
+ .name = "mediatek-disp-merge",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_merge_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 929630a6d832..ee8efc13eaea 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -331,6 +331,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
.stop = mtk_gamma_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+ .start = mtk_merge_start,
+ .stop = mtk_merge_stop,
+ .config = mtk_merge_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_od = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -380,6 +388,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_DITHER] = "dither",
[MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
+ [MTK_DISP_MERGE] = "merge",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
@@ -415,6 +424,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
+ [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
+ [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
+ [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
+ [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
+ [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
+ [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
@@ -545,6 +560,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_CCORR ||
type == MTK_DISP_COLOR ||
type == MTK_DISP_GAMMA ||
+ type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 560be6bc9d0e..b42a47c06956 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_DITHER,
MTK_DISP_DSC,
MTK_DISP_GAMMA,
+ MTK_DISP_MERGE,
MTK_DISP_MUTEX,
MTK_DISP_OD,
MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a95dc1006b82..aba26a704d9c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -539,6 +539,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
if (comp_type == MTK_DISP_CCORR ||
comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_GAMMA ||
+ comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_RDMA ||
@@ -639,6 +640,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_ccorr_driver,
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
+ &mtk_disp_merge_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 637f5669e895..0fa417219a69 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -49,6 +49,7 @@ struct mtk_drm_private {
extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
--
2.18.0
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^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v8 12/13] drm/mediatek: add MERGE support for mediatek-drm
2021-08-19 2:23 ` [PATCH v8 12/13] drm/mediatek: add MERGE " jason-jh.lin
@ 2021-08-20 9:37 ` CK Hu
2021-08-20 15:43 ` Chun-Kuang Hu
1 sibling, 0 replies; 28+ messages in thread
From: CK Hu @ 2021-08-20 9:37 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao,
Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, Yongqiang Niu, Jitao shi,
nancy.lin, singo.chang, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel, dri-devel
Hi, Jason:
On Thu, 2021-08-19 at 10:23 +0800, jason-jh.lin wrote:
> Add MERGE engine file:
> MERGE module is used to merge two slice-per-line inputs
> into one side-by-side output.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
[snip]
> +
> +int mtk_merge_clk_enable(struct device *dev)
> +{
> + int ret = 0;
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + ret = clk_prepare_enable(priv->clk);
> + if (ret)
> + pr_err("merge clk prepare enable failed\n");
> +
> + if (priv->async_clk) {
This checking is redundant.
> + ret = clk_prepare_enable(priv->async_clk);
> + if (ret)
> + pr_err("async clk prepare enable failed\n");
> + }
> +
> + return ret;
> +}
> +
> +void mtk_merge_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + if (priv->async_clk)
Ditto.
Regards,
CK
> + clk_disable_unprepare(priv->async_clk);
> +
> + clk_disable_unprepare(priv->clk);
> +}
> +
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^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v8 12/13] drm/mediatek: add MERGE support for mediatek-drm
2021-08-19 2:23 ` [PATCH v8 12/13] drm/mediatek: add MERGE " jason-jh.lin
2021-08-20 9:37 ` CK Hu
@ 2021-08-20 15:43 ` Chun-Kuang Hu
2021-08-25 9:34 ` Jason-JH Lin
1 sibling, 1 reply; 28+ messages in thread
From: Chun-Kuang Hu @ 2021-08-20 15:43 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao,
Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, Hsin-Yi Wang, Yongqiang Niu,
Jitao shi, Nancy Lin, singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道：
>
> Add MERGE engine file:
> MERGE module is used to merge two slice-per-line inputs
> into one side-by-side output.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 268 ++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 7 files changed, 297 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index dc54a7a69005..538e0087a44c 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -3,6 +3,7 @@
> mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_disp_color.o \
> mtk_disp_gamma.o \
> + mtk_disp_merge.o \
> mtk_disp_ovl.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index cafd9df2d63b..f407cd9d873e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
> void mtk_gamma_start(struct device *dev);
> void mtk_gamma_stop(struct device *dev);
>
> +int mtk_merge_clk_enable(struct device *dev);
> +void mtk_merge_clk_disable(struct device *dev);
> +void mtk_merge_config(struct device *dev, unsigned int width,
> + unsigned int height, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_start(struct device *dev);
> +void mtk_merge_stop(struct device *dev);
> +
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> new file mode 100644
> index 000000000000..ebcb646bde9c
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -0,0 +1,268 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_drv.h"
> +
> +#define DISP_REG_MERGE_CTRL 0x000
> +#define MERGE_EN 1
> +#define DISP_REG_MERGE_CFG_0 0x010
> +#define DISP_REG_MERGE_CFG_4 0x020
> +#define DISP_REG_MERGE_CFG_10 0x038
> +/* no swap */
> +#define SWAP_MODE 0
> +#define FLD_SWAP_MODE GENMASK(4, 0)
> +#define DISP_REG_MERGE_CFG_12 0x040
> +#define CFG_10_10_1PI_2PO_BUF_MODE 6
> +#define CFG_10_10_2PI_2PO_BUF_MODE 8
> +#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
> +#define DISP_REG_MERGE_CFG_24 0x070
> +#define DISP_REG_MERGE_CFG_25 0x074
> +#define DISP_REG_MERGE_CFG_36 0x0a0
> +#define ULTRA_EN 1
You could use FLD_ULTRA_EN for this.
> +#define PREULTRA_EN 1
> +#define HALT_FOR_DVFS_EN 0
You could just not set this.
> +#define FLD_ULTRA_EN GENMASK(0, 0)
#define FLD_ULTRA_EN BIT(0)
Regards,
Chun-Kuang.
> +#define FLD_PREULTRA_EN GENMASK(4, 4)
> +#define FLD_HALT_FOR_DVFS_EN GENMASK(8, 8)
> +#define DISP_REG_MERGE_CFG_37 0x0a4
> +/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
> +#define BUFFER_MODE 3
> +#define FLD_BUFFER_MODE GENMASK(1, 0)
> +#define DISP_REG_MERGE_CFG_38 0x0a8
> +#define FLD_VDE_BLOCK_ULTRA GENMASK(0, 0)
> +#define FLD_VALID_TH_BLOCK_ULTRA GENMASK(4, 4)
> +#define FLD_ULTRA_FIFO_VALID_TH GENMASK(31, 16)
> +#define DISP_REG_MERGE_CFG_39 0x0ac
> +#define FLD_NVDE_FORCE_PREULTRA GENMASK(8, 8)
> +#define FLD_NVALID_TH_FORCE_PREULTRA GENMASK(12, 12)
> +#define FLD_PREULTRA_FIFO_VALID_TH GENMASK(31, 16)
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v8 12/13] drm/mediatek: add MERGE support for mediatek-drm
2021-08-20 15:43 ` Chun-Kuang Hu
@ 2021-08-25 9:34 ` Jason-JH Lin
0 siblings, 0 replies; 28+ messages in thread
From: Jason-JH Lin @ 2021-08-25 9:34 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, fshao, Philipp Zabel,
Enric Balletbo i Serra, David Airlie, Daniel Vetter,
Fabien Parent, Hsin-Yi Wang, Yongqiang Niu, Jitao shi, Nancy Lin,
singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi Chun-Kuang,
Thanks for the review.
On Fri, 2021-08-20 at 23:43 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:23寫道：
> >
> > Add MERGE engine file:
> > MERGE module is used to merge two slice-per-line inputs
> > into one side-by-side output.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 268
> > ++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 ++
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > 7 files changed, 297 insertions(+)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index dc54a7a69005..538e0087a44c 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -3,6 +3,7 @@
> > mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_disp_color.o \
> > mtk_disp_gamma.o \
> > + mtk_disp_merge.o \
> > mtk_disp_ovl.o \
> > mtk_disp_rdma.o \
> > mtk_drm_crtc.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index cafd9df2d63b..f407cd9d873e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs,
> > struct drm_crtc_state *state);
> > void mtk_gamma_start(struct device *dev);
> > void mtk_gamma_stop(struct device *dev);
> >
> > +int mtk_merge_clk_enable(struct device *dev);
> > +void mtk_merge_clk_disable(struct device *dev);
> > +void mtk_merge_config(struct device *dev, unsigned int width,
> > + unsigned int height, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_merge_start(struct device *dev);
> > +void mtk_merge_stop(struct device *dev);
> > +
> > void mtk_ovl_bgclr_in_on(struct device *dev);
> > void mtk_ovl_bgclr_in_off(struct device *dev);
> > void mtk_ovl_bypass_shadow(struct device *dev);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > new file mode 100644
> > index 000000000000..ebcb646bde9c
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > @@ -0,0 +1,268 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_drv.h"
> > +
> > +#define DISP_REG_MERGE_CTRL 0x000
> > +#define MERGE_EN 1
> > +#define DISP_REG_MERGE_CFG_0 0x010
> > +#define DISP_REG_MERGE_CFG_4 0x020
> > +#define DISP_REG_MERGE_CFG_10 0x038
> > +/* no swap */
> > +#define SWAP_MODE 0
> > +#define FLD_SWAP_MODE GENMASK(4, 0)
> > +#define DISP_REG_MERGE_CFG_12 0x040
> > +#define CFG_10_10_1PI_2PO_BUF_MODE 6
> > +#define CFG_10_10_2PI_2PO_BUF_MODE 8
> > +#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
> > +#define DISP_REG_MERGE_CFG_24 0x070
> > +#define DISP_REG_MERGE_CFG_25 0x074
> > +#define DISP_REG_MERGE_CFG_36 0x0a0
> > +#define ULTRA_EN 1
>
> You could use FLD_ULTRA_EN for this.
OK, I'll use mtk_ddp_write() directly, if the bit width of setting is
always the same as mask.
>
> > +#define PREULTRA_EN 1
> > +#define HALT_FOR_DVFS_EN 0
>
> You could just not set this.
OK, I'll remove the setting of 0.
>
> > +#define FLD_ULTRA_EN GENMASK(0, 0)
>
> #define FLD_ULTRA_EN BIT(0)
>
> Regards,
> Chun-Kuang.
>
OK, I'll just use BIT(n) instead of GENMASK(n, n).
Regards,
Jason-JH.Lin
> > +#define FLD_PREULTRA_EN GENMASK(4,
> > 4)
> > +#define FLD_HALT_FOR_DVFS_EN GENMASK(8, 8)
> > +#define DISP_REG_MERGE_CFG_37 0x0a4
> > +/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
> > +#define BUFFER_MODE 3
> > +#define FLD_BUFFER_MODE GENMASK(1,
> > 0)
> > +#define DISP_REG_MERGE_CFG_38 0x0a8
> > +#define FLD_VDE_BLOCK_ULTRA GENMASK(0, 0)
> > +#define FLD_VALID_TH_BLOCK_ULTRA GENMASK(4, 4)
> > +#define FLD_ULTRA_FIFO_VALID_TH GENMASK(31,
> > 16)
> > +#define DISP_REG_MERGE_CFG_39 0x0ac
> > +#define FLD_NVDE_FORCE_PREULTRA GENMASK(8,
> > 8)
> > +#define FLD_NVALID_TH_FORCE_PREULTRA GENMASK(12, 12)
> > +#define FLD_PREULTRA_FIFO_VALID_TH GENMASK(31, 16)
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v8 13/13] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (11 preceding siblings ...)
2021-08-19 2:23 ` [PATCH v8 12/13] drm/mediatek: add MERGE " jason-jh.lin
@ 2021-08-19 2:23 ` jason-jh.lin
12 siblings, 0 replies; 28+ messages in thread
From: jason-jh.lin @ 2021-08-19 2:23 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, fshao
Cc: Philipp Zabel, Enric Balletbo i Serra, David Airlie,
Daniel Vetter, Fabien Parent, hsinyi, jason-jh . lin,
Yongqiang Niu, Jitao shi, nancy.lin, singo.chang, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28 ++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 705f28ceb4dd..0d3d3c834e0f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -353,6 +353,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+ .fifo_size = 1920,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
@@ -360,6 +364,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
.data = &mt8173_rdma_driver_data},
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = &mt8183_rdma_driver_data},
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = &mt8195_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index aba26a704d9c..18b89ab990c0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_DP_INTF0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .main_path = mt8195_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -406,10 +424,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8183-disp-dither",
.data = (void *)MTK_DISP_DITHER },
+ { .compatible = "mediatek,mt8195-disp-dsc",
+ .data = (void *)MTK_DISP_DSC },
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8183-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)MTK_DISP_MERGE },
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -418,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -438,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -468,6 +494,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8173_mmsys_driver_data},
{ .compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data},
+ {.compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
--
2.18.0
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^ permalink raw reply related [flat|nested] 28+ messages in thread