* [PATCH v6 0/5] media: mediatek: support mdp3 on mt8183 platform
@ 2021-08-19 7:09 Moudy Ho
2021-08-19 7:09 ` [PATCH v6 1/5] soc: mediatek: mmsys: Add support for MDP Moudy Ho
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Moudy Ho @ 2021-08-19 7:09 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
Changes since v5:
- Rebase on v5.14-rc6.
- Move MMSYS/Mutex settings to corresponding driver.
- Revise the software license description and copyright.
- Remove unnecessary enum. or definitions.
- Optimize platform/chip definition conditions.
- Use general printing functions instead of MDP3 private ones.
- Fix compile warning.
Changes since v4:
- Rebase on v5.13-rc1.
- Remove the CMDQ flush flow to match the CMDQ API change.
- Integrate four of MDP's direct-link subcomponents into MDP controller node
from syscon node to avoid illegal clock usage.
- Rewrite dt-binding in a JSON compatible subset of YAML
- Fix a bit of macro argument precedence.
Changes since v3:
- Rebase on v5.9-rc1.
- modify code for review comment from Rob Herring, cancel multiple nodes using
same register base situation.
- control IOMMU port through pm runtime get/put to DMA components' device.
- SCP(VPU) driver revision.
- stop queuing jobs(remove flush_workqueue()) after mdp_m2m_release().
- add computation of plane address with data_offset.
- fix scale ratio check issue.
- add default v4l2_format setting.
Changes since v2:
- modify code for review comment from Tomasz Figa & Alexandre Courbot
- review comment from Rob Herring will offer code revision in v4, due to
it's related to device node modification, will need to modify code
architecture
Changes since v1:
- modify code for CMDQ v3 API support
- EC ipi cmd migration
- fix compliance test fail item (m2m cmd with -f) due to there is two problem in runing all format(-f) cmd:
1. out of memory before test complete
Due to capture buffer mmap (refcount + 1) after reqbuf but seems
no corresponding munmap called before device close.
There are total 12XX items(formats) in format test and each format
alloc 8 capture/output buffers.
2. unceasingly captureBufs() (randomly)
Seems the break statement didn't catch the count == 0 situation:
In v4l2-test-buffers.cpp, function: captureBufs()
...
count--;
if (!node->is_m2m && !count)
break;
Log is as attachment
I will paste the test result with problem part in another e-mail
Hi,
This is the first version of RFC patch for Media Data Path 3 (MDP3),
MDP3 is used for scaling and color format conversion.
support using GCE to write register in critical time limitation.
support V4L2 m2m device control.
Moudy Ho (5):
soc: mediatek: mmsys: Add support for MDP
soc: mediatek: mutex: add support for MDP
dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
dts: arm64: mt8183: Add Mediatek MDP3 nodes
media: platform: mtk-mdp3: Add Mediatek MDP3 driver
.../bindings/media/mediatek,mdp3-ccorr.yaml | 58 +
.../bindings/media/mediatek,mdp3-rdma.yaml | 241 +++
.../bindings/media/mediatek,mdp3-rsz.yaml | 66 +
.../bindings/media/mediatek,mdp3-wdma.yaml | 71 +
.../bindings/media/mediatek,mdp3-wrot.yaml | 71 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 110 ++
drivers/media/platform/Kconfig | 19 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/mtk-mdp3/Makefile | 7 +
drivers/media/platform/mtk-mdp3/isp_reg.h | 27 +
.../media/platform/mtk-mdp3/mdp_reg_ccorr.h | 19 +
.../media/platform/mtk-mdp3/mdp_reg_rdma.h | 65 +
drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 39 +
.../media/platform/mtk-mdp3/mdp_reg_wdma.h | 47 +
.../media/platform/mtk-mdp3/mdp_reg_wrot.h | 55 +
drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 281 ++++
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 508 ++++++
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 47 +
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 1357 +++++++++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 148 ++
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 300 ++++
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 75 +
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 802 ++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.h | 42 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 747 +++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 373 +++++
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 314 ++++
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 79 +
drivers/soc/mediatek/mt8183-mmsys.h | 235 +++
drivers/soc/mediatek/mtk-mmsys.c | 164 ++
drivers/soc/mediatek/mtk-mmsys.h | 9 +-
drivers/soc/mediatek/mtk-mutex.c | 106 +-
include/linux/soc/mediatek/mtk-mmsys.h | 81 +
include/linux/soc/mediatek/mtk-mutex.h | 8 +
34 files changed, 6564 insertions(+), 9 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
create mode 100644 drivers/media/platform/mtk-mdp3/Makefile
create mode 100644 drivers/media/platform/mtk-mdp3/isp_reg.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ccorr.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wdma.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
--
2.18.0
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v6 1/5] soc: mediatek: mmsys: Add support for MDP
2021-08-19 7:09 [PATCH v6 0/5] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
@ 2021-08-19 7:09 ` Moudy Ho
2021-08-19 7:09 ` [PATCH v6 2/5] soc: mediatek: mutex: add " Moudy Ho
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Moudy Ho @ 2021-08-19 7:09 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
Add functions to support MDP:
1. MDP connect/disconnect functions
2. ISP control function
3. Write register via CMDQ
Add MDP related settings for 8183 SoC
1. Register settings
2. MDP route table
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
drivers/soc/mediatek/mt8183-mmsys.h | 235 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 164 +++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 9 +-
include/linux/soc/mediatek/mtk-mmsys.h | 81 +++++++++
4 files changed, 486 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 579dfc8dc8fc..2fa79e745a45 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -12,6 +12,32 @@
#define MT8183_DISP_DPI0_SEL_IN 0xf30
#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
+#define MT8183_MDP_ISP_MOUT_EN 0xf80
+#define MT8183_MDP_RDMA0_MOUT_EN 0xf84
+#define MT8183_MDP_PRZ0_MOUT_EN 0xf8c
+#define MT8183_MDP_PRZ1_MOUT_EN 0xf90
+#define MT8183_MDP_COLOR_MOUT_EN 0xf94
+#define MT8183_MDP_IPU_MOUT_EN 0xf98
+#define MT8183_MDP_PATH0_SOUT_SEL 0xfa8
+#define MT8183_MDP_PATH1_SOUT_SEL 0xfac
+#define MT8183_MDP_PRZ0_SEL_IN 0xfc0
+#define MT8183_MDP_PRZ1_SEL_IN 0xfc4
+#define MT8183_MDP_TDSHP_SEL_IN 0xfc8
+#define MT8183_MDP_WROT0_SEL_IN 0xfd0
+#define MT8183_MDP_WDMA_SEL_IN 0xfd4
+#define MT8183_MDP_PATH0_SEL_IN 0xfe0
+#define MT8183_MDP_PATH1_SEL_IN 0xfe4
+#define MT8183_MDP_AAL_MOUT_EN 0xfe8
+#define MT8183_MDP_AAL_SEL_IN 0xfec
+#define MT8183_MDP_CCORR_SEL_IN 0xff0
+#define MT8183_MDP_CCORR_SOUT_SEL 0xff4
+
+#define MT8183_ISP_CTRL_MMSYS_SW0_RST_B 0x140
+#define MT8183_ISP_CTRL_MMSYS_SW1_RST_B 0x144
+#define MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD 0x934
+#define MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD 0x93C
+#define MT8183_ISP_CTRL_ISP_RELAY_CFG_WD 0x994
+#define MT8183_ISP_CTRL_IPU_RELAY_CFG_WD 0x9a0
#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
@@ -24,6 +50,55 @@
#define MT8183_DPI0_SEL_IN_RDMA1 0x2
#define MT8183_RDMA0_SOUT_COLOR0 0x1
#define MT8183_RDMA1_SOUT_DSI0 0x1
+#define MT8183_MDP_ISP_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_ISP_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_ISP_MOUT_EN_AAL0 BIT(2)
+#define MT8183_MDP_IPU_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_IPU_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_IPU_MOUT_EN_AAL0 BIT(2)
+#define MT8183_MDP_RDMA0_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_RDMA0_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT BIT(2)
+#define MT8183_MDP_RDMA0_MOUT_EN_AAL0 BIT(3)
+#define MT8183_MDP_AAL_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_AAL_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_AAL_MOUT_EN_RSZ0 BIT(2)
+#define MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_PRZ0_MOUT_EN_TDSHP0 BIT(1)
+#define MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_PRZ1_MOUT_EN_TDSHP0 BIT(1)
+#define MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT BIT(2)
+#define MT8183_MDP_PRZ1_MOUT_EN_COLOR0 BIT(4)
+#define MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT BIT(1)
+#define MT8183_MDP_AAL_SEL_IN_CAMIN 0
+#define MT8183_MDP_AAL_SEL_IN_RDMA0 1
+#define MT8183_MDP_AAL_SEL_IN_CAMIN2 2
+#define MT8183_MDP_AAL_SEL_IN_CCORR0 3
+#define MT8183_MDP_CCORR_SEL_IN_CAMIN 0
+#define MT8183_MDP_CCORR_SEL_IN_RDMA0 1
+#define MT8183_MDP_CCORR_SEL_IN_CAMIN2 3
+#define MT8183_MDP_CCORR_SEL_IN_AAL0 4
+#define MT8183_MDP_PRZ0_SEL_IN_AAL0 0
+#define MT8183_MDP_PRZ0_SEL_IN_CCORR0 1
+#define MT8183_MDP_PRZ1_SEL_IN_CAMIN 0
+#define MT8183_MDP_PRZ1_SEL_IN_RDMA0 1
+#define MT8183_MDP_PRZ1_SEL_IN_CAMIN2 4
+#define MT8183_MDP_PRZ1_SEL_IN_AAL0 5
+#define MT8183_MDP_TDSHP_SEL_IN_RSZ0 0
+#define MT8183_MDP_TDSHP_SEL_IN_RSZ1 1
+#define MT8183_MDP_PATH0_SEL_IN_RSZ0 0
+#define MT8183_MDP_PATH0_SEL_IN_RSZ1 1
+#define MT8183_MDP_PATH0_SEL_IN_COLOR0 2
+#define MT8183_MDP_PATH0_SEL_IN_RDMA0 3
+#define MT8183_MDP_PATH1_SEL_IN_RSZ1 0
+#define MT8183_MDP_PATH1_SEL_IN_COLOR0 1
+#define MT8183_MDP_WROT0_SEL_IN_PATH0_OUT 0
+#define MT8183_MDP_WDMA_SEL_IN_PATH1_OUT 0
+#define MT8183_MDP_CCORR_SOUT_SEL_AAL0 0
+#define MT8183_MDP_CCORR_SOUT_SEL_RSZ0 1
+#define MT8183_MDP_PATH0_SOUT_SEL_WROT0 0
+#define MT8183_MDP_PATH1_SOUT_SEL_WDMA 0
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
{
@@ -50,5 +125,165 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
}
};
+static const struct mtk_mmsys_routes mmsys_mt8183_mdp_routing_table[] = {
+ {
+ MDP_COMP_CAMIN, MDP_COMP_CCORR0,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_RSZ1,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_AAL0,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_AAL0,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_CCORR0,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_RSZ1,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_AAL0,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_CCORR0,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ1,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ0,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ0
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PRZ0_MOUT_EN, MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
+ MT8183_MDP_PRZ0_MOUT_EN, MT8183_MDP_PRZ0_MOUT_EN_TDSHP0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_TDSHP0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_COLOR0,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_COLOR0
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_COLOR_MOUT_EN, MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_COLOR_MOUT_EN, MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_AAL0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ0,
+ MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_AAL0
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_RSZ0,
+ MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_AAL0
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
+ MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
+ MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_COLOR0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_COLOR0
+ }, {
+ MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
+ MT8183_MDP_WROT0_SEL_IN, MT8183_MDP_WROT0_SEL_IN_PATH0_OUT
+ }, {
+ MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
+ MT8183_MDP_WDMA_SEL_IN, MT8183_MDP_WDMA_SEL_IN_PATH1_OUT
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_AAL0,
+ MT8183_MDP_CCORR_SOUT_SEL, MT8183_MDP_CCORR_SOUT_SEL_AAL0
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_RSZ0,
+ MT8183_MDP_CCORR_SOUT_SEL, MT8183_MDP_CCORR_SOUT_SEL_RSZ0
+ }, {
+ MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
+ MT8183_MDP_PATH0_SOUT_SEL, MT8183_MDP_PATH0_SOUT_SEL_WROT0
+ }, {
+ MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
+ MT8183_MDP_PATH1_SOUT_SEL, MT8183_MDP_PATH1_SOUT_SEL_WDMA
+ }
+};
+
+static const unsigned int mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
+ [ISP_CTRL_MMSYS_SW0_RST_B] = MT8183_ISP_CTRL_MMSYS_SW0_RST_B,
+ [ISP_CTRL_MMSYS_SW1_RST_B] = MT8183_ISP_CTRL_MMSYS_SW1_RST_B,
+ [ISP_CTRL_MDP_ASYNC_CFG_WD] = MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD,
+ [ISP_CTRL_MDP_ASYNC_IPU_CFG_WD] = MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD,
+ [ISP_CTRL_ISP_RELAY_CFG_WD] = MT8183_ISP_CTRL_ISP_RELAY_CFG_WD,
+ [ISP_CTRL_IPU_RELAY_CFG_WD] = MT8183_ISP_CTRL_IPU_RELAY_CFG_WD,
+};
+
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 080660ef11bf..c4b99a99ee1e 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -7,8 +7,10 @@
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
@@ -50,11 +52,16 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+ .mdp_routes = mmsys_mt8183_mdp_routing_table,
+ .mdp_num_routes = ARRAY_SIZE(mmsys_mt8183_mdp_routing_table),
+ .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
};
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
+ phys_addr_t addr;
+ u8 subsys_id;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -91,12 +98,160 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_mdp_connect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
+ int i;
+
+ WARN_ON(!routes);
+ WARN_ON(mmsys->subsys_id == 0);
+ for (i = 0; i < mmsys->data->mdp_num_routes; i++)
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
+ mmsys->addr + routes[i].addr,
+ routes[i].val, 0xFFFFFFFF);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_connect);
+
+void mtk_mmsys_mdp_disconnect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
+ int i;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ for (i = 0; i < mmsys->data->mdp_num_routes; i++)
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
+ mmsys->addr + routes[i].addr,
+ 0, 0xFFFFFFFF);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_disconnect);
+
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ /* Direct link */
+ if (id == MDP_COMP_CAMIN) {
+ /* Reset MDP_DL_ASYNC_TX */
+ /* Bit 3: MDP_DL_ASYNC_TX / MDP_RELAY */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000008);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 3, 0x00000008);
+ }
+
+ /* Reset MDP_DL_ASYNC_RX */
+ /* Bit 10: MDP_DL_ASYNC_RX */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000400);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 10, 0x00000400);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0 << 31, 0x80000000);
+ }
+ }
+
+ if (id == MDP_COMP_CAMIN2) {
+ /* Reset MDP_DL_ASYNC2_TX */
+ /* Bit 4: MDP_DL_ASYNC2_TX / MDP_RELAY2 */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000010);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 4, 0x00000010);
+ }
+
+ /* Reset MDP_DL_ASYNC2_RX */
+ /* Bit 11: MDP_DL_ASYNC2_RX */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000800);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 11, 0x00000800);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0 << 31, 0x80000000);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id, u32 camin_w, u32 camin_h)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ /* Config for direct link */
+ if (id == MDP_COMP_CAMIN) {
+ if (isp_ctrl[ISP_CTRL_MDP_ASYNC_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MDP_ASYNC_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+
+ if (isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+ if (id == MDP_COMP_CAMIN2) {
+ if (isp_ctrl[ISP_CTRL_MDP_ASYNC_IPU_CFG_WD]) {
+ reg = mmsys->addr +
+ isp_ctrl[ISP_CTRL_MDP_ASYNC_IPU_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ if (isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct platform_device *clks;
struct platform_device *drm;
struct mtk_mmsys *mmsys;
+ struct resource res;
+ struct cmdq_client_reg cmdq_reg;
int ret;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -110,6 +265,15 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
+ if (of_address_to_resource(dev->of_node, 0, &res) < 0)
+ mmsys->addr = 0L;
+ else
+ mmsys->addr = res.start;
+
+ if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
+ dev_info(dev, "cmdq subsys id has not been set\n");
+ mmsys->subsys_id = cmdq_reg.subsys;
+
mmsys->data = of_device_get_match_data(&pdev->dev);
platform_set_drvdata(pdev, mmsys);
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index a760a34e6eca..025d4bc9c8cc 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -74,9 +74,12 @@ struct mtk_mmsys_routes {
};
struct mtk_mmsys_driver_data {
- const char *clk_driver;
- const struct mtk_mmsys_routes *routes;
- const unsigned int num_routes;
+ const char *clk_driver;
+ const struct mtk_mmsys_routes *routes;
+ const unsigned int num_routes;
+ const struct mtk_mmsys_routes *mdp_routes;
+ const unsigned int mdp_num_routes;
+ const unsigned int *mdp_isp_ctrl;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..1234e8c0aefd 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -7,8 +7,14 @@
#define __MTK_MMSYS_H
enum mtk_ddp_comp_id;
+enum mtk_mdp_comp_id;
struct device;
+struct mmsys_cmdq_cmd {
+ struct cmdq_pkt *pkt;
+ s32 *event;
+};
+
enum mtk_ddp_comp_id {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_AAL1,
@@ -42,6 +48,64 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mdp_comp_id {
+ MDP_COMP_NONE = -1, /* Invalid engine */
+
+ /* ISP */
+ MDP_COMP_WPEI = 0,
+ MDP_COMP_WPEO, /* 1 */
+ MDP_COMP_WPEI2, /* 2 */
+ MDP_COMP_WPEO2, /* 3 */
+ MDP_COMP_ISP_IMGI, /* 4 */
+ MDP_COMP_ISP_IMGO, /* 5 */
+ MDP_COMP_ISP_IMG2O, /* 6 */
+
+ /* IPU */
+ MDP_COMP_IPUI, /* 7 */
+ MDP_COMP_IPUO, /* 8 */
+
+ /* MDP */
+ MDP_COMP_CAMIN, /* 9 */
+ MDP_COMP_CAMIN2, /* 10 */
+ MDP_COMP_RDMA0, /* 11 */
+ MDP_COMP_AAL0, /* 12 */
+ MDP_COMP_CCORR0, /* 13 */
+ MDP_COMP_RSZ0, /* 14 */
+ MDP_COMP_RSZ1, /* 15 */
+ MDP_COMP_TDSHP0, /* 16 */
+ MDP_COMP_COLOR0, /* 17 */
+ MDP_COMP_PATH0_SOUT, /* 18 */
+ MDP_COMP_PATH1_SOUT, /* 19 */
+ MDP_COMP_WROT0, /* 20 */
+ MDP_COMP_WDMA, /* 21 */
+
+ /* Dummy Engine */
+ MDP_COMP_RDMA1, /* 22 */
+ MDP_COMP_RSZ2, /* 23 */
+ MDP_COMP_TDSHP1, /* 24 */
+ MDP_COMP_WROT1, /* 25 */
+
+ MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
+};
+
+enum mtk_mdp_pipe_id {
+ MDP_PIPE_IMGI,
+ MDP_PIPE_RDMA0,
+ MDP_PIPE_WPEI,
+ MDP_PIPE_WPEI2,
+ MDP_PIPE_MAX
+};
+
+enum mtk_isp_ctrl {
+ ISP_CTRL_MMSYS_SW0_RST_B,
+ ISP_CTRL_MMSYS_SW1_RST_B,
+ ISP_CTRL_MDP_ASYNC_CFG_WD,
+ ISP_CTRL_MDP_ASYNC_IPU_CFG_WD,
+ ISP_CTRL_ISP_RELAY_CFG_WD,
+ ISP_CTRL_IPU_RELAY_CFG_WD,
+ ISP_CTRL_MAX
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -50,4 +114,21 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_mdp_connect(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next);
+
+void mtk_mmsys_mdp_disconnect(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next);
+
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id,
+ u32 camin_w, u32 camin_h);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v6 2/5] soc: mediatek: mutex: add support for MDP
2021-08-19 7:09 [PATCH v6 0/5] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2021-08-19 7:09 ` [PATCH v6 1/5] soc: mediatek: mmsys: Add support for MDP Moudy Ho
@ 2021-08-19 7:09 ` Moudy Ho
2021-08-19 7:09 ` [PATCH v6 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings Moudy Ho
2021-08-19 7:09 ` [PATCH v6 4/5] dts: arm64: mt8183: Add Mediatek MDP3 nodes Moudy Ho
3 siblings, 0 replies; 8+ messages in thread
From: Moudy Ho @ 2021-08-19 7:09 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
Add functions to support MDP:
1. Get mutex function
2. Enable/disable mutex
3. Enable MDP's modules
4. Write register via CMDQ
Add MDP related settings for 8183 SoC
1. Register settings
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 106 +++++++++++++++++++++++--
include/linux/soc/mediatek/mtk-mutex.h | 8 ++
2 files changed, 108 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..935f2849a094 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -7,9 +7,11 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include <linux/soc/mediatek/mtk-mutex.h>
#define MT2701_MUTEX0_MOD0 0x2c
@@ -107,6 +109,10 @@
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8183_MUTEX_MDP_START 5
+#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
+#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
+
struct mtk_mutex {
int id;
bool claimed;
@@ -123,11 +129,14 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
- const unsigned int *mutex_sof;
- const unsigned int mutex_mod_reg;
- const unsigned int mutex_sof_reg;
- const bool no_clk;
+ const unsigned int *mutex_mod;
+ const unsigned int *mutex_sof;
+ const unsigned int mutex_mod_reg;
+ const unsigned int mutex_sof_reg;
+ const unsigned int *mutex_mdp_offset;
+ const unsigned int mutex_mdp_mod_mask;
+ const unsigned int mutex_mdp_sof_mask;
+ const bool no_clk;
};
struct mtk_mutex_ctx {
@@ -136,6 +145,8 @@ struct mtk_mutex_ctx {
void __iomem *regs;
struct mtk_mutex mutex[10];
const struct mtk_mutex_data *data;
+ phys_addr_t addr;
+ u8 subsys_id;
};
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -238,6 +249,14 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
};
+/* indicate which mutex is used by each pipepline */
+static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
+ [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
+ [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
+ [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -272,6 +291,9 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.mutex_sof = mt8183_mutex_sof,
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
+ .mutex_mdp_offset = mt8183_mutex_mdp_offset,
+ .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
.no_clk = true,
};
@@ -290,6 +312,21 @@ struct mtk_mutex *mtk_mutex_get(struct device *dev)
}
EXPORT_SYMBOL_GPL(mtk_mutex_get);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id)
+{
+ struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
+ int i = mtx->data->mutex_mdp_offset[id];
+
+ if (!mtx->mutex[i].claimed) {
+ mtx->mutex[i].claimed = true;
+ return &mtx->mutex[i];
+ }
+
+ return ERR_PTR(-EBUSY);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
+
void mtk_mutex_put(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -369,6 +406,25 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
}
EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
+void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+ unsigned int offset;
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
+ mod, mtx->data->mutex_mdp_mod_mask);
+
+ offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
+ 0, mtx->data->mutex_mdp_sof_mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_add_mdp_mod);
+
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id)
{
@@ -420,6 +476,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_enable);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ 0x1, 0x00000001);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
+
void mtk_mutex_disable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -431,6 +501,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_disable);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ 0x0, 0x00000001);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
+
void mtk_mutex_acquire(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -458,7 +542,8 @@ static int mtk_mutex_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_mutex_ctx *mtx;
- struct resource *regs;
+ struct cmdq_client_reg cmdq_reg;
+ struct resource *regs, addr;
int i;
mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
@@ -479,6 +564,15 @@ static int mtk_mutex_probe(struct platform_device *pdev)
}
}
+ if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
+ mtx->addr = 0L;
+ else
+ mtx->addr = addr.start;
+
+ if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
+ dev_info(dev, "cmdq subsys id has not been set\n");
+ mtx->subsys_id = cmdq_reg.subsys;
+
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mtx->regs = devm_ioremap_resource(dev, regs);
if (IS_ERR(mtx->regs)) {
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 6fe4ffbde290..d08b98419dd9 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -11,11 +11,19 @@ struct device;
struct mtk_mutex;
struct mtk_mutex *mtk_mutex_get(struct device *dev);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id);
int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
+void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_enable(struct mtk_mutex *mutex);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_disable(struct mtk_mutex *mutex);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
void mtk_mutex_unprepare(struct mtk_mutex *mutex);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v6 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-08-19 7:09 [PATCH v6 0/5] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2021-08-19 7:09 ` [PATCH v6 1/5] soc: mediatek: mmsys: Add support for MDP Moudy Ho
2021-08-19 7:09 ` [PATCH v6 2/5] soc: mediatek: mutex: add " Moudy Ho
@ 2021-08-19 7:09 ` Moudy Ho
2021-08-19 12:49 ` Rob Herring
2021-08-19 7:09 ` [PATCH v6 4/5] dts: arm64: mt8183: Add Mediatek MDP3 nodes Moudy Ho
3 siblings, 1 reply; 8+ messages in thread
From: Moudy Ho @ 2021-08-19 7:09 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
This patch adds DT binding document for Media Data Path 3 (MDP3)
a unit in multimedia system used for scaling and color format convert.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
.../bindings/media/mediatek,mdp3-ccorr.yaml | 58 +++++
.../bindings/media/mediatek,mdp3-rdma.yaml | 241 ++++++++++++++++++
.../bindings/media/mediatek,mdp3-rsz.yaml | 66 +++++
.../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
.../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
5 files changed, 507 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
new file mode 100644
index 000000000000..205b91b55806
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-ccorr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 CCORR Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to do color correction with 3X3 matrix.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-ccorr
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ description: |
+ Physical base address and length of the function block
+ register space, the number aligns with the component
+ and its own subcomponent.
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ mdp3_ccorr: mdp3_ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp3-ccorr";
+ mediatek,mdp3-id = <0>;
+ reg = <0x1401c000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
+ };
+
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
new file mode 100644
index 000000000000..9565317990a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -0,0 +1,241 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to do read DMA.
+ RDMA0 is also used to be a controller node containing MMSYS,
+ MUTEX, GCE and SCP settings.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ # controller node
+ - mediatek,mt8183-mdp3
+ - enum:
+ - mediatek,mt8183-mdp3-rdma
+
+ - items:
+ - enum:
+ # read DMA
+ - mediatek,mt8183-mdp3-rdma
+
+ mediatek,scp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description: |
+ The node of system control processor (SCP), using
+ the remoteproc & rpmsg framework.
+ $ref: /schemas/remoteproc/mtk,scp.yaml
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ In MDP3, it can allocate multiple identical modules for
+ different data path selection or multi-pipeline execution.
+ This node is used to indicate the ID of each module.
+
+ mdp3-comps:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ items:
+ - enum:
+ # MDP direct-link input path selection, create a
+ # component for path connectedness of HW pipe control
+ - mediatek,mt8183-mdp3-dl1
+ - enum:
+ - mediatek,mt8183-mdp3-dl2
+ - enum:
+ # MDP direct-link output path selection, create a
+ # component for path connectedness of HW pipe control
+ - mediatek,mt8183-mdp3-path1
+ - enum:
+ - mediatek,mt8183-mdp3-path2
+ - enum:
+ # Input DMA of ISP PASS2 (DIP) module for raw image input
+ - mediatek,mt8183-mdp3-imgi
+ - enum:
+ # Output DMA of ISP PASS2 (DIP) module for YUV image output
+ - mediatek,mt8183-mdp3-exto
+
+ mdp3-comp-ids:
+ maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Pipeline ID of MDP direct-link or DIP.
+
+ reg:
+ description: |
+ Physical base address and length of the function block
+ register space, the number aligns with the component
+ and its own subcomponent.
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 6
+
+ iommus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ Should point to the respective IOMMU block with master
+ port as argument.
+ $ref: /schemas/iommu/mediatek,iommu.yaml
+
+ mediatek,mmsys:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description: |
+ The node of mux(multiplexer) controller for HW connections.
+
+ mediatek,mm-mutex:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description: |
+ The node of sof(start of frame) signal controller.
+
+ mediatek,mailbox-gce:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ The node of global command engine (GCE), used to read/write
+ registers with critical time limitation.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ mboxes:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ $ref: /schemas/mailbox/mailbox.txt
+
+ gce-subsys:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ mediatek,gce-events:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ In use event IDs list, all IDs are defined in
+ 'dt-bindings/gce/mt8183-gce.h'.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+if:
+ properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3
+ - enum:
+ - mediatek,mt8183-mdp3-rdma
+
+then:
+ required:
+ - mediatek,scp
+ - mediatek,mmsys
+ - mediatek,mm-mutex
+ - mediatek,gce-events
+ - mediatek,mailbox-gce
+ - mboxes
+ - gce-subsys
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - clocks
+ - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_rdma0: mdp3_rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp3",
+ "mediatek,mt8183-mdp3-rdma";
+ mediatek,scp = <&scp>;
+ mediatek,mdp3-id = <0>;
+ mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2",
+ "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2",
+ "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto";
+ mdp3-comp-ids = <0 1 0 1 0 1>;
+ reg = <0x14001000 0x1000>,
+ <0x14000000 0x1000>,
+ <0x14005000 0x1000>,
+ <0x14006000 0x1000>,
+ <0x15020000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
+ <&gce SUBSYS_1502XXXX 0 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>,
+ <&mmsys CLK_MM_MDP_DL_TXCK>,
+ <&mmsys CLK_MM_MDP_DL_RX>,
+ <&mmsys CLK_MM_IPU_DL_TXCK>,
+ <&mmsys CLK_MM_IPU_DL_RX>;
+ iommus = <&iommu>;
+ mediatek,mmsys = <&mmsys>;
+ mediatek,mm-mutex = <&mutex>;
+ mediatek,mailbox-gce = <&gce>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
+ gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+ <&gce 0x14010000 SUBSYS_1401XXXX>,
+ <&gce 0x14020000 SUBSYS_1402XXXX>,
+ <&gce 0x15020000 SUBSYS_1502XXXX>;
+ mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
+ <CMDQ_EVENT_MDP_RDMA0_EOF>,
+ <CMDQ_EVENT_MDP_RSZ0_SOF>,
+ <CMDQ_EVENT_MDP_RSZ1_SOF>,
+ <CMDQ_EVENT_MDP_TDSHP_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_EOF>,
+ <CMDQ_EVENT_MDP_WDMA0_SOF>,
+ <CMDQ_EVENT_MDP_WDMA0_EOF>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+ <CMDQ_EVENT_WPE_A_DONE>,
+ <CMDQ_EVENT_SPE_B_DONE>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
new file mode 100644
index 000000000000..218f035ad406
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 Resizer Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to do frame resizing.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-rsz
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ description: |
+ Physical base address and length of the function block
+ register space, the number aligns with the component
+ and its own subcomponent.
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ mdp3_rsz0: mdp3_rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <0>;
+ reg = <0x14003000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp3_rsz1: mdp3_rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <1>;
+ reg = <0x14004000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
+
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
new file mode 100644
index 000000000000..93e6f331ada8
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-wdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to write DMA.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-wdma
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ description: |
+ Physical base address and length of the function block
+ register space, the number aligns with the component
+ and its own subcomponent.
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ iommus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ Should point to the respective IOMMU block with master
+ port as argument.
+ $ref: /schemas/iommu/mediatek,iommu.yaml
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_wdma: mdp3_wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp3-wdma";
+ mediatek,mdp3-id = <0>;
+ reg = <0x14006000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
new file mode 100644
index 000000000000..2993da04c562
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-wrot
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ description: |
+ Physical base address and length of the function block
+ register space, the number aligns with the component
+ and its own subcomponent.
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ iommus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ Should point to the respective IOMMU block with master
+ port as argument.
+ $ref: /schemas/iommu/mediatek,iommu.yaml
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_wrot0: mdp3_wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ mediatek,mdp3-id = <0>;
+ reg = <0x14005000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu>;
+ };
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v6 4/5] dts: arm64: mt8183: Add Mediatek MDP3 nodes
2021-08-19 7:09 [PATCH v6 0/5] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
` (2 preceding siblings ...)
2021-08-19 7:09 ` [PATCH v6 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings Moudy Ho
@ 2021-08-19 7:09 ` Moudy Ho
2021-08-24 5:02 ` CK Hu
3 siblings, 1 reply; 8+ messages in thread
From: Moudy Ho @ 2021-08-19 7:09 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
Add device nodes for Media Data Path 3 (MDP3) modules.
Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 110 +++++++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index f90df6439c08..7cb1fcfeefb6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1232,6 +1232,108 @@
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
+ mdp3_rdma0: mdp3_rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp3",
+ "mediatek,mt8183-mdp3-rdma";
+ mediatek,scp = <&scp>;
+ mediatek,mdp3-id = <0>;
+ mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2",
+ "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2",
+ "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto";
+ mdp3-comp-ids = <0 1 0 1 0 1>;
+ reg = <0 0x14001000 0 0x1000>,
+ <0 0x14000000 0 0x1000>,
+ <0 0x14005000 0 0x1000>,
+ <0 0x14006000 0 0x1000>,
+ <0 0x15020000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
+ <&gce SUBSYS_1502XXXX 0 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>,
+ <&mmsys CLK_MM_MDP_DL_TXCK>,
+ <&mmsys CLK_MM_MDP_DL_RX>,
+ <&mmsys CLK_MM_IPU_DL_TXCK>,
+ <&mmsys CLK_MM_IPU_DL_RX>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mediatek,mmsys = <&mmsys>;
+ mediatek,mm-mutex = <&mutex>;
+ mediatek,mailbox-gce = <&gce>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
+ gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+ <&gce 0x14010000 SUBSYS_1401XXXX>,
+ <&gce 0x14020000 SUBSYS_1402XXXX>,
+ <&gce 0x15020000 SUBSYS_1502XXXX>;
+ mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
+ <CMDQ_EVENT_MDP_RDMA0_EOF>,
+ <CMDQ_EVENT_MDP_RSZ0_SOF>,
+ <CMDQ_EVENT_MDP_RSZ1_SOF>,
+ <CMDQ_EVENT_MDP_TDSHP_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_EOF>,
+ <CMDQ_EVENT_MDP_WDMA0_SOF>,
+ <CMDQ_EVENT_MDP_WDMA0_EOF>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+ <CMDQ_EVENT_WPE_A_DONE>,
+ <CMDQ_EVENT_SPE_B_DONE>;
+ };
+
+ mdp3_rsz0: mdp3_rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp3_rsz1: mdp3_rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
+
+ mdp3_wrot0: mdp3_wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14005000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ };
+
+ mdp3_wdma: mdp3_wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp3-wdma";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14006000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+ };
+
ovl0: ovl@14008000 {
compatible = "mediatek,mt8183-disp-ovl";
reg = <0 0x14008000 0 0x1000>;
@@ -1378,6 +1480,14 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
};
+ mdp3_ccorr: mdp3_ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp3-ccorr";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x1401c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
+ };
+
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v6 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-08-19 7:09 ` [PATCH v6 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings Moudy Ho
@ 2021-08-19 12:49 ` Rob Herring
2021-08-23 2:32 ` moudy.ho
0 siblings, 1 reply; 8+ messages in thread
From: Rob Herring @ 2021-08-19 12:49 UTC (permalink / raw)
To: Moudy Ho
Cc: Mauro Carvalho Chehab, devicetree, Hans Verkuil, acourbot,
pihsun, daoyuan huang, Rob Landley, drinkcat, Maoguang Meng,
sj.huang, menghui.lin, tfiga, Ping-Hsun Wu, hsinyi, Rob Herring,
Laurent Pinchart, randy.wu, srv_heupstream, Jernej Skrabec,
linux-mediatek, ben.lok, Geert Uytterhoeven, Matthias Brugger,
linux-kernel, linux-media, linux-arm-kernel
On Thu, 19 Aug 2021 15:09:52 +0800, Moudy Ho wrote:
> This patch adds DT binding document for Media Data Path 3 (MDP3)
> a unit in multimedia system used for scaling and color format convert.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> .../bindings/media/mediatek,mdp3-ccorr.yaml | 58 +++++
> .../bindings/media/mediatek,mdp3-rdma.yaml | 241 ++++++++++++++++++
> .../bindings/media/mediatek,mdp3-rsz.yaml | 66 +++++
> .../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
> .../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
> 5 files changed, 507 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
make[1]: *** Deleting file 'Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.example.dts'
Traceback (most recent call last):
File "/usr/local/bin/dt-extract-example", line 45, in <module>
binding = yaml.load(open(args.yamlfile, encoding='utf-8').read())
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 434, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 120, in get_single_data
node = self.composer.get_single_node()
File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node
File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 773, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 848, in _ruamel_yaml.CParser._compose_sequence_node
File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event
ruamel.yaml.scanner.ScannerError: while scanning a block scalar
in "<unicode string>", line 171, column 5
found a tab character where an indentation space is expected
in "<unicode string>", line 183, column 1
make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
./Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml: while scanning a block scalar
in "<unicode string>", line 171, column 5
found a tab character where an indentation space is expected
in "<unicode string>", line 183, column 1
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml: ignoring, error parsing file
warning: no schema found in file: ./Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
make: *** [Makefile:1419: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1518477
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-08-19 12:49 ` Rob Herring
@ 2021-08-23 2:32 ` moudy.ho
0 siblings, 0 replies; 8+ messages in thread
From: moudy.ho @ 2021-08-23 2:32 UTC (permalink / raw)
To: Rob Herring
Cc: Mauro Carvalho Chehab, devicetree, Hans Verkuil, acourbot,
pihsun, daoyuan huang, Rob Landley, drinkcat, Maoguang Meng,
sj.huang, menghui.lin, tfiga, Ping-Hsun Wu, hsinyi, Rob Herring,
Laurent Pinchart, randy.wu, srv_heupstream, Jernej Skrabec,
linux-mediatek, ben.lok, Geert Uytterhoeven, Matthias Brugger,
linux-kernel, linux-media, linux-arm-kernel
On Thu, 2021-08-19 at 07:49 -0500, Rob Herring wrote:
> On Thu, 19 Aug 2021 15:09:52 +0800, Moudy Ho wrote:
> > This patch adds DT binding document for Media Data Path 3 (MDP3)
> > a unit in multimedia system used for scaling and color format
> > convert.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> > .../bindings/media/mediatek,mdp3-ccorr.yaml | 58 +++++
> > .../bindings/media/mediatek,mdp3-rdma.yaml | 241
> > ++++++++++++++++++
> > .../bindings/media/mediatek,mdp3-rsz.yaml | 66 +++++
> > .../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
> > .../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
> > 5 files changed, 507 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> >
Sorry for missing a space on line:183 of the file "mediatek,mdp3-
rdma.yaml " caused an alignment error that make "dt_binding_check"
fail.
It will be fixed in the further.
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m
> dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> make[1]: *** Deleting file
> 'Documentation/devicetree/bindings/media/mediatek,mdp3-
> rdma.example.dts'
> Traceback (most recent call last):
> File "/usr/local/bin/dt-extract-example", line 45, in <module>
> binding = yaml.load(open(args.yamlfile, encoding='utf-8').read())
> File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py",
> line 434, in load
> return constructor.get_single_data()
> File "/usr/local/lib/python3.8/dist-
> packages/ruamel/yaml/constructor.py", line 120, in get_single_data
> node = self.composer.get_single_node()
> File "_ruamel_yaml.pyx", line 706, in
> _ruamel_yaml.CParser.get_single_node
> File "_ruamel_yaml.pyx", line 724, in
> _ruamel_yaml.CParser._compose_document
> File "_ruamel_yaml.pyx", line 775, in
> _ruamel_yaml.CParser._compose_node
> File "_ruamel_yaml.pyx", line 889, in
> _ruamel_yaml.CParser._compose_mapping_node
> File "_ruamel_yaml.pyx", line 773, in
> _ruamel_yaml.CParser._compose_node
> File "_ruamel_yaml.pyx", line 848, in
> _ruamel_yaml.CParser._compose_sequence_node
> File "_ruamel_yaml.pyx", line 904, in
> _ruamel_yaml.CParser._parse_next_event
> ruamel.yaml.scanner.ScannerError: while scanning a block scalar
> in "<unicode string>", line 171, column 5
> found a tab character where an indentation space is expected
> in "<unicode string>", line 183, column 1
> make[1]: *** [Documentation/devicetree/bindings/Makefile:20:
> Documentation/devicetree/bindings/media/mediatek,mdp3-
> rdma.example.dts] Error 1
> make[1]: *** Waiting for unfinished jobs....
> ./Documentation/devicetree/bindings/media/mediatek,mdp3-
> rdma.yaml: while scanning a block scalar
> in "<unicode string>", line 171, column 5
> found a tab character where an indentation space is expected
> in "<unicode string>", line 183, column 1
> /builds/robherring/linux-dt-
> review/Documentation/devicetree/bindings/media/mediatek,mdp3-
> rdma.yaml: ignoring, error parsing file
> warning: no schema found in file:
> ./Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> make: *** [Makefile:1419: dt_binding_check] Error 2
>
> doc reference errors (make refcheckdocs):
>
> See
> https://urldefense.com/v3/__https://patchwork.ozlabs.org/patch/1518477__;!!CTRNKA9wMg0ARbw!2av75m5eJ2hSjFAgkXmPi-gQOv7ITc4RcVm1365xi_QcwQlFdg7oYQsw4pZf2ft_$
>
>
> This check can fail if there are any dependencies. The base for a
> patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up
> to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 4/5] dts: arm64: mt8183: Add Mediatek MDP3 nodes
2021-08-19 7:09 ` [PATCH v6 4/5] dts: arm64: mt8183: Add Mediatek MDP3 nodes Moudy Ho
@ 2021-08-24 5:02 ` CK Hu
0 siblings, 0 replies; 8+ messages in thread
From: CK Hu @ 2021-08-24 5:02 UTC (permalink / raw)
To: Moudy Ho
Cc: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, tfiga, drinkcat, acourbot, pihsun, menghui.lin,
sj.huang, ben.lok, randy.wu, srv_heupstream, hsinyi
Hi, Moudy:
On Thu, 2021-08-19 at 15:09 +0800, Moudy Ho wrote:
> Add device nodes for Media Data Path 3 (MDP3) modules.
>
> Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 110 +++++++++++++++++++++++
> 1 file changed, 110 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index f90df6439c08..7cb1fcfeefb6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -1232,6 +1232,108 @@
> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> };
>
> + mdp3_rdma0: mdp3_rdma0@14001000 {
> + compatible = "mediatek,mt8183-mdp3",
> + "mediatek,mt8183-mdp3-rdma";
> + mediatek,scp = <&scp>;
> + mediatek,mdp3-id = <0>;
> + mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2",
> + "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2",
> + "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto";
> + mdp3-comp-ids = <0 1 0 1 0 1>;
> + reg = <0 0x14001000 0 0x1000>,
> + <0 0x14000000 0 0x1000>,
> + <0 0x14005000 0 0x1000>,
> + <0 0x14006000 0 0x1000>,
> + <0 0x15020000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
> + <&gce SUBSYS_1400XXXX 0 0x1000>,
> + <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
> + <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
> + <&gce SUBSYS_1502XXXX 0 0x1000>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> + <&mmsys CLK_MM_MDP_RSZ1>,
> + <&mmsys CLK_MM_MDP_DL_TXCK>,
> + <&mmsys CLK_MM_MDP_DL_RX>,
> + <&mmsys CLK_MM_IPU_DL_TXCK>,
> + <&mmsys CLK_MM_IPU_DL_RX>;
> + iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> + mediatek,mmsys = <&mmsys>;
> + mediatek,mm-mutex = <&mutex>;
> + mediatek,mailbox-gce = <&gce>;
> + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
> + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
> + <&gce 0x14010000 SUBSYS_1401XXXX>,
> + <&gce 0x14020000 SUBSYS_1402XXXX>,
> + <&gce 0x15020000 SUBSYS_1502XXXX>;
> + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
> + <CMDQ_EVENT_MDP_RDMA0_EOF>,
> + <CMDQ_EVENT_MDP_RSZ0_SOF>,
CMDQ_EVENT_MDP_RSZ0_SOF is sent from rsz0 to gce, so move this event to
rsz0.
Regards,
CK
> + <CMDQ_EVENT_MDP_RSZ1_SOF>,
> + <CMDQ_EVENT_MDP_TDSHP_SOF>,
> + <CMDQ_EVENT_MDP_WROT0_SOF>,
> + <CMDQ_EVENT_MDP_WROT0_EOF>,
> + <CMDQ_EVENT_MDP_WDMA0_SOF>,
> + <CMDQ_EVENT_MDP_WDMA0_EOF>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
> + <CMDQ_EVENT_WPE_A_DONE>,
> + <CMDQ_EVENT_SPE_B_DONE>;
> + };
> +
> + mdp3_rsz0: mdp3_rsz0@14003000 {
> + compatible = "mediatek,mt8183-mdp3-rsz";
> + mediatek,mdp3-id = <0>;
> + reg = <0 0x14003000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> + };
> +
> + mdp3_rsz1: mdp3_rsz1@14004000 {
> + compatible = "mediatek,mt8183-mdp3-rsz";
> + mediatek,mdp3-id = <1>;
> + reg = <0 0x14004000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> + };
> +
> + mdp3_wrot0: mdp3_wrot0@14005000 {
> + compatible = "mediatek,mt8183-mdp3-wrot";
> + mediatek,mdp3-id = <0>;
> + reg = <0 0x14005000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_WROT0>;
> + iommus = <&iommu M4U_PORT_MDP_WROT0>;
> + };
> +
> + mdp3_wdma: mdp3_wdma@14006000 {
> + compatible = "mediatek,mt8183-mdp3-wdma";
> + mediatek,mdp3-id = <0>;
> + reg = <0 0x14006000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_WDMA0>;
> + iommus = <&iommu M4U_PORT_MDP_WDMA0>;
> + };
> +
> ovl0: ovl@14008000 {
> compatible = "mediatek,mt8183-disp-ovl";
> reg = <0 0x14008000 0 0x1000>;
> @@ -1378,6 +1480,14 @@
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> };
>
> + mdp3_ccorr: mdp3_ccorr@1401c000 {
> + compatible = "mediatek,mt8183-mdp3-ccorr";
> + mediatek,mdp3-id = <0>;
> + reg = <0 0x1401c000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_CCORR>;
> + };
> +
> imgsys: syscon@15020000 {
> compatible = "mediatek,mt8183-imgsys", "syscon";
> reg = <0 0x15020000 0 0x1000>;
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-08-24 5:04 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-19 7:09 [PATCH v6 0/5] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2021-08-19 7:09 ` [PATCH v6 1/5] soc: mediatek: mmsys: Add support for MDP Moudy Ho
2021-08-19 7:09 ` [PATCH v6 2/5] soc: mediatek: mutex: add " Moudy Ho
2021-08-19 7:09 ` [PATCH v6 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings Moudy Ho
2021-08-19 12:49 ` Rob Herring
2021-08-23 2:32 ` moudy.ho
2021-08-19 7:09 ` [PATCH v6 4/5] dts: arm64: mt8183: Add Mediatek MDP3 nodes Moudy Ho
2021-08-24 5:02 ` CK Hu
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