* [PATCH v8 0/7] media: mediatek: support mdp3 on mt8183 platform
@ 2021-10-15 12:38 Moudy Ho
2021-10-15 12:38 ` [PATCH v8 1/7] soc: mediatek: mmsys: add support for MDP Moudy Ho
` (6 more replies)
0 siblings, 7 replies; 16+ messages in thread
From: Moudy Ho @ 2021-10-15 12:38 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
Change since v7:
- Rebase on v5.15-rc6
- Revise several V4L2 M2M settings to pass v4l2-compliance test
- Integrate those same component dt-binding documents of DRM and MDP, and move them under the MMSYS domain
- Split MMSYS and MUTEX into two different files according to their functional properties
Changes since v6:
- Refactor GCE event to corresponding node.
- Fix dt_binding_check fail.
- Fix compilation errors.
Changes since v5:
- Rebase on v5.14-rc6.
- Move MMSYS/Mutex settings to corresponding driver.
- Revise the software license description and copyright.
- Remove unnecessary enum. or definitions.
- Optimize platform/chip definition conditions.
- Use general printing functions instead of MDP3 private ones.
- Fix compile warning.
Changes since v4:
- Rebase on v5.13-rc1.
- Remove the CMDQ flush flow to match the CMDQ API change.
- Integrate four of MDP's direct-link subcomponents into MDP controller node
from syscon node to avoid illegal clock usage.
- Rewrite dt-binding in a JSON compatible subset of YAML
- Fix a bit of macro argument precedence.
Changes since v3:
- Rebase on v5.9-rc1.
- modify code for review comment from Rob Herring, cancel multiple nodes using
same register base situation.
- control IOMMU port through pm runtime get/put to DMA components' device.
- SCP(VPU) driver revision.
- stop queuing jobs(remove flush_workqueue()) after mdp_m2m_release().
- add computation of plane address with data_offset.
- fix scale ratio check issue.
- add default v4l2_format setting.
Changes since v2:
- modify code for review comment from Tomasz Figa & Alexandre Courbot
- review comment from Rob Herring will offer code revision in v4, due to
it's related to device node modification, will need to modify code
architecture
Changes since v1:
- modify code for CMDQ v3 API support
- EC ipi cmd migration
- fix compliance test fail item (m2m cmd with -f) due to there is two problem in runing all format(-f) cmd:
1. out of memory before test complete
Due to capture buffer mmap (refcount + 1) after reqbuf but seems
no corresponding munmap called before device close.
There are total 12XX items(formats) in format test and each format
alloc 8 capture/output buffers.
2. unceasingly captureBufs() (randomly)
Seems the break statement didn't catch the count == 0 situation:
In v4l2-test-buffers.cpp, function: captureBufs()
...
count--;
if (!node->is_m2m && !count)
break;
Log is as attachment
I will paste the test result with problem part in another e-mail
Hi,
This is the first version of RFC patch for Media Data Path 3 (MDP3),
MDP3 is used for scaling and color format conversion.
support using GCE to write register in critical time limitation.
support V4L2 m2m device control.
Moudy Ho (7):
soc: mediatek: mmsys: add support for MDP
soc: mediatek: mmsys: add support for ISP control
soc: mediatek: mutex: add support for MDP
soc: mediatek: mutex: add functions that operate registers by CMDQ
dt-binding: mt8183: add Mediatek MDP3 dt-bindings
dts: arm64: mt8183: add Mediatek MDP3 nodes
media: platform: mtk-mdp3: add Mediatek MDP3 driver
.../bindings/arm/mediatek/mediatek,ccorr.yaml | 59 +
.../bindings/arm/mediatek/mediatek,rdma.yaml | 211 +++
.../bindings/arm/mediatek/mediatek,wdma.yaml | 70 +
.../bindings/media/mediatek,mdp3-rsz.yaml | 68 +
.../bindings/media/mediatek,mdp3-wrot.yaml | 70 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 112 +-
drivers/media/platform/Kconfig | 19 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/mtk-mdp3/Makefile | 6 +
.../media/platform/mtk-mdp3/mdp_reg_ccorr.h | 19 +
drivers/media/platform/mtk-mdp3/mdp_reg_isp.h | 27 +
.../media/platform/mtk-mdp3/mdp_reg_rdma.h | 65 +
drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 39 +
.../media/platform/mtk-mdp3/mdp_reg_wdma.h | 47 +
.../media/platform/mtk-mdp3/mdp_reg_wrot.h | 55 +
drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 280 ++++
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 514 +++++++
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 46 +
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 1307 +++++++++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 147 ++
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 340 +++++
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 76 +
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 789 ++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.h | 49 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 737 ++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 373 +++++
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 313 ++++
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 78 +
drivers/soc/mediatek/Kconfig | 1 +
drivers/soc/mediatek/mt8183-mmsys.h | 235 +++
drivers/soc/mediatek/mtk-mmsys.c | 160 ++
drivers/soc/mediatek/mtk-mmsys.h | 3 +
drivers/soc/mediatek/mtk-mutex.c | 96 +-
include/linux/soc/mediatek/mtk-mmsys.h | 81 +
include/linux/soc/mediatek/mtk-mutex.h | 8 +
35 files changed, 6500 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,wdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
create mode 100644 drivers/media/platform/mtk-mdp3/Makefile
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ccorr.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_isp.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wdma.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
--
2.18.0
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v8 1/7] soc: mediatek: mmsys: add support for MDP
2021-10-15 12:38 [PATCH v8 0/7] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
@ 2021-10-15 12:38 ` Moudy Ho
2021-10-18 13:50 ` AngeloGioacchino Del Regno
2021-10-15 12:38 ` [PATCH v8 2/7] soc: mediatek: mmsys: add support for ISP control Moudy Ho
` (5 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Moudy Ho @ 2021-10-15 12:38 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
For the purpose of module independence, related settings should be moved
from MDP to the corresponding driver.
This patch adds more 8183 MDP settings and interface. and MDP
related settings must be set via CMDQ to avoid frame unsynchronized.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
drivers/soc/mediatek/Kconfig | 1 +
drivers/soc/mediatek/mt8183-mmsys.h | 219 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 52 ++++++
drivers/soc/mediatek/mtk-mmsys.h | 2 +
include/linux/soc/mediatek/mtk-mmsys.h | 56 +++++++
5 files changed, 330 insertions(+)
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index fdd8bc08569e..172bc7828aca 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -69,6 +69,7 @@ config MTK_MMSYS
bool "MediaTek MMSYS Support"
default ARCH_MEDIATEK
depends on HAS_IOMEM
+ select MTK_CMDQ
help
Say yes here to add support for the MediaTek Multimedia
Subsystem (MMSYS).
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 9dee485807c9..663f196fc4e7 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -12,6 +12,25 @@
#define MT8183_DISP_DPI0_SEL_IN 0xf30
#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
+#define MT8183_MDP_ISP_MOUT_EN 0xf80
+#define MT8183_MDP_RDMA0_MOUT_EN 0xf84
+#define MT8183_MDP_PRZ0_MOUT_EN 0xf8c
+#define MT8183_MDP_PRZ1_MOUT_EN 0xf90
+#define MT8183_MDP_COLOR_MOUT_EN 0xf94
+#define MT8183_MDP_IPU_MOUT_EN 0xf98
+#define MT8183_MDP_PATH0_SOUT_SEL 0xfa8
+#define MT8183_MDP_PATH1_SOUT_SEL 0xfac
+#define MT8183_MDP_PRZ0_SEL_IN 0xfc0
+#define MT8183_MDP_PRZ1_SEL_IN 0xfc4
+#define MT8183_MDP_TDSHP_SEL_IN 0xfc8
+#define MT8183_MDP_WROT0_SEL_IN 0xfd0
+#define MT8183_MDP_WDMA_SEL_IN 0xfd4
+#define MT8183_MDP_PATH0_SEL_IN 0xfe0
+#define MT8183_MDP_PATH1_SEL_IN 0xfe4
+#define MT8183_MDP_AAL_MOUT_EN 0xfe8
+#define MT8183_MDP_AAL_SEL_IN 0xfec
+#define MT8183_MDP_CCORR_SEL_IN 0xff0
+#define MT8183_MDP_CCORR_SOUT_SEL 0xff4
#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
@@ -24,6 +43,55 @@
#define MT8183_DPI0_SEL_IN_RDMA1 0x2
#define MT8183_RDMA0_SOUT_COLOR0 0x1
#define MT8183_RDMA1_SOUT_DSI0 0x1
+#define MT8183_MDP_ISP_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_ISP_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_ISP_MOUT_EN_AAL0 BIT(2)
+#define MT8183_MDP_IPU_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_IPU_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_IPU_MOUT_EN_AAL0 BIT(2)
+#define MT8183_MDP_RDMA0_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_RDMA0_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT BIT(2)
+#define MT8183_MDP_RDMA0_MOUT_EN_AAL0 BIT(3)
+#define MT8183_MDP_AAL_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_AAL_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_AAL_MOUT_EN_RSZ0 BIT(2)
+#define MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_PRZ0_MOUT_EN_TDSHP0 BIT(1)
+#define MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_PRZ1_MOUT_EN_TDSHP0 BIT(1)
+#define MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT BIT(2)
+#define MT8183_MDP_PRZ1_MOUT_EN_COLOR0 BIT(4)
+#define MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT BIT(1)
+#define MT8183_MDP_AAL_SEL_IN_CAMIN 0
+#define MT8183_MDP_AAL_SEL_IN_RDMA0 1
+#define MT8183_MDP_AAL_SEL_IN_CAMIN2 2
+#define MT8183_MDP_AAL_SEL_IN_CCORR0 3
+#define MT8183_MDP_CCORR_SEL_IN_CAMIN 0
+#define MT8183_MDP_CCORR_SEL_IN_RDMA0 1
+#define MT8183_MDP_CCORR_SEL_IN_CAMIN2 3
+#define MT8183_MDP_CCORR_SEL_IN_AAL0 4
+#define MT8183_MDP_PRZ0_SEL_IN_AAL0 0
+#define MT8183_MDP_PRZ0_SEL_IN_CCORR0 1
+#define MT8183_MDP_PRZ1_SEL_IN_CAMIN 0
+#define MT8183_MDP_PRZ1_SEL_IN_RDMA0 1
+#define MT8183_MDP_PRZ1_SEL_IN_CAMIN2 4
+#define MT8183_MDP_PRZ1_SEL_IN_AAL0 5
+#define MT8183_MDP_TDSHP_SEL_IN_RSZ0 0
+#define MT8183_MDP_TDSHP_SEL_IN_RSZ1 1
+#define MT8183_MDP_PATH0_SEL_IN_RSZ0 0
+#define MT8183_MDP_PATH0_SEL_IN_RSZ1 1
+#define MT8183_MDP_PATH0_SEL_IN_COLOR0 2
+#define MT8183_MDP_PATH0_SEL_IN_RDMA0 3
+#define MT8183_MDP_PATH1_SEL_IN_RSZ1 0
+#define MT8183_MDP_PATH1_SEL_IN_COLOR0 1
+#define MT8183_MDP_WROT0_SEL_IN_PATH0_OUT 0
+#define MT8183_MDP_WDMA_SEL_IN_PATH1_OUT 0
+#define MT8183_MDP_CCORR_SOUT_SEL_AAL0 0
+#define MT8183_MDP_CCORR_SOUT_SEL_RSZ0 1
+#define MT8183_MDP_PATH0_SOUT_SEL_WROT0 0
+#define MT8183_MDP_PATH1_SOUT_SEL_WDMA 0
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
{
@@ -57,5 +125,156 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
}
};
+static const struct mtk_mmsys_routes mmsys_mt8183_mdp_routing_table[] = {
+ {
+ MDP_COMP_CAMIN, MDP_COMP_CCORR0,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_RSZ1,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_AAL0,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_AAL0,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_CCORR0,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_RSZ1,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_AAL0,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_CCORR0,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ1,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ0,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ0
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PRZ0_MOUT_EN, MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
+ MT8183_MDP_PRZ0_MOUT_EN, MT8183_MDP_PRZ0_MOUT_EN_TDSHP0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_TDSHP0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_COLOR0,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_COLOR0
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_COLOR_MOUT_EN, MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_COLOR_MOUT_EN, MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_AAL0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ0,
+ MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_AAL0
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_RSZ0,
+ MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_AAL0
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
+ MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
+ MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_COLOR0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_COLOR0
+ }, {
+ MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
+ MT8183_MDP_WROT0_SEL_IN, MT8183_MDP_WROT0_SEL_IN_PATH0_OUT
+ }, {
+ MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
+ MT8183_MDP_WDMA_SEL_IN, MT8183_MDP_WDMA_SEL_IN_PATH1_OUT
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_AAL0,
+ MT8183_MDP_CCORR_SOUT_SEL, MT8183_MDP_CCORR_SOUT_SEL_AAL0
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_RSZ0,
+ MT8183_MDP_CCORR_SOUT_SEL, MT8183_MDP_CCORR_SOUT_SEL_RSZ0
+ }, {
+ MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
+ MT8183_MDP_PATH0_SOUT_SEL, MT8183_MDP_PATH0_SOUT_SEL_WROT0
+ }, {
+ MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
+ MT8183_MDP_PATH1_SOUT_SEL, MT8183_MDP_PATH1_SOUT_SEL_WDMA
+ }
+};
+
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index a78e88f27b62..31fec490617e 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -7,8 +7,10 @@
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
@@ -51,6 +53,8 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+ .mdp_routes = mmsys_mt8183_mdp_routing_table,
+ .mdp_num_routes = ARRAY_SIZE(mmsys_mt8183_mdp_routing_table),
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
@@ -62,6 +66,8 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
+ phys_addr_t addr;
+ u8 subsys_id;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -101,12 +107,49 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_mdp_connect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
+ int i;
+
+ WARN_ON(!routes);
+ WARN_ON(mmsys->subsys_id == 0);
+ for (i = 0; i < mmsys->data->mdp_num_routes; i++)
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
+ mmsys->addr + routes[i].addr,
+ routes[i].val, 0xFFFFFFFF);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_connect);
+
+void mtk_mmsys_mdp_disconnect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
+ int i;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ for (i = 0; i < mmsys->data->mdp_num_routes; i++)
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
+ mmsys->addr + routes[i].addr,
+ 0, 0xFFFFFFFF);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_disconnect);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct platform_device *clks;
struct platform_device *drm;
struct mtk_mmsys *mmsys;
+ struct resource res;
+ struct cmdq_client_reg cmdq_reg;
int ret;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -120,6 +163,15 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
+ if (of_address_to_resource(dev->of_node, 0, &res) < 0)
+ mmsys->addr = 0L;
+ else
+ mmsys->addr = res.start;
+
+ if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
+ dev_info(dev, "cmdq subsys id has not been set\n");
+ mmsys->subsys_id = cmdq_reg.subsys;
+
mmsys->data = of_device_get_match_data(&pdev->dev);
platform_set_drvdata(pdev, mmsys);
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 9e2b81bd38db..a823eb5bf94f 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -90,6 +90,8 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const struct mtk_mmsys_routes *mdp_routes;
+ const unsigned int mdp_num_routes;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..d1afeabca97d 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -7,8 +7,14 @@
#define __MTK_MMSYS_H
enum mtk_ddp_comp_id;
+enum mtk_mdp_comp_id;
struct device;
+struct mmsys_cmdq_cmd {
+ struct cmdq_pkt *pkt;
+ s32 *event;
+};
+
enum mtk_ddp_comp_id {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_AAL1,
@@ -42,6 +48,46 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mdp_comp_id {
+ MDP_COMP_NONE = -1, /* Invalid engine */
+
+ /* ISP */
+ MDP_COMP_WPEI = 0,
+ MDP_COMP_WPEO, /* 1 */
+ MDP_COMP_WPEI2, /* 2 */
+ MDP_COMP_WPEO2, /* 3 */
+ MDP_COMP_ISP_IMGI, /* 4 */
+ MDP_COMP_ISP_IMGO, /* 5 */
+ MDP_COMP_ISP_IMG2O, /* 6 */
+
+ /* IPU */
+ MDP_COMP_IPUI, /* 7 */
+ MDP_COMP_IPUO, /* 8 */
+
+ /* MDP */
+ MDP_COMP_CAMIN, /* 9 */
+ MDP_COMP_CAMIN2, /* 10 */
+ MDP_COMP_RDMA0, /* 11 */
+ MDP_COMP_AAL0, /* 12 */
+ MDP_COMP_CCORR0, /* 13 */
+ MDP_COMP_RSZ0, /* 14 */
+ MDP_COMP_RSZ1, /* 15 */
+ MDP_COMP_TDSHP0, /* 16 */
+ MDP_COMP_COLOR0, /* 17 */
+ MDP_COMP_PATH0_SOUT, /* 18 */
+ MDP_COMP_PATH1_SOUT, /* 19 */
+ MDP_COMP_WROT0, /* 20 */
+ MDP_COMP_WDMA, /* 21 */
+
+ /* Dummy Engine */
+ MDP_COMP_RDMA1, /* 22 */
+ MDP_COMP_RSZ2, /* 23 */
+ MDP_COMP_TDSHP1, /* 24 */
+ MDP_COMP_WROT1, /* 25 */
+
+ MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -50,4 +96,14 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_mdp_connect(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next);
+
+void mtk_mmsys_mdp_disconnect(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v8 2/7] soc: mediatek: mmsys: add support for ISP control
2021-10-15 12:38 [PATCH v8 0/7] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2021-10-15 12:38 ` [PATCH v8 1/7] soc: mediatek: mmsys: add support for MDP Moudy Ho
@ 2021-10-15 12:38 ` Moudy Ho
2021-10-18 13:50 ` AngeloGioacchino Del Regno
2021-10-15 12:38 ` [PATCH v8 3/7] soc: mediatek: mutex: add support for MDP Moudy Ho
` (4 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Moudy Ho @ 2021-10-15 12:38 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
This patch adds 8183 ISP settings in MMSYS domain and interface.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
drivers/soc/mediatek/mt8183-mmsys.h | 16 ++++
drivers/soc/mediatek/mtk-mmsys.c | 108 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 25 ++++++
4 files changed, 150 insertions(+)
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 663f196fc4e7..c490cc1b1072 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -32,6 +32,13 @@
#define MT8183_MDP_CCORR_SEL_IN 0xff0
#define MT8183_MDP_CCORR_SOUT_SEL 0xff4
+#define MT8183_ISP_CTRL_MMSYS_SW0_RST_B 0x140
+#define MT8183_ISP_CTRL_MMSYS_SW1_RST_B 0x144
+#define MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD 0x934
+#define MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD 0x93C
+#define MT8183_ISP_CTRL_ISP_RELAY_CFG_WD 0x994
+#define MT8183_ISP_CTRL_IPU_RELAY_CFG_WD 0x9a0
+
#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
@@ -276,5 +283,14 @@ static const struct mtk_mmsys_routes mmsys_mt8183_mdp_routing_table[] = {
}
};
+static const unsigned int mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
+ [ISP_CTRL_MMSYS_SW0_RST_B] = MT8183_ISP_CTRL_MMSYS_SW0_RST_B,
+ [ISP_CTRL_MMSYS_SW1_RST_B] = MT8183_ISP_CTRL_MMSYS_SW1_RST_B,
+ [ISP_CTRL_MDP_ASYNC_CFG_WD] = MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD,
+ [ISP_CTRL_MDP_ASYNC_IPU_CFG_WD] = MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD,
+ [ISP_CTRL_ISP_RELAY_CFG_WD] = MT8183_ISP_CTRL_ISP_RELAY_CFG_WD,
+ [ISP_CTRL_IPU_RELAY_CFG_WD] = MT8183_ISP_CTRL_IPU_RELAY_CFG_WD,
+};
+
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 31fec490617e..f4b1d2fa41b4 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -55,6 +55,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
.mdp_routes = mmsys_mt8183_mdp_routing_table,
.mdp_num_routes = ARRAY_SIZE(mmsys_mt8183_mdp_routing_table),
+ .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
@@ -142,6 +143,113 @@ void mtk_mmsys_mdp_disconnect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_disconnect);
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ /* Direct link */
+ if (id == MDP_COMP_CAMIN) {
+ /* Reset MDP_DL_ASYNC_TX */
+ /* Bit 3: MDP_DL_ASYNC_TX / MDP_RELAY */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000008);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 3, 0x00000008);
+ }
+
+ /* Reset MDP_DL_ASYNC_RX */
+ /* Bit 10: MDP_DL_ASYNC_RX */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000400);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 10, 0x00000400);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0 << 31, 0x80000000);
+ }
+ }
+
+ if (id == MDP_COMP_CAMIN2) {
+ /* Reset MDP_DL_ASYNC2_TX */
+ /* Bit 4: MDP_DL_ASYNC2_TX / MDP_RELAY2 */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000010);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 4, 0x00000010);
+ }
+
+ /* Reset MDP_DL_ASYNC2_RX */
+ /* Bit 11: MDP_DL_ASYNC2_RX */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000800);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 11, 0x00000800);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0 << 31, 0x80000000);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id, u32 camin_w, u32 camin_h)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ /* Config for direct link */
+ if (id == MDP_COMP_CAMIN) {
+ if (isp_ctrl[ISP_CTRL_MDP_ASYNC_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MDP_ASYNC_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w, 0x3FFF3FFF);
+ }
+
+ if (isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w, 0x3FFF3FFF);
+ }
+ }
+ if (id == MDP_COMP_CAMIN2) {
+ if (isp_ctrl[ISP_CTRL_MDP_ASYNC_IPU_CFG_WD]) {
+ reg = mmsys->addr +
+ isp_ctrl[ISP_CTRL_MDP_ASYNC_IPU_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w, 0x3FFF3FFF);
+ }
+ if (isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w, 0x3FFF3FFF);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index a823eb5bf94f..fdfa3f0641ea 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
const struct mtk_mmsys_routes *mdp_routes;
const unsigned int mdp_num_routes;
+ const unsigned int *mdp_isp_ctrl;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index d1afeabca97d..4eb48d073d2a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -88,6 +88,24 @@ enum mtk_mdp_comp_id {
MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
};
+enum mtk_mdp_pipe_id {
+ MDP_PIPE_RDMA0,
+ MDP_PIPE_IMGI,
+ MDP_PIPE_WPEI,
+ MDP_PIPE_WPEI2,
+ MDP_PIPE_MAX
+};
+
+enum mtk_isp_ctrl {
+ ISP_CTRL_MMSYS_SW0_RST_B,
+ ISP_CTRL_MMSYS_SW1_RST_B,
+ ISP_CTRL_MDP_ASYNC_CFG_WD,
+ ISP_CTRL_MDP_ASYNC_IPU_CFG_WD,
+ ISP_CTRL_ISP_RELAY_CFG_WD,
+ ISP_CTRL_IPU_RELAY_CFG_WD,
+ ISP_CTRL_MAX
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -106,4 +124,11 @@ void mtk_mmsys_mdp_disconnect(struct device *dev,
enum mtk_mdp_comp_id cur,
enum mtk_mdp_comp_id next);
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id,
+ u32 camin_w, u32 camin_h);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v8 3/7] soc: mediatek: mutex: add support for MDP
2021-10-15 12:38 [PATCH v8 0/7] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2021-10-15 12:38 ` [PATCH v8 1/7] soc: mediatek: mmsys: add support for MDP Moudy Ho
2021-10-15 12:38 ` [PATCH v8 2/7] soc: mediatek: mmsys: add support for ISP control Moudy Ho
@ 2021-10-15 12:38 ` Moudy Ho
2021-10-18 13:50 ` AngeloGioacchino Del Regno
2021-10-15 12:38 ` [PATCH v8 4/7] soc: mediatek: mutex: add functions that operate registers by CMDQ Moudy Ho
` (3 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Moudy Ho @ 2021-10-15 12:38 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
For the purpose of module independence, related settings should be moved
from MDP to the corresponding driver.
This patch adds more 8183 MDP settings and interface.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 33 ++++++++++++++++++++++++++
include/linux/soc/mediatek/mtk-mutex.h | 2 ++
2 files changed, 35 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..adab4c9edc16 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -107,6 +107,10 @@
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8183_MUTEX_MDP_START 5
+#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
+#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
+
struct mtk_mutex {
int id;
bool claimed;
@@ -127,6 +131,9 @@ struct mtk_mutex_data {
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
+ const unsigned int *mutex_mdp_offset;
+ const unsigned int mutex_mdp_mod_mask;
+ const unsigned int mutex_mdp_sof_mask;
const bool no_clk;
};
@@ -238,6 +245,14 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
};
+/* indicate which mutex is used by each pipepline */
+static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
+ [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
+ [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
+ [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -272,6 +287,9 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.mutex_sof = mt8183_mutex_sof,
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
+ .mutex_mdp_offset = mt8183_mutex_mdp_offset,
+ .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
.no_clk = true,
};
@@ -290,6 +308,21 @@ struct mtk_mutex *mtk_mutex_get(struct device *dev)
}
EXPORT_SYMBOL_GPL(mtk_mutex_get);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id)
+{
+ struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
+ int i = mtx->data->mutex_mdp_offset[id];
+
+ if (!mtx->mutex[i].claimed) {
+ mtx->mutex[i].claimed = true;
+ return &mtx->mutex[i];
+ }
+
+ return ERR_PTR(-EBUSY);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
+
void mtk_mutex_put(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 6fe4ffbde290..099ddb025d79 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -11,6 +11,8 @@ struct device;
struct mtk_mutex;
struct mtk_mutex *mtk_mutex_get(struct device *dev);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id);
int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v8 4/7] soc: mediatek: mutex: add functions that operate registers by CMDQ
2021-10-15 12:38 [PATCH v8 0/7] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
` (2 preceding siblings ...)
2021-10-15 12:38 ` [PATCH v8 3/7] soc: mediatek: mutex: add support for MDP Moudy Ho
@ 2021-10-15 12:38 ` Moudy Ho
2021-10-18 13:50 ` AngeloGioacchino Del Regno
2021-10-15 12:38 ` [PATCH v8 5/7] dt-binding: mt8183: add Mediatek MDP3 dt-bindings Moudy Ho
` (2 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Moudy Ho @ 2021-10-15 12:38 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
Considering that some functions have timing requirements
in specific situation, this patch adds several interface that
operate registers by CMDQ.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 63 +++++++++++++++++++++++++-
include/linux/soc/mediatek/mtk-mutex.h | 6 +++
2 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index adab4c9edc16..874d4c60b844 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -7,10 +7,12 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include <linux/soc/mediatek/mtk-mutex.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#define MT2701_MUTEX0_MOD0 0x2c
#define MT2701_MUTEX0_SOF0 0x30
@@ -143,6 +145,8 @@ struct mtk_mutex_ctx {
void __iomem *regs;
struct mtk_mutex mutex[10];
const struct mtk_mutex_data *data;
+ phys_addr_t addr;
+ u8 subsys_id;
};
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -442,6 +446,25 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
}
EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
+void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+ unsigned int offset;
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
+ mod, mtx->data->mutex_mdp_mod_mask);
+
+ offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
+ 0, mtx->data->mutex_mdp_sof_mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
+
void mtk_mutex_enable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -453,6 +476,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_enable);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ 0x1, 0x00000001);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
+
void mtk_mutex_disable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -464,6 +501,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_disable);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ 0x0, 0x00000001);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
+
void mtk_mutex_acquire(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -491,7 +542,8 @@ static int mtk_mutex_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_mutex_ctx *mtx;
- struct resource *regs;
+ struct cmdq_client_reg cmdq_reg;
+ struct resource *regs, addr;
int i;
mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
@@ -512,6 +564,15 @@ static int mtk_mutex_probe(struct platform_device *pdev)
}
}
+ if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
+ mtx->addr = 0L;
+ else
+ mtx->addr = addr.start;
+
+ if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
+ dev_info(dev, "cmdq subsys id has not been set\n");
+ mtx->subsys_id = cmdq_reg.subsys;
+
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mtx->regs = devm_ioremap_resource(dev, regs);
if (IS_ERR(mtx->regs)) {
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 099ddb025d79..86c17c024d83 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -16,8 +16,14 @@ struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
+void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_enable(struct mtk_mutex *mutex);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_disable(struct mtk_mutex *mutex);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
void mtk_mutex_unprepare(struct mtk_mutex *mutex);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v8 5/7] dt-binding: mt8183: add Mediatek MDP3 dt-bindings
2021-10-15 12:38 [PATCH v8 0/7] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
` (3 preceding siblings ...)
2021-10-15 12:38 ` [PATCH v8 4/7] soc: mediatek: mutex: add functions that operate registers by CMDQ Moudy Ho
@ 2021-10-15 12:38 ` Moudy Ho
2021-10-15 21:45 ` Rob Herring
2021-10-16 14:18 ` Rob Herring
2021-10-15 12:38 ` [PATCH v8 6/7] dts: arm64: mt8183: add Mediatek MDP3 nodes Moudy Ho
[not found] ` <20211015123832.17914-8-moudy.ho@mediatek.com>
6 siblings, 2 replies; 16+ messages in thread
From: Moudy Ho @ 2021-10-15 12:38 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
This patch adds DT binding document for Media Data Path 3 (MDP3)
a unit in multimedia system used for scaling and color format convert.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
.../bindings/arm/mediatek/mediatek,ccorr.yaml | 59 +++++
.../bindings/arm/mediatek/mediatek,rdma.yaml | 211 ++++++++++++++++++
.../bindings/arm/mediatek/mediatek,wdma.yaml | 70 ++++++
.../bindings/media/mediatek,mdp3-rsz.yaml | 68 ++++++
.../bindings/media/mediatek,mdp3-wrot.yaml | 70 ++++++
5 files changed, 478 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,wdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml
new file mode 100644
index 000000000000..40ea7955efc6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,ccorr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek color correction
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ Mediatek color correction with 3X3 matrix.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-ccorr
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ There may be multiple blocks with the same function but
+ different addresses in MDP3.
+ In order to distinguish the connection with other blocks,
+ a unique ID is needed to dynamically use one or more identical
+ blocks to implement multiple pipelines.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ The register of client driver can be configured by gce with 4 arguments
+ defined in this property, such as phandle of gce, subsys id,
+ register offset and size.
+ Each GCE subsys id is mapping to a client defined in the header
+ include/dt-bindings/gce/<chip>-gce.h.
+
+ clocks:
+ minItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ mdp3_ccorr: mdp3_ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp3-ccorr";
+ mediatek,mdp3-id = <0>;
+ reg = <0x1401c000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml
new file mode 100644
index 000000000000..ad0e56923494
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml
@@ -0,0 +1,211 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Read Direct Memory Access
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ Mediatek Read Direct Memory Access(RDMA) component used to do read DMA.
+ It contains one line buffer to store the sufficient pixel data, and
+ must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+ The 1st RDMA is also used to be a controller node in Media Data Path 3(MDP3)
+ that containing MMSYS, MUTEX, GCE and SCP settings.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8183-mdp3
+ - const: mediatek,mt8183-mdp3-rdma
+ - items:
+ - const: mediatek,mt8183-mdp3-rdma
+
+ mediatek,scp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description: |
+ The node of system control processor (SCP), using
+ the remoteproc & rpmsg framework.
+ $ref: /schemas/remoteproc/mtk,scp.yaml
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ There may be multiple blocks with the same function but
+ different addresses in MDP3.
+ In order to distinguish the connection with other blocks,
+ a unique ID is needed to dynamically use one or more identical
+ blocks to implement multiple pipelines.
+
+ mdp3-comps:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ items:
+ - enum:
+ # MDP direct-link input path selection, create a
+ # component for path connectedness of HW pipe control
+ - mediatek,mt8183-mdp3-dl1
+ - enum:
+ - mediatek,mt8183-mdp3-dl2
+ - enum:
+ # MDP direct-link output path selection, create a
+ # component for path connectedness of HW pipe control
+ - mediatek,mt8183-mdp3-path1
+ - enum:
+ - mediatek,mt8183-mdp3-path2
+ - enum:
+ # Input DMA of ISP PASS2 (DIP) module for raw image input
+ - mediatek,mt8183-mdp3-imgi
+ - enum:
+ # Output DMA of ISP PASS2 (DIP) module for YUV image output
+ - mediatek,mt8183-mdp3-exto
+ description: |
+ MTK sub-system of direct-link or DIP
+
+ mdp3-comp-ids:
+ maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Pipeline ID of MDP sub-system.
+
+ reg:
+ minItems: 1
+ maxItems: 5
+ description: |
+ 1st: basic HW address
+ 2nd: mediatek,mt8183-mdp-dl1, mediatek,mt8183-mdp-dl2
+ 3rd: mediatek,mt8183-mdp-path1
+ 4th: mediatek,mt8183-mdp-path2
+ 5th: mediatek,mt8183-mdp3-imgi, mediatek,mt8183-mdp3-exto
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ The register of client driver can be configured by gce with 4 arguments
+ defined in this property, such as phandle of gce, subsys id,
+ register offset and size.
+ Each GCE subsys id is mapping to a client defined in the header
+ include/dt-bindings/gce/<chip>-gce.h.
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 6
+ description: |
+ 1st: RDMA0 clock
+ 2nd: RSZ1 clock
+ 3rd: direck-link TX clock in MDP side
+ 4th: direck-link RX clock in MDP side
+ 5th: direck-link TX clock in ISP side
+ 6th: direck-link RX clock in ISP side
+
+ iommus:
+ maxItems: 1
+
+ mediatek,mmsys:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description: |
+ The node of mux(multiplexer) controller for HW connections.
+
+ mediatek,mm-mutex:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description: |
+ The node of sof(start of frame) signal controller.
+
+ mediatek,mailbox-gce:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ The node of global command engine (GCE), used to read/write
+ registers with critical time limitation.
+
+ mboxes:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+ gce-subsys:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8183-mdp3
+
+then:
+ required:
+ - mediatek,scp
+ - mediatek,mmsys
+ - mediatek,mm-mutex
+ - mediatek,mailbox-gce
+ - mboxes
+ - gce-subsys
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - clocks
+ - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_rdma0: mdp3_rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp3",
+ "mediatek,mt8183-mdp3-rdma";
+ mediatek,scp = <&scp>;
+ mediatek,mdp3-id = <0>;
+ mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2",
+ "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2",
+ "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto";
+ mdp3-comp-ids = <0 1 0 1 0 1>;
+ reg = <0x14001000 0x1000>,
+ <0x14000000 0x1000>,
+ <0x14005000 0x1000>,
+ <0x14006000 0x1000>,
+ <0x15020000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
+ <&gce SUBSYS_1502XXXX 0 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>,
+ <&mmsys CLK_MM_MDP_DL_TXCK>,
+ <&mmsys CLK_MM_MDP_DL_RX>,
+ <&mmsys CLK_MM_IPU_DL_TXCK>,
+ <&mmsys CLK_MM_IPU_DL_RX>;
+ iommus = <&iommu>;
+ mediatek,mmsys = <&mmsys>;
+ mediatek,mm-mutex = <&mutex>;
+ mediatek,mailbox-gce = <&gce>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
+ gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+ <&gce 0x14010000 SUBSYS_1401XXXX>,
+ <&gce 0x14020000 SUBSYS_1402XXXX>,
+ <&gce 0x15020000 SUBSYS_1502XXXX>;
+ };
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,wdma.yaml
new file mode 100644
index 000000000000..53a4eae9f963
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,wdma.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,wdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Write Direct Memory Access
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ Mediatek Write Direct Memory Access(WDMA) component used to write
+ the data into DMA.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-wdma
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ There may be multiple blocks with the same function but
+ different addresses in MDP3.
+ In order to distinguish the connection with other blocks,
+ a unique ID is needed to dynamically use one or more identical
+ blocks to implement multiple pipelines.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ The register of client driver can be configured by gce with 4 arguments
+ defined in this property, such as phandle of gce, subsys id,
+ register offset and size.
+ Each GCE subsys id is mapping to a client defined in the header
+ include/dt-bindings/gce/<chip>-gce.h.
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ iommus:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_wdma: mdp3_wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp3-wdma";
+ mediatek,mdp3-id = <0>;
+ reg = <0x14006000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
new file mode 100644
index 000000000000..5be288cffc38
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Resizer
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to do frame resizing.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-rsz
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ There may be multiple blocks with the same function but
+ different addresses in MDP3.
+ In order to distinguish the connection with other blocks,
+ a unique ID is needed to dynamically use one or more identical
+ blocks to implement multiple pipelines.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ The register of client driver can be configured by gce with 4 arguments
+ defined in this property, such as phandle of gce, subsys id,
+ register offset and size.
+ Each GCE subsys id is mapping to a client defined in the header
+ include/dt-bindings/gce/<chip>-gce.h.
+
+ clocks:
+ minItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ mdp3_rsz0: mdp3_rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <0>;
+ reg = <0x14003000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp3_rsz1: mdp3_rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <1>;
+ reg = <0x14004000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
new file mode 100644
index 000000000000..f9bed467c353
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Write DMA with Rotation
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-wrot
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ There may be multiple blocks with the same function but
+ different addresses in MDP3.
+ In order to distinguish the connection with other blocks,
+ a unique ID is needed to dynamically use one or more identical
+ blocks to implement multiple pipelines.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ The register of client driver can be configured by gce with 4 arguments
+ defined in this property, such as phandle of gce, subsys id,
+ register offset and size.
+ Each GCE subsys id is mapping to a client defined in the header
+ include/dt-bindings/gce/<chip>-gce.h.
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ iommus:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_wrot0: mdp3_wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ mediatek,mdp3-id = <0>;
+ reg = <0x14005000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu>;
+ };
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v8 6/7] dts: arm64: mt8183: add Mediatek MDP3 nodes
2021-10-15 12:38 [PATCH v8 0/7] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
` (4 preceding siblings ...)
2021-10-15 12:38 ` [PATCH v8 5/7] dt-binding: mt8183: add Mediatek MDP3 dt-bindings Moudy Ho
@ 2021-10-15 12:38 ` Moudy Ho
[not found] ` <20211015123832.17914-8-moudy.ho@mediatek.com>
6 siblings, 0 replies; 16+ messages in thread
From: Moudy Ho @ 2021-10-15 12:38 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
Add device nodes for Media Data Path 3 (MDP3) modules.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 112 ++++++++++++++++++++++-
1 file changed, 111 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 409cf827970c..89597256e5c3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1232,6 +1232,82 @@
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
+ mdp3_rdma0: mdp3_rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp3",
+ "mediatek,mt8183-mdp3-rdma";
+ mediatek,scp = <&scp>;
+ mediatek,mdp3-id = <0>;
+ mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2",
+ "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2",
+ "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto";
+ mdp3-comp-ids = <0 1 0 1 0 1>;
+ reg = <0 0x14001000 0 0x1000>,
+ <0 0x14000000 0 0x1000>,
+ <0 0x14005000 0 0x1000>,
+ <0 0x14006000 0 0x1000>,
+ <0 0x15020000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
+ <&gce SUBSYS_1502XXXX 0 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>,
+ <&mmsys CLK_MM_MDP_DL_TXCK>,
+ <&mmsys CLK_MM_MDP_DL_RX>,
+ <&mmsys CLK_MM_IPU_DL_TXCK>,
+ <&mmsys CLK_MM_IPU_DL_RX>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mediatek,mmsys = <&mmsys>;
+ mediatek,mm-mutex = <&mutex>;
+ mediatek,mailbox-gce = <&gce>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
+ gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+ <&gce 0x14010000 SUBSYS_1401XXXX>,
+ <&gce 0x14020000 SUBSYS_1402XXXX>,
+ <&gce 0x15020000 SUBSYS_1502XXXX>;
+ };
+
+ mdp3_rsz0: mdp3_rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp3_rsz1: mdp3_rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
+
+ mdp3_wrot0: mdp3_wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14005000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ };
+
+ mdp3_wdma: mdp3_wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp3-wdma";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14006000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+ };
+
ovl0: ovl@14008000 {
compatible = "mediatek,mt8183-disp-ovl";
reg = <0 0x14008000 0 0x1000>;
@@ -1356,7 +1432,33 @@
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
- <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
+ <CMDQ_EVENT_MUTEX_STREAM_DONE1>,
+ <CMDQ_EVENT_MDP_RDMA0_SOF>,
+ <CMDQ_EVENT_MDP_RDMA0_EOF>,
+ <CMDQ_EVENT_MDP_RSZ0_SOF>,
+ <CMDQ_EVENT_MDP_RSZ1_SOF>,
+ <CMDQ_EVENT_MDP_TDSHP_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_EOF>,
+ <CMDQ_EVENT_MDP_WDMA0_SOF>,
+ <CMDQ_EVENT_MDP_WDMA0_EOF>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+ <CMDQ_EVENT_WPE_A_DONE>,
+ <CMDQ_EVENT_SPE_B_DONE>;
};
larb0: larb@14017000 {
@@ -1380,6 +1482,14 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
};
+ mdp3_ccorr: mdp3_ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp3-ccorr";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x1401c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
+ };
+
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v8 5/7] dt-binding: mt8183: add Mediatek MDP3 dt-bindings
2021-10-15 12:38 ` [PATCH v8 5/7] dt-binding: mt8183: add Mediatek MDP3 dt-bindings Moudy Ho
@ 2021-10-15 21:45 ` Rob Herring
2021-10-16 14:18 ` Rob Herring
1 sibling, 0 replies; 16+ messages in thread
From: Rob Herring @ 2021-10-15 21:45 UTC (permalink / raw)
To: Moudy Ho
Cc: acourbot, srv_heupstream, pihsun, linux-mediatek, Rob Landley,
allen-kh.cheng, randy.wu, tfiga, daoyuan huang, linux-media,
Ping-Hsun Wu, Mauro Carvalho Chehab, Laurent Pinchart,
Maoguang Meng, Geert Uytterhoeven, sj.huang, menghui.lin,
linux-kernel, Rob Herring, linux-arm-kernel, drinkcat,
Jernej Skrabec, devicetree, hsinyi, Matthias Brugger,
Hans Verkuil
On Fri, 15 Oct 2021 20:38:30 +0800, Moudy Ho wrote:
> This patch adds DT binding document for Media Data Path 3 (MDP3)
> a unit in multimedia system used for scaling and color format convert.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> .../bindings/arm/mediatek/mediatek,ccorr.yaml | 59 +++++
> .../bindings/arm/mediatek/mediatek,rdma.yaml | 211 ++++++++++++++++++
> .../bindings/arm/mediatek/mediatek,wdma.yaml | 70 ++++++
> .../bindings/media/mediatek,mdp3-rsz.yaml | 68 ++++++
> .../bindings/media/mediatek,mdp3-wrot.yaml | 70 ++++++
> 5 files changed, 478 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,wdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/arm/mediatek/mediatek,wdma.yaml:20:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
./Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml:211:7: [error] no new line character at the end of file (new-line-at-end-of-file)
./Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml:19:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
./Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml:20:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
./Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml:20:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1541634
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 5/7] dt-binding: mt8183: add Mediatek MDP3 dt-bindings
2021-10-15 12:38 ` [PATCH v8 5/7] dt-binding: mt8183: add Mediatek MDP3 dt-bindings Moudy Ho
2021-10-15 21:45 ` Rob Herring
@ 2021-10-16 14:18 ` Rob Herring
2021-11-23 3:12 ` moudy ho
1 sibling, 1 reply; 16+ messages in thread
From: Rob Herring @ 2021-10-16 14:18 UTC (permalink / raw)
To: Moudy Ho
Cc: Mauro Carvalho Chehab, Matthias Brugger, Hans Verkuil,
Jernej Skrabec, Maoguang Meng, daoyuan huang, Ping-Hsun Wu,
Geert Uytterhoeven, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
tfiga, drinkcat, acourbot, pihsun, menghui.lin, sj.huang,
allen-kh.cheng, randy.wu, srv_heupstream, hsinyi
On Fri, Oct 15, 2021 at 08:38:30PM +0800, Moudy Ho wrote:
> This patch adds DT binding document for Media Data Path 3 (MDP3)
> a unit in multimedia system used for scaling and color format convert.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> .../bindings/arm/mediatek/mediatek,ccorr.yaml | 59 +++++
> .../bindings/arm/mediatek/mediatek,rdma.yaml | 211 ++++++++++++++++++
> .../bindings/arm/mediatek/mediatek,wdma.yaml | 70 ++++++
These belong in a functional directory, not 'arm'.
> .../bindings/media/mediatek,mdp3-rsz.yaml | 68 ++++++
> .../bindings/media/mediatek,mdp3-wrot.yaml | 70 ++++++
> 5 files changed, 478 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,wdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml
> new file mode 100644
> index 000000000000..40ea7955efc6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,ccorr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek color correction
> +
> +maintainers:
> + - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description: |
> + Mediatek color correction with 3X3 matrix.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8183-mdp3-ccorr
> +
> + mediatek,mdp3-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maxItems: 1
maxItems is for an array, but you said this is a uint32.
> + description: |
> + There may be multiple blocks with the same function but
> + different addresses in MDP3.
> + In order to distinguish the connection with other blocks,
> + a unique ID is needed to dynamically use one or more identical
> + blocks to implement multiple pipelines.
They aren't identical if you need to distinguish them. We should
describe the difference rather than make up device indices. Why is this
needed?
For connections between components, use the graph binding.
> +
> + reg:
> + maxItems: 1
> +
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + The register of client driver can be configured by gce with 4 arguments
> + defined in this property, such as phandle of gce, subsys id,
> + register offset and size.
> + Each GCE subsys id is mapping to a client defined in the header
> + include/dt-bindings/gce/<chip>-gce.h.
> +
> + clocks:
> + minItems: 1
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/gce/mt8183-gce.h>
> +
> + mdp3_ccorr: mdp3_ccorr@1401c000 {
> + compatible = "mediatek,mt8183-mdp3-ccorr";
> + mediatek,mdp3-id = <0>;
> + reg = <0x1401c000 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_CCORR>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml
> new file mode 100644
> index 000000000000..ad0e56923494
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml
> @@ -0,0 +1,211 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,rdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Read Direct Memory Access
> +
> +maintainers:
> + - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description: |
> + Mediatek Read Direct Memory Access(RDMA) component used to do read DMA.
> + It contains one line buffer to store the sufficient pixel data, and
> + must be siblings to the central MMSYS_CONFIG node.
> + For a description of the MMSYS_CONFIG binding, see
> + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> + for details.
> + The 1st RDMA is also used to be a controller node in Media Data Path 3(MDP3)
> + that containing MMSYS, MUTEX, GCE and SCP settings.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: mediatek,mt8183-mdp3
This looks less specific than this:
> + - const: mediatek,mt8183-mdp3-rdma
Which is the wrong order. But why the 2 values to begin with?
> + - items:
> + - const: mediatek,mt8183-mdp3-rdma
> +
> + mediatek,scp:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + maxItems: 1
> + description: |
> + The node of system control processor (SCP), using
> + the remoteproc & rpmsg framework.
> + $ref: /schemas/remoteproc/mtk,scp.yaml
> +
> + mediatek,mdp3-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maxItems: 1
> + description: |
> + There may be multiple blocks with the same function but
> + different addresses in MDP3.
> + In order to distinguish the connection with other blocks,
> + a unique ID is needed to dynamically use one or more identical
> + blocks to implement multiple pipelines.
> +
> + mdp3-comps:
vendor prefix needed.
> + $ref: /schemas/types.yaml#/definitions/string-array
> + items:
> + - enum:
> + # MDP direct-link input path selection, create a
> + # component for path connectedness of HW pipe control
> + - mediatek,mt8183-mdp3-dl1
> + - enum:
> + - mediatek,mt8183-mdp3-dl2
> + - enum:
> + # MDP direct-link output path selection, create a
> + # component for path connectedness of HW pipe control
> + - mediatek,mt8183-mdp3-path1
> + - enum:
> + - mediatek,mt8183-mdp3-path2
> + - enum:
> + # Input DMA of ISP PASS2 (DIP) module for raw image input
> + - mediatek,mt8183-mdp3-imgi
> + - enum:
> + # Output DMA of ISP PASS2 (DIP) module for YUV image output
> + - mediatek,mt8183-mdp3-exto
> + description: |
> + MTK sub-system of direct-link or DIP
> +
> + mdp3-comp-ids:
> + maxItems: 1
> + $ref: /schemas/types.yaml#/definitions/uint32-array
An array of only 1 item is a 'uint32'
> + description: |
> + Pipeline ID of MDP sub-system.
Needs a better description and possibly constraints. Any value 0-2^32 is
valid?
> +
> + reg:
> + minItems: 1
> + maxItems: 5
> + description: |
> + 1st: basic HW address
> + 2nd: mediatek,mt8183-mdp-dl1, mediatek,mt8183-mdp-dl2
> + 3rd: mediatek,mt8183-mdp-path1
> + 4th: mediatek,mt8183-mdp-path2
> + 5th: mediatek,mt8183-mdp3-imgi, mediatek,mt8183-mdp3-exto
This is better expressed as:
items:
- description: ...
- description: ...
- description: ...
- description: ...
- description: ...
> +
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + The register of client driver can be configured by gce with 4 arguments
So 'maxItems: 4'?
> + defined in this property, such as phandle of gce, subsys id,
> + register offset and size.
> + Each GCE subsys id is mapping to a client defined in the header
> + include/dt-bindings/gce/<chip>-gce.h.
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 6
> + description: |
> + 1st: RDMA0 clock
> + 2nd: RSZ1 clock
> + 3rd: direck-link TX clock in MDP side
> + 4th: direck-link RX clock in MDP side
> + 5th: direck-link TX clock in ISP side
> + 6th: direck-link RX clock in ISP side
Again, use 'items'.
> +
> + iommus:
> + maxItems: 1
> +
> + mediatek,mmsys:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + maxItems: 1
Not an array.
> + description: |
Don't need '|' when there is no formatting to maintain.
> + The node of mux(multiplexer) controller for HW connections.
> +
> + mediatek,mm-mutex:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + maxItems: 1
> + description: |
> + The node of sof(start of frame) signal controller.
> +
> + mediatek,mailbox-gce:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: |
> + The node of global command engine (GCE), used to read/write
> + registers with critical time limitation.
> +
> + mboxes:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
Already has a type. This is where you need to define how many and what
each one is if more than 1.
> +
> + gce-subsys:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + sub-system id corresponding to the global command engine (GCE)
> + register address.
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + const: mediatek,mt8183-mdp3
> +
> +then:
> + required:
> + - mediatek,scp
> + - mediatek,mmsys
> + - mediatek,mm-mutex
> + - mediatek,mailbox-gce
> + - mboxes
> + - gce-subsys
> +
> +required:
> + - compatible
> + - mediatek,mdp3-id
> + - reg
> + - clocks
> + - mediatek,gce-client-reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/gce/mt8183-gce.h>
> + #include <dt-bindings/power/mt8183-power.h>
> + #include <dt-bindings/memory/mt8183-larb-port.h>
> +
> + mdp3_rdma0: mdp3_rdma0@14001000 {
> + compatible = "mediatek,mt8183-mdp3",
> + "mediatek,mt8183-mdp3-rdma";
> + mediatek,scp = <&scp>;
> + mediatek,mdp3-id = <0>;
> + mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2",
> + "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2",
> + "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto";
> + mdp3-comp-ids = <0 1 0 1 0 1>;
> + reg = <0x14001000 0x1000>,
> + <0x14000000 0x1000>,
> + <0x14005000 0x1000>,
> + <0x14006000 0x1000>,
> + <0x15020000 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
> + <&gce SUBSYS_1400XXXX 0 0x1000>,
> + <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
> + <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
> + <&gce SUBSYS_1502XXXX 0 0x1000>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> + <&mmsys CLK_MM_MDP_RSZ1>,
> + <&mmsys CLK_MM_MDP_DL_TXCK>,
> + <&mmsys CLK_MM_MDP_DL_RX>,
> + <&mmsys CLK_MM_IPU_DL_TXCK>,
> + <&mmsys CLK_MM_IPU_DL_RX>;
> + iommus = <&iommu>;
> + mediatek,mmsys = <&mmsys>;
> + mediatek,mm-mutex = <&mutex>;
> + mediatek,mailbox-gce = <&gce>;
> + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
> + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
> + <&gce 0x14010000 SUBSYS_1401XXXX>,
> + <&gce 0x14020000 SUBSYS_1402XXXX>,
> + <&gce 0x15020000 SUBSYS_1502XXXX>;
> + };
> \ No newline at end of file
Fix this.
Similar comments on the rest...
Rob
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 4/7] soc: mediatek: mutex: add functions that operate registers by CMDQ
2021-10-15 12:38 ` [PATCH v8 4/7] soc: mediatek: mutex: add functions that operate registers by CMDQ Moudy Ho
@ 2021-10-18 13:50 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 16+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-18 13:50 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
> Considering that some functions have timing requirements
> in specific situation, this patch adds several interface that
> operate registers by CMDQ.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 63 +++++++++++++++++++++++++-
> include/linux/soc/mediatek/mtk-mutex.h | 6 +++
> 2 files changed, 68 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index adab4c9edc16..874d4c60b844 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -7,10 +7,12 @@
> #include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> #include <linux/soc/mediatek/mtk-mutex.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> @@ -143,6 +145,8 @@ struct mtk_mutex_ctx {
> void __iomem *regs;
> struct mtk_mutex mutex[10];
> const struct mtk_mutex_data *data;
> + phys_addr_t addr;
> + u8 subsys_id;
> };
>
> static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> @@ -442,6 +446,25 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
>
> +void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> + mutex[mutex->id]);
> + unsigned int offset;
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
> + mod, mtx->data->mutex_mdp_mod_mask);
> +
> + offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
> + 0, mtx->data->mutex_mdp_sof_mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
> +
> void mtk_mutex_enable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> @@ -453,6 +476,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_enable);
>
> +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + 0x1, 0x00000001);
(don't use this definition name if not appropriate)
#define MTK_MUTEX_ENABLE BIT(0)
cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
MTK_MUTEX_ENABLE, MTK_MUTEX_ENABLE);
...or anyway remove leading zeros.
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
> +
> void mtk_mutex_disable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> @@ -464,6 +501,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_disable);
>
> +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + 0x0, 0x00000001);
cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
0, MTK_MUTEX_ENABLE);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
> +
Regards,
- Angelo
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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 2/7] soc: mediatek: mmsys: add support for ISP control
2021-10-15 12:38 ` [PATCH v8 2/7] soc: mediatek: mmsys: add support for ISP control Moudy Ho
@ 2021-10-18 13:50 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 16+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-18 13:50 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
> This patch adds 8183 ISP settings in MMSYS domain and interface.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> drivers/soc/mediatek/mt8183-mmsys.h | 16 ++++
> drivers/soc/mediatek/mtk-mmsys.c | 108 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> include/linux/soc/mediatek/mtk-mmsys.h | 25 ++++++
> 4 files changed, 150 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 663f196fc4e7..c490cc1b1072 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -32,6 +32,13 @@
> #define MT8183_MDP_CCORR_SEL_IN 0xff0
> #define MT8183_MDP_CCORR_SOUT_SEL 0xff4
>
> +#define MT8183_ISP_CTRL_MMSYS_SW0_RST_B 0x140
> +#define MT8183_ISP_CTRL_MMSYS_SW1_RST_B 0x144
> +#define MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD 0x934
> +#define MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD 0x93C
> +#define MT8183_ISP_CTRL_ISP_RELAY_CFG_WD 0x994
> +#define MT8183_ISP_CTRL_IPU_RELAY_CFG_WD 0x9a0
> +
> #define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
> #define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
> #define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> @@ -276,5 +283,14 @@ static const struct mtk_mmsys_routes mmsys_mt8183_mdp_routing_table[] = {
> }
> };
>
> +static const unsigned int mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
> + [ISP_CTRL_MMSYS_SW0_RST_B] = MT8183_ISP_CTRL_MMSYS_SW0_RST_B,
> + [ISP_CTRL_MMSYS_SW1_RST_B] = MT8183_ISP_CTRL_MMSYS_SW1_RST_B,
> + [ISP_CTRL_MDP_ASYNC_CFG_WD] = MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD,
> + [ISP_CTRL_MDP_ASYNC_IPU_CFG_WD] = MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD,
> + [ISP_CTRL_ISP_RELAY_CFG_WD] = MT8183_ISP_CTRL_ISP_RELAY_CFG_WD,
> + [ISP_CTRL_IPU_RELAY_CFG_WD] = MT8183_ISP_CTRL_IPU_RELAY_CFG_WD,
> +};
> +
> #endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 31fec490617e..f4b1d2fa41b4 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -55,6 +55,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> .mdp_routes = mmsys_mt8183_mdp_routing_table,
> .mdp_num_routes = ARRAY_SIZE(mmsys_mt8183_mdp_routing_table),
> + .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
> };
>
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> @@ -142,6 +143,113 @@ void mtk_mmsys_mdp_disconnect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_disconnect);
>
> +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> + u32 reg;
> +
> + WARN_ON(mmsys->subsys_id == 0);
> + /* Direct link */
> + if (id == MDP_COMP_CAMIN) {
> + /* Reset MDP_DL_ASYNC_TX */
> + /* Bit 3: MDP_DL_ASYNC_TX / MDP_RELAY */
> + if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 0x0, 0x00000008);
This is 0, 0x8);
Please remove leading zeros.
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 1 << 3, 0x00000008);
1 << 3 is BIT(3)
Also remove leading zeros.
> + }
> +
> + /* Reset MDP_DL_ASYNC_RX */
> + /* Bit 10: MDP_DL_ASYNC_RX */
> + if (isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 0x0, 0x00000400);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 1 << 10, 0x00000400);
BIT(10) and leading zeros.
> + }
> +
> + /* Enable sof mode */
> + if (isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 0 << 31, 0x80000000);
Shifting 0 by N bits is still zero, so this is simply 0.
> + }
> + }
> +
> + if (id == MDP_COMP_CAMIN2) {
> + /* Reset MDP_DL_ASYNC2_TX */
> + /* Bit 4: MDP_DL_ASYNC2_TX / MDP_RELAY2 */
> + if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 0x0, 0x00000010);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 1 << 4, 0x00000010);
Please use the BIT() macro and remove leading zeros, here and everywhere else.
Also, I would really appreciate if you defined these bits somewhere instead of
writing "magic values".
For example, here you're documenting what bit 4 is, but it would be better if
you simply defined (please use appropriate names!)
#define MY_REGISTER_BIT BIT(4)
...and then you called your function like that:
cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
0, MY_REGISTER_BIT);
and then
cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
MY_REGISTER_BIT, MY_REGISTER_BIT);
So, since you're documenting it with defines, you will also be able to remove
the comments describing the same thing.
Regards,
- Angelo
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 3/7] soc: mediatek: mutex: add support for MDP
2021-10-15 12:38 ` [PATCH v8 3/7] soc: mediatek: mutex: add support for MDP Moudy Ho
@ 2021-10-18 13:50 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 16+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-18 13:50 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
Il 15/10/21 14:38, Moudy Ho ha scritto:
> For the purpose of module independence, related settings should be moved
> from MDP to the corresponding driver.
> This patch adds more 8183 MDP settings and interface.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 33 ++++++++++++++++++++++++++
> include/linux/soc/mediatek/mtk-mutex.h | 2 ++
> 2 files changed, 35 insertions(+)
>
Acked-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 1/7] soc: mediatek: mmsys: add support for MDP
2021-10-15 12:38 ` [PATCH v8 1/7] soc: mediatek: mmsys: add support for MDP Moudy Ho
@ 2021-10-18 13:50 ` AngeloGioacchino Del Regno
2021-11-11 11:40 ` AngeloGioacchino Del Regno
0 siblings, 1 reply; 16+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-18 13:50 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
Il 15/10/21 14:38, Moudy Ho ha scritto:
> For the purpose of module independence, related settings should be moved
> from MDP to the corresponding driver.
> This patch adds more 8183 MDP settings and interface. and MDP
> related settings must be set via CMDQ to avoid frame unsynchronized.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> drivers/soc/mediatek/Kconfig | 1 +
> drivers/soc/mediatek/mt8183-mmsys.h | 219 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 52 ++++++
> drivers/soc/mediatek/mtk-mmsys.h | 2 +
> include/linux/soc/mediatek/mtk-mmsys.h | 56 +++++++
> 5 files changed, 330 insertions(+)
>
snip...
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index a78e88f27b62..31fec490617e 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -7,8 +7,10 @@
> #include <linux/device.h>
> #include <linux/io.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk-mmsys.h"
> #include "mt8167-mmsys.h"
> @@ -51,6 +53,8 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> + .mdp_routes = mmsys_mt8183_mdp_routing_table,
> + .mdp_num_routes = ARRAY_SIZE(mmsys_mt8183_mdp_routing_table),
> };
>
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> @@ -62,6 +66,8 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> + phys_addr_t addr;
> + u8 subsys_id;
> };
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -101,12 +107,49 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_mdp_connect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id cur,
> + enum mtk_mdp_comp_id next)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
> + int i;
> +
> + WARN_ON(!routes);
Sorry, I didn't notice this one in the previous version review.
> + WARN_ON(mmsys->subsys_id == 0);
> + for (i = 0; i < mmsys->data->mdp_num_routes; i++)
> + if (cur == routes[i].from_comp && next == routes[i].to_comp)
If routes is NULL, you'll get a NULL pointer kernel panic here, so you should
avoid reaching this point if that happens.
After fixing that,
Acked-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 1/7] soc: mediatek: mmsys: add support for MDP
2021-10-18 13:50 ` AngeloGioacchino Del Regno
@ 2021-11-11 11:40 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 16+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-11-11 11:40 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
Il 18/10/21 15:50, AngeloGioacchino Del Regno ha scritto:
> Il 15/10/21 14:38, Moudy Ho ha scritto:
>> For the purpose of module independence, related settings should be moved
>> from MDP to the corresponding driver.
>> This patch adds more 8183 MDP settings and interface. and MDP
>> related settings must be set via CMDQ to avoid frame unsynchronized.
>>
>> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
>> ---
>> drivers/soc/mediatek/Kconfig | 1 +
>> drivers/soc/mediatek/mt8183-mmsys.h | 219 +++++++++++++++++++++++++
>> drivers/soc/mediatek/mtk-mmsys.c | 52 ++++++
>> drivers/soc/mediatek/mtk-mmsys.h | 2 +
>> include/linux/soc/mediatek/mtk-mmsys.h | 56 +++++++
>> 5 files changed, 330 insertions(+)
>>
>
This patch does not apply cleanly anymore, as of next-20211111.
Can you please send a v9 asap?
Thanks,
Angelo
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 5/7] dt-binding: mt8183: add Mediatek MDP3 dt-bindings
2021-10-16 14:18 ` Rob Herring
@ 2021-11-23 3:12 ` moudy ho
0 siblings, 0 replies; 16+ messages in thread
From: moudy ho @ 2021-11-23 3:12 UTC (permalink / raw)
To: Rob Herring
Cc: Mauro Carvalho Chehab, Matthias Brugger, Hans Verkuil,
Jernej Skrabec, Maoguang Meng, daoyuan huang, Ping-Hsun Wu,
Geert Uytterhoeven, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
tfiga, drinkcat, acourbot, pihsun, menghui.lin, sj.huang,
allen-kh.cheng, randy.wu, srv_heupstream, hsinyi, jason-jh.lin
On Sat, 2021-10-16 at 09:18 -0500, Rob Herring wrote:
> On Fri, Oct 15, 2021 at 08:38:30PM +0800, Moudy Ho wrote:
> > This patch adds DT binding document for Media Data Path 3 (MDP3)
> > a unit in multimedia system used for scaling and color format
> > convert.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> > .../bindings/arm/mediatek/mediatek,ccorr.yaml | 59 +++++
> > .../bindings/arm/mediatek/mediatek,rdma.yaml | 211
> > ++++++++++++++++++
> > .../bindings/arm/mediatek/mediatek,wdma.yaml | 70 ++++++
>
> These belong in a functional directory, not 'arm'.
>
Hi Matthias,
We tried to integrate the common components of DRM & MDP3 into the same
binding files and move them to the "bindings/arm/mediatek" directory,
but it did not meet the requirements.
Is it appropriate for us to change the path to "bindings/soc/mediatek",
or do you have other suggestions?
Thanks & Regards,
Moudy Ho
> > .../bindings/media/mediatek,mdp3-rsz.yaml | 68 ++++++
> > .../bindings/media/mediatek,mdp3-wrot.yaml | 70 ++++++
> > 5 files changed, 478 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,ccorr.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,rdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,wdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
(snip)
>
> Fix this.
>
> Similar comments on the rest...
>
> Rob
>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 7/7] media: platform: mtk-mdp3: add Mediatek MDP3 driver
[not found] ` <df3ca43b-ea02-36f7-2d37-7240a1ba4f96@collabora.com>
@ 2021-11-23 9:19 ` moudy ho
0 siblings, 0 replies; 16+ messages in thread
From: moudy ho @ 2021-11-23 9:19 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, allen-kh.cheng,
randy.wu, srv_heupstream, hsinyi
On Mon, 2021-10-18 at 15:49 +0200, AngeloGioacchino Del Regno wrote:
> > This patch adds driver for Mediatek's Media Data Path ver.3 (MDP3).
> > It provides the following functions:
> > color transform, format conversion, resize, crop, rotate, flip
> > and additional image quality enhancement.
> >
> > The MDP3 driver is mainly used for Google Chromebook products to
> > import the new architecture to set the HW settings as shown below:
> > User -> V4L2 framework
> > -> MDP3 driver -> SCP (setting calculations)
> > -> MDP3 driver -> CMDQ (GCE driver) -> HW
> >
> > Each modules' related operation control is sited in mtk-mdp3-comp.c
> > Each modules' register table is defined in file with "mdp_reg_"
> > prefix
> > GCE related API, operation control sited in mtk-mdp3-cmdq.c
> > V4L2 m2m device functions are implemented in mtk-mdp3-m2m.c
> > Probe, power, suspend/resume, system level functions are defined in
> > mtk-mdp3-core.c
> >
> > Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> > Depend on:
> > [1]
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20190906115513.159705-9-acourbot@chromium.org/__;!!CTRNKA9wMg0ARbw!xFX7LsYeTavOapGwdM6Viy-_5Rlf-aa1FkMbMZQc6tol5Veeq1ZkQkld3FTXMc7x$
> >
> > [2]
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20190906115513.159705-10-acourbot@chromium.org/__;!!CTRNKA9wMg0ARbw!xFX7LsYeTavOapGwdM6Viy-_5Rlf-aa1FkMbMZQc6tol5Veeq1ZkQkld3Fxm1BEE$
> >
> > ---
> > drivers/media/platform/Kconfig | 19 +
> > drivers/media/platform/Makefile | 2 +
> > drivers/media/platform/mtk-mdp3/Makefile | 6 +
> > .../media/platform/mtk-mdp3/mdp_reg_ccorr.h | 19 +
> > drivers/media/platform/mtk-mdp3/mdp_reg_isp.h | 27 +
> > .../media/platform/mtk-mdp3/mdp_reg_rdma.h | 65 +
> > drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 39 +
> > .../media/platform/mtk-mdp3/mdp_reg_wdma.h | 47 +
> > .../media/platform/mtk-mdp3/mdp_reg_wrot.h | 55 +
> > drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 280 ++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 514 +++++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 46 +
> > .../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 1307
> > +++++++++++++++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 147 ++
> > .../media/platform/mtk-mdp3/mtk-mdp3-core.c | 340 +++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-core.h | 76 +
> > .../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 789 ++++++++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-m2m.h | 49 +
> > .../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 737 ++++++++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 373 +++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 313 ++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 78 +
> > 22 files changed, 5328 insertions(+)
> > create mode 100644 drivers/media/platform/mtk-mdp3/Makefile
> > create mode 100644 drivers/media/platform/mtk-
> > mdp3/mdp_reg_ccorr.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_isp.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wdma.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-
> > cmdq.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-
> > cmdq.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-
> > comp.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-
> > comp.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-
> > core.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-
> > core.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-
> > regs.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-
> > regs.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
(snip)
> > diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> > b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> > new file mode 100644
> > index 000000000000..110f8911638f
> > --- /dev/null
> > +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> > @@ -0,0 +1,514 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > + */
> > +
> > +#include <linux/platform_device.h>
> > +#include "mtk-mdp3-cmdq.h"
> > +#include "mtk-mdp3-comp.h"
> > +#include "mtk-mdp3-core.h"
> > +#include "mtk-mdp3-m2m.h"
> > +
> > +static void mdp_auto_release_work(struct work_struct *work)
> > +{
> > + struct mdp_cmdq_cb_param *cb_param;
> > + struct mdp_dev *mdp;
> > +
> > + cb_param = container_of(work, struct mdp_cmdq_cb_param,
> > + auto_release_work);
> > + mdp = cb_param->mdp;
> > +
> > + mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
> > + mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
> > + cb_param->num_comps);
> > +
> > + kfree(cb_param->comps);
> > + kfree(cb_param);
> > +
> > + atomic_dec(&mdp->job_count);
> > + wake_up(&mdp->callback_wq);
> > +}
> > +
> > +static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
> > +{
> > + struct mdp_cmdq_cb_param *cb_param;
> > + struct mdp_dev *mdp;
> > + struct device *dev;
> > +
> > + if (!data.data) {
> > + pr_info("%s:no callback data\n", __func__);
>
> If this is not an error, then I'd say it should be a dev_dbg().
>
Hi Angelo,
Thanks for reminding, and this is a CMDQ driver
callback and pass empty data error handling.
Before this check, the dev_err can't be used but pr_info instead, or do
you have other better ideas?
Thanks & Regards,
Moudy Ho
> > + return;
+ }
+ cb_param = (struct
> > mdp_cmdq_cb_param *)data.data;
+ mdp = cb_param->mdp;
+ dev
> > = &mdp->pdev->dev;
+
+ if (cb_param->mdp_ctx)
+ mdp
> > _m2m_job_finish(cb_param->mdp_ctx);
+
+ if (cb_param-
> > >user_cmdq_cb) {
+ struct cmdq_cb_data user_cb_data;
+
+
> > user_cb_data.sta = data.sta;
+ user_cb_data.data =
> > cb_param->user_cb_data;
+ cb_param-
> > >user_cmdq_cb(user_cb_data);
+ }
+
+ cmdq_pkt_destroy(cb_param-
> > >pkt);
+ INIT_WORK(&cb_param->auto_release_work,
> > mdp_auto_release_work);
+ if (!queue_work(mdp->clock_wq,
> > &cb_param->auto_release_work)) {
> > + dev_err(dev, +"%s:queue_work fail!\n", __func__);
> > +
> > +int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param
> > *param)
> > +{
> > + struct mmsys_cmdq_cmd cmd;
> > + struct mdp_path *path = NULL;
> > + struct mdp_cmdq_cb_param *cb_param = NULL;
> > + struct mdp_comp *comps = NULL;
> > + struct device *dev = &mdp->pdev->dev;
> > + int i, ret;
> > +
> > + if (atomic_read(&mdp->suspended))
> > + return -ECANCELED;
> > +
> > + atomic_inc(&mdp->job_count);
> > +
> > + cmd.pkt = cmdq_pkt_create(mdp->cmdq_clt, SZ_16K);
> > + if (IS_ERR(cmd.pkt)) {
> > + atomic_dec(&mdp->job_count);
> > + wake_up(&mdp->callback_wq);
> > + return PTR_ERR(cmd.pkt);
> > + }
> > + cmd.event = &mdp->event[0];
> > +
> > + path = kzalloc(sizeof(*path), GFP_KERNEL);
> > + if (!path) {
> > + ret = -ENOMEM;
> > + goto err_destroy_pkt;
> > + }
> > +
> > + path->mdp_dev = mdp;
> > + path->config = param->config;
> > + path->param = param->param;
> > + for (i = 0; i < param->param->num_outputs; i++) {
> > + path->bounds[i].left = 0;
> > + path->bounds[i].top = 0;
> > + path->bounds[i].width =
> > + param->param->outputs[i].buffer.format.width;
> > + path->bounds[i].height =
> > + param->param->outputs[i].buffer.format.height;
> > + path->composes[i] = param->composes[i] ?
> > + param->composes[i] : &path->bounds[i];
> > + }
> > +
> > + ret = mdp_path_ctx_init(mdp, path);
> > + if (ret) {
> > + pr_info("%s mdp_path_ctx_init error\n", __func__);
>
> Please, use dev_err here.
>
> > + goto err_destroy_pkt;
> > + }
> > +
> > + mtk_mutex_prepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
> > + for (i = 0; i < param->config->num_components; i++)
> > + mdp_comp_clock_on(&mdp->pdev->dev, path-
> > >comps[i].comp);
> > +
> > + ret = mdp_path_config(mdp, &cmd, path);
> > + if (ret) {
> > + pr_info("%s mdp_path_config error\n", __func__);
>
> This is also dev_err.
>
> > + goto err_destroy_pkt;
> > + }
> > +
> > + cb_param = kzalloc(sizeof(*cb_param), GFP_KERNEL);
> > + if (!cb_param) {
> > + ret = -ENOMEM;
> > + goto err_destroy_pkt;
> > + }
> > +
> > + comps = kcalloc(param->config->num_components, sizeof(*comps),
> > + GFP_KERNEL);
> > + if (!comps) {
> > + ret = -ENOMEM;
> > + goto err_destroy_pkt;
> > + }
> > +
> > + for (i = 0; i < param->config->num_components; i++)
> > + memcpy(&comps[i], path->comps[i].comp,
> > + sizeof(struct mdp_comp));
> > + cb_param->mdp = mdp;
> > + cb_param->user_cmdq_cb = param->cmdq_cb;
> > + cb_param->user_cb_data = param->cb_data;
> > + cb_param->pkt = cmd.pkt;
> > + cb_param->comps = comps;
> > + cb_param->num_comps = param->config->num_components;
> > + cb_param->mdp_ctx = param->mdp_ctx;
> > +
> > + cmdq_pkt_finalize(cmd.pkt);
> > + ret = cmdq_pkt_flush_async(cmd.pkt,
> > + mdp_handle_cmdq_callback,
> > + (void *)cb_param);
> > + if (ret) {
> > + dev_err(dev, "cmdq_pkt_flush_async fail!\n");
> > + goto err_clock_off;
> > + }
> > + return 0;
> > +
> > +err_clock_off:
> > + mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
> > + mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
> > + cb_param->num_comps);
> > +err_destroy_pkt:
> > + cmdq_pkt_destroy(cmd.pkt);
> > + atomic_dec(&mdp->job_count);
> > + wake_up(&mdp->callback_wq);
> > + kfree(comps);
> > + kfree(cb_param);
> > + kfree(path);
> > +
> > + return ret;
> > +}
> > +
> > +int mdp_cmdq_sendtask(struct platform_device *pdev, struct
> > img_config *config,
> > + struct img_ipi_frameparam *param,
> > + struct v4l2_rect *compose,
> > + void (*cmdq_cb)(struct cmdq_cb_data data), void
> > *cb_data)
> > +{
> > + struct mdp_dev *mdp = platform_get_drvdata(pdev);
> > + struct mdp_cmdq_param task = {
> > + .config = config,
> > + .param = param,
> > + .composes[0] = compose,
> > + .cmdq_cb = cmdq_cb,
> > + .cb_data = cb_data,
> > + };
> > +
> > + return mdp_cmdq_send(mdp, &task);
> +}
(snip)
>
> Thanks,
> - Angelo
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^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2021-11-23 9:22 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-15 12:38 [PATCH v8 0/7] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2021-10-15 12:38 ` [PATCH v8 1/7] soc: mediatek: mmsys: add support for MDP Moudy Ho
2021-10-18 13:50 ` AngeloGioacchino Del Regno
2021-11-11 11:40 ` AngeloGioacchino Del Regno
2021-10-15 12:38 ` [PATCH v8 2/7] soc: mediatek: mmsys: add support for ISP control Moudy Ho
2021-10-18 13:50 ` AngeloGioacchino Del Regno
2021-10-15 12:38 ` [PATCH v8 3/7] soc: mediatek: mutex: add support for MDP Moudy Ho
2021-10-18 13:50 ` AngeloGioacchino Del Regno
2021-10-15 12:38 ` [PATCH v8 4/7] soc: mediatek: mutex: add functions that operate registers by CMDQ Moudy Ho
2021-10-18 13:50 ` AngeloGioacchino Del Regno
2021-10-15 12:38 ` [PATCH v8 5/7] dt-binding: mt8183: add Mediatek MDP3 dt-bindings Moudy Ho
2021-10-15 21:45 ` Rob Herring
2021-10-16 14:18 ` Rob Herring
2021-11-23 3:12 ` moudy ho
2021-10-15 12:38 ` [PATCH v8 6/7] dts: arm64: mt8183: add Mediatek MDP3 nodes Moudy Ho
[not found] ` <20211015123832.17914-8-moudy.ho@mediatek.com>
[not found] ` <df3ca43b-ea02-36f7-2d37-7240a1ba4f96@collabora.com>
2021-11-23 9:19 ` [PATCH v8 7/7] media: platform: mtk-mdp3: add Mediatek MDP3 driver moudy ho
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