From: Shawn Guo <shawnguo@kernel.org>
To: Li Yang <leoyang.li@nxp.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Xiaowei Bao <xiaowei.bao@nxp.com>,
Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: Re: [PATCH v2 06/10] arm64: dts: lx2160a: add pcie EP mode nodes
Date: Tue, 14 Dec 2021 13:40:45 +0800 [thread overview]
Message-ID: <20211214054044.GG10916@dragon> (raw)
In-Reply-To: <20211203235446.8266-7-leoyang.li@nxp.com>
On Fri, Dec 03, 2021 at 05:54:42PM -0600, Li Yang wrote:
> From: Xiaowei Bao <xiaowei.bao@nxp.com>
>
> The LX2160A PCIe EP mode nodes based on controller used on lx2160a rev2.
>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 60 +++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index de680521e1d1..593c5a498ae3 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -1115,6 +1115,16 @@ pcie1: pcie@3400000 {
> status = "disabled";
> };
>
> + pcie_ep1: pcie_ep@3400000 {
Hyphen is more recommended than underscore for node name.
Shawn
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03400000 0x0 0x00100000
> + 0x80 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <8>;
> + num-ib-windows = <8>;
> + status = "disabled";
> + };
> +
> pcie2: pcie@3500000 {
> compatible = "fsl,ls2088a-pcie";
> reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
> @@ -1143,6 +1153,16 @@ pcie2: pcie@3500000 {
> status = "disabled";
> };
>
> + pcie_ep2: pcie_ep@3500000 {
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03500000 0x0 0x00100000
> + 0x88 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <8>;
> + num-ib-windows = <8>;
> + status = "disabled";
> + };
> +
> pcie3: pcie@3600000 {
> compatible = "fsl,ls2088a-pcie";
> reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
> @@ -1171,6 +1191,16 @@ pcie3: pcie@3600000 {
> status = "disabled";
> };
>
> + pcie_ep3: pcie_ep@3600000 {
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03600000 0x0 0x00100000
> + 0x90 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <256>;
> + num-ib-windows = <24>;
> + status = "disabled";
> + };
> +
> pcie4: pcie@3700000 {
> compatible = "fsl,ls2088a-pcie";
> reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
> @@ -1199,6 +1229,16 @@ pcie4: pcie@3700000 {
> status = "disabled";
> };
>
> + pcie_ep4: pcie_ep@3700000 {
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03700000 0x0 0x00100000
> + 0x98 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <8>;
> + num-ib-windows = <8>;
> + status = "disabled";
> + };
> +
> pcie5: pcie@3800000 {
> compatible = "fsl,ls2088a-pcie";
> reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
> @@ -1227,6 +1267,16 @@ pcie5: pcie@3800000 {
> status = "disabled";
> };
>
> + pcie_ep5: pcie_ep@3800000 {
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03800000 0x0 0x00100000
> + 0xa0 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <256>;
> + num-ib-windows = <24>;
> + status = "disabled";
> + };
> +
> pcie6: pcie@3900000 {
> compatible = "fsl,ls2088a-pcie";
> reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
> @@ -1255,6 +1305,16 @@ pcie6: pcie@3900000 {
> status = "disabled";
> };
>
> + pcie_ep6: pcie_ep@3900000 {
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03900000 0x0 0x00100000
> + 0xa8 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <8>;
> + num-ib-windows = <8>;
> + status = "disabled";
> + };
> +
> smmu: iommu@5000000 {
> compatible = "arm,mmu-500";
> reg = <0 0x5000000 0 0x800000>;
> --
> 2.25.1
>
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next prev parent reply other threads:[~2021-12-14 5:42 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-03 23:54 [PATCH v2 00/10] lx216x DTS updates Li Yang
2021-12-03 23:54 ` [PATCH v2 01/10] arm64: dts: lx2160a: fix scl-gpios property name Li Yang
2021-12-14 5:33 ` Shawn Guo
2021-12-03 23:54 ` [PATCH v2 02/10] arm64: dts: lx2160a-rdb: Add Inphi PHY node Li Yang
2021-12-03 23:54 ` [PATCH v2 03/10] arm64: dts: lx2160a: add optee-tz node Li Yang
2021-12-03 23:54 ` [PATCH v2 04/10] arm64: dts: lx2160a-qds: Add mdio mux nodes Li Yang
2021-12-03 23:54 ` [PATCH v2 05/10] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon Li Yang
2021-12-14 5:39 ` Shawn Guo
2021-12-14 6:14 ` Leo Li
2021-12-03 23:54 ` [PATCH v2 06/10] arm64: dts: lx2160a: add pcie EP mode nodes Li Yang
2021-12-14 5:40 ` Shawn Guo [this message]
2021-12-03 23:54 ` [PATCH v2 07/10] arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodes Li Yang
2021-12-03 23:54 ` [PATCH v2 08/10] arm64: dts: lx2162a-qds: support SD UHS-I and eMMC HS400 modes Li Yang
2021-12-03 23:54 ` [PATCH v2 09/10] arm64: dts: lx2162a-qds: add interrupt line for RTC node Li Yang
2021-12-03 23:54 ` [PATCH v2 10/10] arm64: dts: lx2162a-qds: enable CAN nodes Li Yang
2021-12-06 5:58 ` Kuldeep Singh
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