From: Ard Biesheuvel <ardb@kernel.org>
To: linux@armlinux.org.uk, linux-arm-kernel@lists.infradead.org
Cc: linux-hardening@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Nicolas Pitre <nico@fluxnic.net>, Arnd Bergmann <arnd@arndb.de>,
Kees Cook <keescook@chromium.org>,
Keith Packard <keithpac@amazon.com>,
Linus Walleij <linus.walleij@linaro.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Tony Lindgren <tony@atomide.com>, Marc Zyngier <maz@kernel.org>,
Vladimir Murzin <vladimir.murzin@arm.com>,
Jesse Taube <mr.bossman075@gmail.com>,
Mark Rutland <mark.rutland@arm.com>
Subject: [PATCH v5 07/32] irqchip: nvic: Use GENERIC_IRQ_MULTI_HANDLER
Date: Mon, 24 Jan 2022 18:47:19 +0100 [thread overview]
Message-ID: <20220124174744.1054712-8-ardb@kernel.org> (raw)
In-Reply-To: <20220124174744.1054712-1-ardb@kernel.org>
From: Vladimir Murzin <vladimir.murzin@arm.com>
Rather then restructuring the ARMv7M entrly logic per TODO, just move
NVIC to GENERIC_IRQ_MULTI_HANDLER.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Marc Zyngier <maz@kernel.org>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
---
arch/arm/include/asm/v7m.h | 3 ++-
arch/arm/kernel/entry-v7m.S | 10 +++------
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-nvic.c | 22 +++++---------------
4 files changed, 11 insertions(+), 25 deletions(-)
diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
index 2cb00d15831b..4512f7e1918f 100644
--- a/arch/arm/include/asm/v7m.h
+++ b/arch/arm/include/asm/v7m.h
@@ -13,6 +13,7 @@
#define V7M_SCB_ICSR_PENDSVSET (1 << 28)
#define V7M_SCB_ICSR_PENDSVCLR (1 << 27)
#define V7M_SCB_ICSR_RETTOBASE (1 << 11)
+#define V7M_SCB_ICSR_VECTACTIVE 0x000001ff
#define V7M_SCB_VTOR 0x08
@@ -38,7 +39,7 @@
#define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16)
#define V7M_xPSR_FRAMEPTRALIGN 0x00000200
-#define V7M_xPSR_EXCEPTIONNO 0x000001ff
+#define V7M_xPSR_EXCEPTIONNO V7M_SCB_ICSR_VECTACTIVE
/*
* When branching to an address that has bits [31:28] == 0xf an exception return
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
index 7bde93c10962..520dd43e7e08 100644
--- a/arch/arm/kernel/entry-v7m.S
+++ b/arch/arm/kernel/entry-v7m.S
@@ -39,14 +39,10 @@ __irq_entry:
@
@ Invoke the IRQ handler
@
- mrs r0, ipsr
- ldr r1, =V7M_xPSR_EXCEPTIONNO
- and r0, r1
- sub r0, #16
- mov r1, sp
+ mov r0, sp
stmdb sp!, {lr}
- @ routine called with r0 = irq number, r1 = struct pt_regs *
- bl nvic_handle_irq
+ @ routine called with r0 = struct pt_regs *
+ bl generic_handle_arch_irq
pop {lr}
@
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7038957f4a77..488eaa14d3a7 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -58,6 +58,7 @@ config ARM_NVIC
bool
select IRQ_DOMAIN_HIERARCHY
select GENERIC_IRQ_CHIP
+ select GENERIC_IRQ_MULTI_HANDLER
config ARM_VIC
bool
diff --git a/drivers/irqchip/irq-nvic.c b/drivers/irqchip/irq-nvic.c
index ba4759b3e269..125f9c1cf0c3 100644
--- a/drivers/irqchip/irq-nvic.c
+++ b/drivers/irqchip/irq-nvic.c
@@ -37,25 +37,12 @@
static struct irq_domain *nvic_irq_domain;
-static void __nvic_handle_irq(irq_hw_number_t hwirq)
+static void __irq_entry nvic_handle_irq(struct pt_regs *regs)
{
- generic_handle_domain_irq(nvic_irq_domain, hwirq);
-}
+ unsigned long icsr = readl_relaxed(BASEADDR_V7M_SCB + V7M_SCB_ICSR);
+ irq_hw_number_t hwirq = (icsr & V7M_SCB_ICSR_VECTACTIVE) - 16;
-/*
- * TODO: restructure the ARMv7M entry logic so that this entry logic can live
- * in arch code.
- */
-asmlinkage void __exception_irq_entry
-nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
-{
- struct pt_regs *old_regs;
-
- irq_enter();
- old_regs = set_irq_regs(regs);
- __nvic_handle_irq(hwirq);
- set_irq_regs(old_regs);
- irq_exit();
+ generic_handle_domain_irq(nvic_irq_domain, hwirq);
}
static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
@@ -141,6 +128,7 @@ static int __init nvic_of_init(struct device_node *node,
for (i = 0; i < irqs; i += 4)
writel_relaxed(0, nvic_base + NVIC_IPR + i);
+ set_handle_irq(nvic_handle_irq);
return 0;
}
IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);
--
2.30.2
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next prev parent reply other threads:[~2022-01-24 17:52 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 17:47 [PATCH v5 00/32] ARM vmap'ed and IRQ stacks roundup Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 01/32] ARM: riscpc: drop support for IOMD_IRQREQC/IOMD_IRQREQD IRQ groups Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 02/32] ARM: riscpc: use GENERIC_IRQ_MULTI_HANDLER Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 03/32] ARM: footbridge: " Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 04/32] ARM: iop32x: offset IRQ numbers by 1 Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 05/32] ARM: iop32x: use GENERIC_IRQ_MULTI_HANDLER Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 06/32] ARM: remove old-style irq entry Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel [this message]
2022-01-24 17:47 ` [PATCH v5 08/32] ARM: decompressor: disable stack protector Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 09/32] ARM: stackprotector: prefer compiler for TLS based per-task protector Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 10/32] ARM: entry: preserve thread_info pointer in switch_to Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 11/32] ARM: module: implement support for PC-relative group relocations Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 12/32] ARM: assembler: add optimized ldr/str macros to load variables from memory Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 13/32] ARM: percpu: add SMP_ON_UP support Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 14/32] ARM: use TLS register for 'current' on !SMP as well Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 15/32] ARM: smp: defer TPIDRURO update for SMP v6 configurations too Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 16/32] ARM: implement THREAD_INFO_IN_TASK for uniprocessor systems Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 17/32] ARM: assembler: introduce bl_r macro Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 18/32] ARM: unwind: support unwinding across multiple stacks Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 19/32] ARM: export dump_mem() to other objects Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 20/32] ARM: unwind: dump exception stack from calling frame Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 21/32] ARM: backtrace-clang: avoid crash on bogus frame pointer Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 22/32] ARM: implement IRQ stacks Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 23/32] ARM: call_with_stack: add unwind support Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 24/32] ARM: run softirqs on the per-CPU IRQ stack Ard Biesheuvel
2022-03-22 9:04 ` Sebastian Andrzej Siewior
2022-03-22 9:35 ` Ard Biesheuvel
2022-03-22 11:29 ` Sebastian Andrzej Siewior
2022-01-24 17:47 ` [PATCH v5 25/32] ARM: memcpy: use frame pointer as unwind anchor Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 26/32] ARM: memmove: " Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 27/32] ARM: memset: clean up unwind annotations Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 28/32] ARM: unwind: disregard unwind info before stack frame is set up Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 29/32] ARM: entry: rework stack realignment code in svc_entry Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 30/32] ARM: switch_to: clean up Thumb2 code path Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 31/32] ARM: mm: prepare vmalloc_seq handling for use under SMP Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 32/32] ARM: implement support for vmap'ed stacks Ard Biesheuvel
2022-01-24 17:56 ` [PATCH v5 00/32] ARM vmap'ed and IRQ stacks roundup Russell King (Oracle)
2022-01-24 17:57 ` Ard Biesheuvel
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