* [PATCH v7 01/24] drm/rockchip: Embed drm_encoder into rockchip_decoder
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 02/24] drm/rockchip: Add crtc_endpoint_id to rockchip_encoder Sascha Hauer
` (22 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
The VOP2 driver needs rockchip specific information for a drm_encoder.
This patch creates a struct rockchip_encoder with a struct drm_encoder
embedded in it. This is used throughout the rockchip driver instead of
struct drm_encoder directly.
The information the VOP2 drivers needs is the of_graph endpoint node
of the encoder. To ease bisectability this is added here.
While at it convert the different encoder-to-driverdata macros to
static inline functions in order to gain type safety and readability.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Notes:
Changes since v5:
- new patch
.../gpu/drm/rockchip/analogix_dp-rockchip.c | 32 +++++++++++------
drivers/gpu/drm/rockchip/cdn-dp-core.c | 18 ++++++----
drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +-
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 17 ++++++----
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 11 ++++--
drivers/gpu/drm/rockchip/inno_hdmi.c | 32 +++++++++++------
drivers/gpu/drm/rockchip/rk3066_hdmi.c | 34 ++++++++++++-------
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 10 ++++++
drivers/gpu/drm/rockchip/rockchip_lvds.c | 26 ++++++++------
9 files changed, 122 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 8abb5ac26807e..bb33c6c217f77 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -40,8 +40,6 @@
#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
-#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
-
/**
* struct rockchip_dp_chip_data - splite the grf setting of kind of chips
* @lcdsel_grf_reg: grf register offset of lcdc select
@@ -59,7 +57,7 @@ struct rockchip_dp_chip_data {
struct rockchip_dp_device {
struct drm_device *drm_dev;
struct device *dev;
- struct drm_encoder encoder;
+ struct rockchip_encoder encoder;
struct drm_display_mode mode;
struct clk *pclk;
@@ -73,6 +71,18 @@ struct rockchip_dp_device {
struct analogix_dp_plat_data plat_data;
};
+static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder)
+{
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+
+ return container_of(rkencoder, struct rockchip_dp_device, encoder);
+}
+
+static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data)
+{
+ return container_of(plat_data, struct rockchip_dp_device, plat_data);
+}
+
static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
{
reset_control_assert(dp->rst);
@@ -84,7 +94,7 @@ static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data)
{
- struct rockchip_dp_device *dp = to_dp(plat_data);
+ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
int ret;
ret = clk_prepare_enable(dp->pclk);
@@ -105,7 +115,7 @@ static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data)
static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
{
- struct rockchip_dp_device *dp = to_dp(plat_data);
+ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
clk_disable_unprepare(dp->pclk);
@@ -166,7 +176,7 @@ struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder,
static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
struct drm_atomic_state *state)
{
- struct rockchip_dp_device *dp = to_dp(encoder);
+ struct rockchip_dp_device *dp = encoder_to_dp(encoder);
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state;
int ret;
@@ -208,7 +218,7 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
struct drm_atomic_state *state)
{
- struct rockchip_dp_device *dp = to_dp(encoder);
+ struct rockchip_dp_device *dp = encoder_to_dp(encoder);
struct drm_crtc *crtc;
struct drm_crtc_state *new_crtc_state = NULL;
int ret;
@@ -297,7 +307,7 @@ static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
{
- struct drm_encoder *encoder = &dp->encoder;
+ struct drm_encoder *encoder = &dp->encoder.encoder;
struct drm_device *drm_dev = dp->drm_dev;
struct device *dev = dp->dev;
int ret;
@@ -333,7 +343,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
return ret;
}
- dp->plat_data.encoder = &dp->encoder;
+ dp->plat_data.encoder = &dp->encoder.encoder;
ret = analogix_dp_bind(dp->adp, drm_dev);
if (ret)
@@ -341,7 +351,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
return 0;
err_cleanup_encoder:
- dp->encoder.funcs->destroy(&dp->encoder);
+ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
return ret;
}
@@ -351,7 +361,7 @@ static void rockchip_dp_unbind(struct device *dev, struct device *master,
struct rockchip_dp_device *dp = dev_get_drvdata(dev);
analogix_dp_unbind(dp->adp);
- dp->encoder.funcs->destroy(&dp->encoder);
+ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
}
static const struct component_ops rockchip_dp_component_ops = {
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c
index 16497c31d9f91..6ce1c1cdd9d68 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@ -26,11 +26,17 @@
#include "cdn-dp-reg.h"
#include "rockchip_drm_vop.h"
-#define connector_to_dp(c) \
- container_of(c, struct cdn_dp_device, connector)
+static inline struct cdn_dp_device *connector_to_dp(struct drm_connector *connector)
+{
+ return container_of(connector, struct cdn_dp_device, connector);
+}
-#define encoder_to_dp(c) \
- container_of(c, struct cdn_dp_device, encoder)
+static inline struct cdn_dp_device *encoder_to_dp(struct drm_encoder *encoder)
+{
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+
+ return container_of(rkencoder, struct cdn_dp_device, encoder);
+}
#define GRF_SOC_CON9 0x6224
#define DP_SEL_VOP_LIT BIT(12)
@@ -1022,7 +1028,7 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data)
INIT_WORK(&dp->event_work, cdn_dp_pd_event_work);
- encoder = &dp->encoder;
+ encoder = &dp->encoder.encoder;
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
dev->of_node);
@@ -1087,7 +1093,7 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data)
static void cdn_dp_unbind(struct device *dev, struct device *master, void *data)
{
struct cdn_dp_device *dp = dev_get_drvdata(dev);
- struct drm_encoder *encoder = &dp->encoder;
+ struct drm_encoder *encoder = &dp->encoder.encoder;
struct drm_connector *connector = &dp->connector;
cancel_work_sync(&dp->event_work);
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.h b/drivers/gpu/drm/rockchip/cdn-dp-core.h
index 81ac9b658a70a..29539170d3b1b 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.h
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h
@@ -65,7 +65,7 @@ struct cdn_dp_device {
struct device *dev;
struct drm_device *drm_dev;
struct drm_connector connector;
- struct drm_encoder encoder;
+ struct rockchip_encoder encoder;
struct drm_display_mode mode;
struct platform_device *audio_pdev;
struct work_struct event_work;
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 4ed7a68681978..110e83aad9bb4 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -181,8 +181,6 @@
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
-#define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm)
-
enum {
DW_DSI_USAGE_IDLE,
DW_DSI_USAGE_DSI,
@@ -236,7 +234,7 @@ struct rockchip_dw_dsi_chip_data {
struct dw_mipi_dsi_rockchip {
struct device *dev;
- struct drm_encoder encoder;
+ struct rockchip_encoder encoder;
void __iomem *base;
struct regmap *grf_regmap;
@@ -271,6 +269,13 @@ struct dw_mipi_dsi_rockchip {
bool dsi_bound;
};
+static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder)
+{
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+
+ return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder);
+}
+
struct dphy_pll_parameter_map {
unsigned int max_mbps;
u8 hsfreqrange;
@@ -770,7 +775,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
int ret, mux;
mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
- &dsi->encoder);
+ &dsi->encoder.encoder);
if (mux < 0)
return;
@@ -801,7 +806,7 @@ dw_mipi_dsi_encoder_helper_funcs = {
static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
struct drm_device *drm_dev)
{
- struct drm_encoder *encoder = &dsi->encoder;
+ struct drm_encoder *encoder = &dsi->encoder.encoder;
int ret;
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
@@ -959,7 +964,7 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
goto out_pll_clk;
}
- ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
+ ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder);
if (ret) {
DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
goto out_pll_clk;
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 8677c82716784..06c9ddef6f362 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -67,7 +67,7 @@ struct rockchip_hdmi_chip_data {
struct rockchip_hdmi {
struct device *dev;
struct regmap *regmap;
- struct drm_encoder encoder;
+ struct rockchip_encoder encoder;
const struct rockchip_hdmi_chip_data *chip_data;
struct clk *vpll_clk;
struct clk *grf_clk;
@@ -75,7 +75,12 @@ struct rockchip_hdmi {
struct phy *phy;
};
-#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
+static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
+{
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+
+ return container_of(rkencoder, struct rockchip_hdmi, encoder);
+}
static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
{
@@ -511,7 +516,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
hdmi->dev = &pdev->dev;
hdmi->chip_data = plat_data->phy_data;
plat_data->phy_data = hdmi;
- encoder = &hdmi->encoder;
+ encoder = &hdmi->encoder.encoder;
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
/*
diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c
index 046e8ec2a71c5..0a4f72021d6af 100644
--- a/drivers/gpu/drm/rockchip/inno_hdmi.c
+++ b/drivers/gpu/drm/rockchip/inno_hdmi.c
@@ -26,8 +26,6 @@
#include "inno_hdmi.h"
-#define to_inno_hdmi(x) container_of(x, struct inno_hdmi, x)
-
struct hdmi_data_info {
int vic;
bool sink_is_hdmi;
@@ -56,7 +54,7 @@ struct inno_hdmi {
void __iomem *regs;
struct drm_connector connector;
- struct drm_encoder encoder;
+ struct rockchip_encoder encoder;
struct inno_hdmi_i2c *i2c;
struct i2c_adapter *ddc;
@@ -67,6 +65,18 @@ struct inno_hdmi {
struct drm_display_mode previous_mode;
};
+static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder)
+{
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+
+ return container_of(rkencoder, struct inno_hdmi, encoder);
+}
+
+static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector)
+{
+ return container_of(connector, struct inno_hdmi, connector);
+}
+
enum {
CSC_ITU601_16_235_TO_RGB_0_255_8BIT,
CSC_ITU601_0_255_TO_RGB_0_255_8BIT,
@@ -483,7 +493,7 @@ static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adj_mode)
{
- struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
inno_hdmi_setup(hdmi, adj_mode);
@@ -493,14 +503,14 @@ static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder,
static void inno_hdmi_encoder_enable(struct drm_encoder *encoder)
{
- struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
inno_hdmi_set_pwr_mode(hdmi, NORMAL);
}
static void inno_hdmi_encoder_disable(struct drm_encoder *encoder)
{
- struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR);
}
@@ -536,7 +546,7 @@ static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = {
static enum drm_connector_status
inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
{
- struct inno_hdmi *hdmi = to_inno_hdmi(connector);
+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
connector_status_connected : connector_status_disconnected;
@@ -544,7 +554,7 @@ inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
{
- struct inno_hdmi *hdmi = to_inno_hdmi(connector);
+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
struct edid *edid;
int ret = 0;
@@ -599,7 +609,7 @@ static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
{
- struct drm_encoder *encoder = &hdmi->encoder;
+ struct drm_encoder *encoder = &hdmi->encoder.encoder;
struct device *dev = hdmi->dev;
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
@@ -879,7 +889,7 @@ static int inno_hdmi_bind(struct device *dev, struct device *master,
return 0;
err_cleanup_hdmi:
hdmi->connector.funcs->destroy(&hdmi->connector);
- hdmi->encoder.funcs->destroy(&hdmi->encoder);
+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
err_put_adapter:
i2c_put_adapter(hdmi->ddc);
err_disable_clk:
@@ -893,7 +903,7 @@ static void inno_hdmi_unbind(struct device *dev, struct device *master,
struct inno_hdmi *hdmi = dev_get_drvdata(dev);
hdmi->connector.funcs->destroy(&hdmi->connector);
- hdmi->encoder.funcs->destroy(&hdmi->encoder);
+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
i2c_put_adapter(hdmi->ddc);
clk_disable_unprepare(hdmi->pclk);
diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
index 1c546c3a89984..319240c33dcc0 100644
--- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c
+++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
@@ -47,7 +47,7 @@ struct rk3066_hdmi {
void __iomem *regs;
struct drm_connector connector;
- struct drm_encoder encoder;
+ struct rockchip_encoder encoder;
struct rk3066_hdmi_i2c *i2c;
struct i2c_adapter *ddc;
@@ -58,7 +58,17 @@ struct rk3066_hdmi {
struct drm_display_mode previous_mode;
};
-#define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x)
+static struct rk3066_hdmi *encoder_to_rk3066_hdmi(struct drm_encoder *encoder)
+{
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+
+ return container_of(rkencoder, struct rk3066_hdmi, encoder);
+}
+
+static struct rk3066_hdmi *connector_to_rk3066_hdmi(struct drm_connector *connector)
+{
+ return container_of(connector, struct rk3066_hdmi, connector);
+}
static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
{
@@ -380,7 +390,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adj_mode)
{
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
/* Store the display mode for plugin/DPMS poweron events. */
memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
@@ -388,7 +398,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder,
static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder)
{
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
int mux, val;
mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
@@ -407,7 +417,7 @@ static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder)
static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder)
{
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n");
@@ -455,7 +465,7 @@ struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = {
static enum drm_connector_status
rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force)
{
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ?
connector_status_connected : connector_status_disconnected;
@@ -463,7 +473,7 @@ rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force)
static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector)
{
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
struct edid *edid;
int ret = 0;
@@ -496,9 +506,9 @@ rk3066_hdmi_connector_mode_valid(struct drm_connector *connector,
static struct drm_encoder *
rk3066_hdmi_connector_best_encoder(struct drm_connector *connector)
{
- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
- return &hdmi->encoder;
+ return &hdmi->encoder.encoder;
}
static int
@@ -538,7 +548,7 @@ struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = {
static int
rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi)
{
- struct drm_encoder *encoder = &hdmi->encoder;
+ struct drm_encoder *encoder = &hdmi->encoder.encoder;
struct device *dev = hdmi->dev;
encoder->possible_crtcs =
@@ -816,7 +826,7 @@ static int rk3066_hdmi_bind(struct device *dev, struct device *master,
err_cleanup_hdmi:
hdmi->connector.funcs->destroy(&hdmi->connector);
- hdmi->encoder.funcs->destroy(&hdmi->encoder);
+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
err_disable_i2c:
i2c_put_adapter(hdmi->ddc);
err_disable_hclk:
@@ -831,7 +841,7 @@ static void rk3066_hdmi_unbind(struct device *dev, struct device *master,
struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
hdmi->connector.funcs->destroy(&hdmi->connector);
- hdmi->encoder.funcs->destroy(&hdmi->encoder);
+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
i2c_put_adapter(hdmi->ddc);
clk_disable_unprepare(hdmi->hclk);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index 143a48330f849..686f687a76a37 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -48,6 +48,10 @@ struct rockchip_drm_private {
struct drm_mm mm;
};
+struct rockchip_encoder {
+ struct drm_encoder encoder;
+};
+
int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
struct device *dev);
void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
@@ -63,4 +67,10 @@ extern struct platform_driver rockchip_dp_driver;
extern struct platform_driver rockchip_lvds_driver;
extern struct platform_driver vop_platform_driver;
extern struct platform_driver rk3066_hdmi_driver;
+
+static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder)
+{
+ return container_of(encoder, struct rockchip_encoder, encoder);
+}
+
#endif /* _ROCKCHIP_DRM_DRV_H_ */
diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c
index be74c87a8be4d..4ced073c6b06c 100644
--- a/drivers/gpu/drm/rockchip/rockchip_lvds.c
+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
@@ -36,12 +36,6 @@
struct rockchip_lvds;
-#define connector_to_lvds(c) \
- container_of(c, struct rockchip_lvds, connector)
-
-#define encoder_to_lvds(c) \
- container_of(c, struct rockchip_lvds, encoder)
-
/**
* struct rockchip_lvds_soc_data - rockchip lvds Soc private data
* @probe: LVDS platform probe function
@@ -65,10 +59,22 @@ struct rockchip_lvds {
struct drm_panel *panel;
struct drm_bridge *bridge;
struct drm_connector connector;
- struct drm_encoder encoder;
+ struct rockchip_encoder encoder;
struct dev_pin_info *pins;
};
+static inline struct rockchip_lvds *connector_to_lvds(struct drm_connector *connector)
+{
+ return container_of(connector, struct rockchip_lvds, connector);
+}
+
+static inline struct rockchip_lvds *encoder_to_lvds(struct drm_encoder *encoder)
+{
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+
+ return container_of(rkencoder, struct rockchip_lvds, encoder);
+}
+
static inline void rk3288_writel(struct rockchip_lvds *lvds, u32 offset,
u32 val)
{
@@ -599,7 +605,7 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master,
goto err_put_remote;
}
- encoder = &lvds->encoder;
+ encoder = &lvds->encoder.encoder;
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
dev->of_node);
@@ -674,10 +680,10 @@ static void rockchip_lvds_unbind(struct device *dev, struct device *master,
const struct drm_encoder_helper_funcs *encoder_funcs;
encoder_funcs = lvds->soc_data->helper_funcs;
- encoder_funcs->disable(&lvds->encoder);
+ encoder_funcs->disable(&lvds->encoder.encoder);
pm_runtime_disable(dev);
drm_connector_cleanup(&lvds->connector);
- drm_encoder_cleanup(&lvds->encoder);
+ drm_encoder_cleanup(&lvds->encoder.encoder);
}
static const struct component_ops rockchip_lvds_component_ops = {
--
2.30.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 02/24] drm/rockchip: Add crtc_endpoint_id to rockchip_encoder
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 01/24] drm/rockchip: Embed drm_encoder into rockchip_decoder Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 03/24] drm/rockchip: dw_hdmi: rename vpll clock to reference clock Sascha Hauer
` (21 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
The VOP2 has an interface mux which decides to which encoder(s) a CRTC
is routed to. The encoders and CRTCs are connected via of_graphs in the
device tree. When given an encoder the VOP2 driver needs to know to
which internal register setting this encoder matches. For this the VOP2
binding offers different endpoints, one for each possible encoder. The
endpoint ids of these endpoints are used as a key from an encoders
device tree description to the internal register setting.
This patch adds the key aka endpoint id to struct rockchip_encoder plus
a function to read the endpoint id starting from the encoders device
node.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Notes:
Changes since v6:
- new patch
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 33 +++++++++++++++++++++
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 4 ++-
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index bec207de45440..7920a4f44f693 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -236,6 +236,39 @@ static const struct dev_pm_ops rockchip_drm_pm_ops = {
static struct platform_driver *rockchip_sub_drivers[MAX_ROCKCHIP_SUB_DRIVERS];
static int num_rockchip_sub_drivers;
+/*
+ * Get the endpoint id of the remote endpoint of the given encoder. This
+ * information is used by the VOP2 driver to identify the encoder.
+ *
+ * @rkencoder: The encoder to get the remote endpoint id from
+ * @np: The encoder device node
+ * @port: The number of the port leading to the VOP2
+ * @reg: The endpoint number leading to the VOP2
+ */
+int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rkencoder,
+ struct device_node *np, int port, int reg)
+{
+ struct of_endpoint ep;
+ struct device_node *en, *ren;
+ int ret;
+
+ en = of_graph_get_endpoint_by_regs(np, port, reg);
+ if (!en)
+ return -ENOENT;
+
+ ren = of_graph_get_remote_endpoint(en);
+ if (!ren)
+ return -ENOENT;
+
+ ret = of_graph_parse_endpoint(ren, &ep);
+ if (ret)
+ return ret;
+
+ rkencoder->crtc_endpoint_id = ep.id;
+
+ return 0;
+}
+
/*
* Check if a vop endpoint is leading to a rockchip subdriver or bridge.
* Should be called from the component bind stage of the drivers
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index 686f687a76a37..1f66a447acada 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -49,6 +49,7 @@ struct rockchip_drm_private {
};
struct rockchip_encoder {
+ int crtc_endpoint_id;
struct drm_encoder encoder;
};
@@ -57,7 +58,8 @@ int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
struct device *dev);
int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout);
-
+int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rencoder,
+ struct device_node *np, int port, int reg);
int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
extern struct platform_driver cdn_dp_driver;
extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 03/24] drm/rockchip: dw_hdmi: rename vpll clock to reference clock
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 01/24] drm/rockchip: Embed drm_encoder into rockchip_decoder Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 02/24] drm/rockchip: Add crtc_endpoint_id to rockchip_encoder Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-28 10:59 ` Dmitry Osipenko
2022-02-25 7:51 ` [PATCH v7 04/24] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name Sascha Hauer
` (20 subsequent siblings)
23 siblings, 1 reply; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
"vpll" is a misnomer. A clock input to a device should be named after
the usage in the device, not after the clock that drives it. On the
rk3568 the same clock is driven by the HPLL.
To fix that, this patch renames the vpll clock to ref clock. The clock
name "vpll" is left for compatibility to old device trees.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Notes:
Changes since v6:
- Simplify by using devm_clk_get_optional() instead of devm_clk_get()
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 27 +++++++++++----------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 06c9ddef6f362..912181429880a 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -69,7 +69,7 @@ struct rockchip_hdmi {
struct regmap *regmap;
struct rockchip_encoder encoder;
const struct rockchip_hdmi_chip_data *chip_data;
- struct clk *vpll_clk;
+ struct clk *ref_clk;
struct clk *grf_clk;
struct dw_hdmi *hdmi;
struct phy *phy;
@@ -201,14 +201,15 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
return PTR_ERR(hdmi->regmap);
}
- hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
- if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
- hdmi->vpll_clk = NULL;
- } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref");
+ if (!hdmi->ref_clk)
+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll");
+
+ if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) {
return -EPROBE_DEFER;
- } else if (IS_ERR(hdmi->vpll_clk)) {
- DRM_DEV_ERROR(hdmi->dev, "failed to get vpll clock\n");
- return PTR_ERR(hdmi->vpll_clk);
+ } else if (IS_ERR(hdmi->ref_clk)) {
+ DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n");
+ return PTR_ERR(hdmi->ref_clk);
}
hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
@@ -262,7 +263,7 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
{
struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
- clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
+ clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
}
static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
@@ -542,9 +543,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
return ret;
}
- ret = clk_prepare_enable(hdmi->vpll_clk);
+ ret = clk_prepare_enable(hdmi->ref_clk);
if (ret) {
- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
ret);
return ret;
}
@@ -563,7 +564,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
if (IS_ERR(hdmi->hdmi)) {
ret = PTR_ERR(hdmi->hdmi);
drm_encoder_cleanup(encoder);
- clk_disable_unprepare(hdmi->vpll_clk);
+ clk_disable_unprepare(hdmi->ref_clk);
}
return ret;
@@ -575,7 +576,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
dw_hdmi_unbind(hdmi->hdmi);
- clk_disable_unprepare(hdmi->vpll_clk);
+ clk_disable_unprepare(hdmi->ref_clk);
}
static const struct component_ops dw_hdmi_rockchip_ops = {
--
2.30.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v7 03/24] drm/rockchip: dw_hdmi: rename vpll clock to reference clock
2022-02-25 7:51 ` [PATCH v7 03/24] drm/rockchip: dw_hdmi: rename vpll clock to reference clock Sascha Hauer
@ 2022-02-28 10:59 ` Dmitry Osipenko
0 siblings, 0 replies; 56+ messages in thread
From: Dmitry Osipenko @ 2022-02-28 10:59 UTC (permalink / raw)
To: Sascha Hauer, dri-devel
Cc: devicetree, Benjamin Gaignard, Peter Geis, Sandy Huang,
linux-rockchip, Michael Riesch, kernel, Andy Yan,
linux-arm-kernel
On 2/25/22 10:51, Sascha Hauer wrote:
> "vpll" is a misnomer. A clock input to a device should be named after
> the usage in the device, not after the clock that drives it. On the
> rk3568 the same clock is driven by the HPLL.
> To fix that, this patch renames the vpll clock to ref clock. The clock
> name "vpll" is left for compatibility to old device trees.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>
> Notes:
> Changes since v6:
> - Simplify by using devm_clk_get_optional() instead of devm_clk_get()
>
> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 27 +++++++++++----------
> 1 file changed, 14 insertions(+), 13 deletions(-)
Looks nice now. Thank you!
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v7 04/24] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (2 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 03/24] drm/rockchip: dw_hdmi: rename vpll clock to reference clock Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 05/24] arm64: dts: rockchip: rk3399: rename HDMI ref clock to 'ref' Sascha Hauer
` (19 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer, Rob Herring
"vpll" is a misnomer. A clock input to a device should be named after
the usage in the device, not after the clock that drives it. On the
rk3568 the same clock is driven by the HPLL.
This patch adds "ref" as a new alternative clock name for "vpll"
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes since v4:
- Add Robs Ack
Changes since v3:
- Keep old clock name for compatibility reasons
.../bindings/display/rockchip/rockchip,dw-hdmi.yaml | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index da3b889ad8fcd..0400f67e5f2c9 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -36,7 +36,8 @@ properties:
# order when present.
- description: The HDMI CEC controller main clock
- description: Power for GRF IO
- - description: External clock for some HDMI PHY
+ - description: External clock for some HDMI PHY (old clock name, deprecated)
+ - description: External clock for some HDMI PHY (new name)
clock-names:
minItems: 2
@@ -47,10 +48,14 @@ properties:
- cec
- grf
- vpll
+ - ref
- enum:
- grf
- vpll
- - const: vpll
+ - ref
+ - enum:
+ - vpll
+ - ref
ddc-i2c-bus:
$ref: /schemas/types.yaml#/definitions/phandle
--
2.30.2
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^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 05/24] arm64: dts: rockchip: rk3399: rename HDMI ref clock to 'ref'
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (3 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 04/24] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 06/24] drm/rockchip: dw_hdmi: add rk3568 support Sascha Hauer
` (18 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
The reference clock for the HDMI controller has been renamed to 'ref',
the previous 'vpll' name is only left for compatibility in the driver.
Rename the clock to the new name.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 080457a68e3c7..d0add619b0d22 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1884,7 +1884,7 @@ hdmi: hdmi@ff940000 {
<&cru SCLK_HDMI_CEC>,
<&cru PCLK_VIO_GRF>,
<&cru PLL_VPLL>;
- clock-names = "iahb", "isfr", "cec", "grf", "vpll";
+ clock-names = "iahb", "isfr", "cec", "grf", "ref";
power-domains = <&power RK3399_PD_HDCP>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
--
2.30.2
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^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 06/24] drm/rockchip: dw_hdmi: add rk3568 support
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (4 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 05/24] arm64: dts: rockchip: rk3399: rename HDMI ref clock to 'ref' Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 07/24] dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568 HDMI Sascha Hauer
` (17 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
Add a new dw_hdmi_plat_data struct and new compatible for rk3568.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 31 +++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 912181429880a..b64cc62c7b5af 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -50,6 +50,10 @@
#define RK3399_GRF_SOC_CON20 0x6250
#define RK3399_HDMI_LCDC_SEL BIT(6)
+#define RK3568_GRF_VO_CON1 0x0364
+#define RK3568_HDMI_SDAIN_MSK BIT(15)
+#define RK3568_HDMI_SCLIN_MSK BIT(14)
+
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
/**
@@ -473,6 +477,19 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
.use_drm_infoframe = true,
};
+static struct rockchip_hdmi_chip_data rk3568_chip_data = {
+ .lcdsel_grf_reg = -1,
+};
+
+static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
+ .mode_valid = dw_hdmi_rockchip_mode_valid,
+ .mpll_cfg = rockchip_mpll_cfg,
+ .cur_ctr = rockchip_cur_ctr,
+ .phy_config = rockchip_phy_config,
+ .phy_data = &rk3568_chip_data,
+ .use_drm_infoframe = true,
+};
+
static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
{ .compatible = "rockchip,rk3228-dw-hdmi",
.data = &rk3228_hdmi_drv_data
@@ -486,6 +503,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
{ .compatible = "rockchip,rk3399-dw-hdmi",
.data = &rk3399_hdmi_drv_data
},
+ { .compatible = "rockchip,rk3568-dw-hdmi",
+ .data = &rk3568_hdmi_drv_data
+ },
{},
};
MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
@@ -520,6 +540,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
encoder = &hdmi->encoder.encoder;
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
+ rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder,
+ dev->of_node, 0, 0);
+
/*
* If we failed to find the CRTC(s) which this encoder is
* supposed to be connected to, it's because the CRTC has
@@ -550,6 +573,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
return ret;
}
+ if (hdmi->chip_data == &rk3568_chip_data) {
+ regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
+ HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
+ RK3568_HDMI_SCLIN_MSK,
+ RK3568_HDMI_SDAIN_MSK |
+ RK3568_HDMI_SCLIN_MSK));
+ }
+
drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
--
2.30.2
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^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 07/24] dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568 HDMI
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (5 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 06/24] drm/rockchip: dw_hdmi: add rk3568 support Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 08/24] drm/rockchip: dw_hdmi: add regulator support Sascha Hauer
` (16 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Rob Herring, Sascha Hauer
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Define a new compatible for rk3568 HDMI.
This version of HDMI hardware block needs two new clocks hclk_vio and hclk
to provide phy reference clocks.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index 0400f67e5f2c9..e6b8437a1e2d1 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -23,6 +23,7 @@ properties:
- rockchip,rk3288-dw-hdmi
- rockchip,rk3328-dw-hdmi
- rockchip,rk3399-dw-hdmi
+ - rockchip,rk3568-dw-hdmi
reg-io-width:
const: 4
--
2.30.2
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^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 08/24] drm/rockchip: dw_hdmi: add regulator support
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (6 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 07/24] dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568 HDMI Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 09/24] dt-bindings: display: rockchip: dw-hdmi: Add " Sascha Hauer
` (15 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer, Dmitry Osipenko
The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs needed
for the HDMI port. add support for these to the driver for boards which
have them supplied by switchable regulators.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++--
1 file changed, 38 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index b64cc62c7b5af..fe4f9556239ac 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -9,6 +9,7 @@
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
#include <drm/bridge/dw_hdmi.h>
#include <drm/drm_edid.h>
@@ -76,6 +77,8 @@ struct rockchip_hdmi {
struct clk *ref_clk;
struct clk *grf_clk;
struct dw_hdmi *hdmi;
+ struct regulator *avdd_0v9;
+ struct regulator *avdd_1v8;
struct phy *phy;
};
@@ -226,6 +229,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
return PTR_ERR(hdmi->grf_clk);
}
+ hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9");
+ if (IS_ERR(hdmi->avdd_0v9))
+ return PTR_ERR(hdmi->avdd_0v9);
+
+ hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8");
+ if (IS_ERR(hdmi->avdd_1v8))
+ return PTR_ERR(hdmi->avdd_1v8);
+
return 0;
}
@@ -566,11 +577,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
return ret;
}
+ ret = regulator_enable(hdmi->avdd_0v9);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret);
+ goto err_avdd_0v9;
+ }
+
+ ret = regulator_enable(hdmi->avdd_1v8);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret);
+ goto err_avdd_1v8;
+ }
+
ret = clk_prepare_enable(hdmi->ref_clk);
if (ret) {
DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
ret);
- return ret;
+ goto err_clk;
}
if (hdmi->chip_data == &rk3568_chip_data) {
@@ -594,10 +617,19 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
*/
if (IS_ERR(hdmi->hdmi)) {
ret = PTR_ERR(hdmi->hdmi);
- drm_encoder_cleanup(encoder);
- clk_disable_unprepare(hdmi->ref_clk);
+ goto err_bind;
}
+ return 0;
+
+err_bind:
+ clk_disable_unprepare(hdmi->ref_clk);
+ drm_encoder_cleanup(encoder);
+err_clk:
+ regulator_disable(hdmi->avdd_1v8);
+err_avdd_1v8:
+ regulator_disable(hdmi->avdd_0v9);
+err_avdd_0v9:
return ret;
}
@@ -608,6 +640,9 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
dw_hdmi_unbind(hdmi->hdmi);
clk_disable_unprepare(hdmi->ref_clk);
+
+ regulator_disable(hdmi->avdd_1v8);
+ regulator_disable(hdmi->avdd_0v9);
}
static const struct component_ops dw_hdmi_rockchip_ops = {
--
2.30.2
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^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 09/24] dt-bindings: display: rockchip: dw-hdmi: Add regulator support
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (7 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 08/24] drm/rockchip: dw_hdmi: add regulator support Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk Sascha Hauer
` (14 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer, Rob Herring
The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs
needed for the HDMI port. Add the binding for these supplies.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes since v4:
- Add Robs Ack
.../bindings/display/rockchip/rockchip,dw-hdmi.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index e6b8437a1e2d1..38ebb69830287 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -28,6 +28,17 @@ properties:
reg-io-width:
const: 4
+ avdd-0v9-supply:
+ description:
+ A 0.9V supply that powers up the SoC internal circuitry. The actual pin name
+ varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes
+ HDMI_AVDD_1V0.
+
+ avdd-1v8-supply:
+ description:
+ A 1.8V supply that powers up the SoC internal circuitry. The pin name on the
+ SoC usually is HDMI_TX_AVDD_1V8.
+
clocks:
minItems: 2
items:
--
2.30.2
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^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (8 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 09/24] dt-bindings: display: rockchip: dw-hdmi: Add " Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 10:26 ` Dmitry Osipenko
2022-02-25 7:51 ` [PATCH v7 11/24] dt-bindings: display: rockchip: dw-hdmi: Add additional clock Sascha Hauer
` (13 subsequent siblings)
23 siblings, 1 reply; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
The rk3568 HDMI has an additional clock that needs to be enabled for the
HDMI controller to work. The purpose of that clock is not clear. It is
named "hclk" in the downstream driver, so use the same name.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Notes:
Changes since v5:
- Use devm_clk_get_optional rather than devm_clk_get
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index fe4f9556239ac..c6c00e8779ab5 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -76,6 +76,7 @@ struct rockchip_hdmi {
const struct rockchip_hdmi_chip_data *chip_data;
struct clk *ref_clk;
struct clk *grf_clk;
+ struct clk *hclk_clk;
struct dw_hdmi *hdmi;
struct regulator *avdd_0v9;
struct regulator *avdd_1v8;
@@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
return PTR_ERR(hdmi->grf_clk);
}
+ hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
+ if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
+ return -EPROBE_DEFER;
+ } else if (IS_ERR(hdmi->hclk_clk)) {
+ DRM_DEV_ERROR(hdmi->dev, "failed to get hclk_clk clock\n");
+ return PTR_ERR(hdmi->hclk_clk);
+ }
+
hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9");
if (IS_ERR(hdmi->avdd_0v9))
return PTR_ERR(hdmi->avdd_0v9);
@@ -596,6 +605,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
goto err_clk;
}
+ ret = clk_prepare_enable(hdmi->hclk_clk);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI hclk clock: %d\n",
+ ret);
+ goto err_clk;
+ }
+
if (hdmi->chip_data == &rk3568_chip_data) {
regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
--
2.30.2
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^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-25 7:51 ` [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk Sascha Hauer
@ 2022-02-25 10:26 ` Dmitry Osipenko
2022-02-25 10:49 ` Sascha Hauer
0 siblings, 1 reply; 56+ messages in thread
From: Dmitry Osipenko @ 2022-02-25 10:26 UTC (permalink / raw)
To: Sascha Hauer, dri-devel
Cc: devicetree, Benjamin Gaignard, Peter Geis, Sandy Huang,
linux-rockchip, Michael Riesch, kernel, Andy Yan,
linux-arm-kernel
25.02.2022 10:51, Sascha Hauer пишет:
> The rk3568 HDMI has an additional clock that needs to be enabled for the
> HDMI controller to work. The purpose of that clock is not clear. It is
> named "hclk" in the downstream driver, so use the same name.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>
> Notes:
> Changes since v5:
> - Use devm_clk_get_optional rather than devm_clk_get
>
> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> index fe4f9556239ac..c6c00e8779ab5 100644
> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> @@ -76,6 +76,7 @@ struct rockchip_hdmi {
> const struct rockchip_hdmi_chip_data *chip_data;
> struct clk *ref_clk;
> struct clk *grf_clk;
> + struct clk *hclk_clk;
> struct dw_hdmi *hdmi;
> struct regulator *avdd_0v9;
> struct regulator *avdd_1v8;
> @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
> return PTR_ERR(hdmi->grf_clk);
> }
>
> + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
> + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
Have you tried to investigate the hclk? I'm still thinking that's not
only HDMI that needs this clock and then the hardware description
doesn't look correct.
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-25 10:26 ` Dmitry Osipenko
@ 2022-02-25 10:49 ` Sascha Hauer
2022-02-25 11:10 ` Dmitry Osipenko
0 siblings, 1 reply; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 10:49 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: dri-devel, devicetree, Benjamin Gaignard, Peter Geis,
Sandy Huang, linux-rockchip, Michael Riesch, kernel, Andy Yan,
linux-arm-kernel
On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
> 25.02.2022 10:51, Sascha Hauer пишет:
> > The rk3568 HDMI has an additional clock that needs to be enabled for the
> > HDMI controller to work. The purpose of that clock is not clear. It is
> > named "hclk" in the downstream driver, so use the same name.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >
> > Notes:
> > Changes since v5:
> > - Use devm_clk_get_optional rather than devm_clk_get
> >
> > drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > index fe4f9556239ac..c6c00e8779ab5 100644
> > --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > @@ -76,6 +76,7 @@ struct rockchip_hdmi {
> > const struct rockchip_hdmi_chip_data *chip_data;
> > struct clk *ref_clk;
> > struct clk *grf_clk;
> > + struct clk *hclk_clk;
> > struct dw_hdmi *hdmi;
> > struct regulator *avdd_0v9;
> > struct regulator *avdd_1v8;
> > @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
> > return PTR_ERR(hdmi->grf_clk);
> > }
> >
> > + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
> > + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
>
> Have you tried to investigate the hclk? I'm still thinking that's not
> only HDMI that needs this clock and then the hardware description
> doesn't look correct.
I am still not sure what you mean. Yes, it's not only the HDMI that
needs this clock. The VOP2 needs it as well and the driver handles that.
Sascha
--
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Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-25 10:49 ` Sascha Hauer
@ 2022-02-25 11:10 ` Dmitry Osipenko
2022-02-25 11:37 ` Sascha Hauer
2022-02-25 12:41 ` Robin Murphy
0 siblings, 2 replies; 56+ messages in thread
From: Dmitry Osipenko @ 2022-02-25 11:10 UTC (permalink / raw)
To: Sascha Hauer
Cc: dri-devel, devicetree, Benjamin Gaignard, Peter Geis,
Sandy Huang, linux-rockchip, Michael Riesch, kernel, Andy Yan,
linux-arm-kernel
25.02.2022 13:49, Sascha Hauer пишет:
> On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
>> 25.02.2022 10:51, Sascha Hauer пишет:
>>> The rk3568 HDMI has an additional clock that needs to be enabled for the
>>> HDMI controller to work. The purpose of that clock is not clear. It is
>>> named "hclk" in the downstream driver, so use the same name.
>>>
>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>> ---
>>>
>>> Notes:
>>> Changes since v5:
>>> - Use devm_clk_get_optional rather than devm_clk_get
>>>
>>> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
>>> 1 file changed, 16 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>> index fe4f9556239ac..c6c00e8779ab5 100644
>>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>> @@ -76,6 +76,7 @@ struct rockchip_hdmi {
>>> const struct rockchip_hdmi_chip_data *chip_data;
>>> struct clk *ref_clk;
>>> struct clk *grf_clk;
>>> + struct clk *hclk_clk;
>>> struct dw_hdmi *hdmi;
>>> struct regulator *avdd_0v9;
>>> struct regulator *avdd_1v8;
>>> @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
>>> return PTR_ERR(hdmi->grf_clk);
>>> }
>>>
>>> + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
>>> + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
>>
>> Have you tried to investigate the hclk? I'm still thinking that's not
>> only HDMI that needs this clock and then the hardware description
>> doesn't look correct.
>
> I am still not sure what you mean. Yes, it's not only the HDMI that
> needs this clock. The VOP2 needs it as well and the driver handles that.
I'm curious whether DSI/DP also need that clock to be enabled. If they
do, then you aren't modeling h/w properly AFAICS.
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-25 11:10 ` Dmitry Osipenko
@ 2022-02-25 11:37 ` Sascha Hauer
2022-02-25 12:41 ` Robin Murphy
1 sibling, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 11:37 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: dri-devel, devicetree, Benjamin Gaignard, Peter Geis,
Sandy Huang, linux-rockchip, Michael Riesch, kernel, Andy Yan,
linux-arm-kernel
On Fri, Feb 25, 2022 at 02:10:55PM +0300, Dmitry Osipenko wrote:
> 25.02.2022 13:49, Sascha Hauer пишет:
> > On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
> >> 25.02.2022 10:51, Sascha Hauer пишет:
> >>> The rk3568 HDMI has an additional clock that needs to be enabled for the
> >>> HDMI controller to work. The purpose of that clock is not clear. It is
> >>> named "hclk" in the downstream driver, so use the same name.
> >>>
> >>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> >>> ---
> >>>
> >>> Notes:
> >>> Changes since v5:
> >>> - Use devm_clk_get_optional rather than devm_clk_get
> >>>
> >>> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
> >>> 1 file changed, 16 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> >>> index fe4f9556239ac..c6c00e8779ab5 100644
> >>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> >>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> >>> @@ -76,6 +76,7 @@ struct rockchip_hdmi {
> >>> const struct rockchip_hdmi_chip_data *chip_data;
> >>> struct clk *ref_clk;
> >>> struct clk *grf_clk;
> >>> + struct clk *hclk_clk;
> >>> struct dw_hdmi *hdmi;
> >>> struct regulator *avdd_0v9;
> >>> struct regulator *avdd_1v8;
> >>> @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
> >>> return PTR_ERR(hdmi->grf_clk);
> >>> }
> >>>
> >>> + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
> >>> + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
> >>
> >> Have you tried to investigate the hclk? I'm still thinking that's not
> >> only HDMI that needs this clock and then the hardware description
> >> doesn't look correct.
> >
> > I am still not sure what you mean. Yes, it's not only the HDMI that
> > needs this clock. The VOP2 needs it as well and the driver handles that.
>
> I'm curious whether DSI/DP also need that clock to be enabled. If they
> do, then you aren't modeling h/w properly AFAICS.
Indeed I can confirm that DSI and DP need that clock enabled for
register access as well. Do you think these devices should be under an
additional bus layer in the device tree which drives the clock? Or
should HCLK_VOP be enabled as part of the RK3568_PD_VO power domain?
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-25 11:10 ` Dmitry Osipenko
2022-02-25 11:37 ` Sascha Hauer
@ 2022-02-25 12:41 ` Robin Murphy
2022-02-25 13:11 ` Sascha Hauer
1 sibling, 1 reply; 56+ messages in thread
From: Robin Murphy @ 2022-02-25 12:41 UTC (permalink / raw)
To: Dmitry Osipenko, Sascha Hauer
Cc: dri-devel, devicetree, Benjamin Gaignard, Peter Geis,
Sandy Huang, linux-rockchip, Michael Riesch, kernel, Andy Yan,
linux-arm-kernel
On 2022-02-25 11:10, Dmitry Osipenko wrote:
> 25.02.2022 13:49, Sascha Hauer пишет:
>> On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
>>> 25.02.2022 10:51, Sascha Hauer пишет:
>>>> The rk3568 HDMI has an additional clock that needs to be enabled for the
>>>> HDMI controller to work. The purpose of that clock is not clear. It is
>>>> named "hclk" in the downstream driver, so use the same name.
>>>>
>>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>>> ---
>>>>
>>>> Notes:
>>>> Changes since v5:
>>>> - Use devm_clk_get_optional rather than devm_clk_get
>>>>
>>>> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
>>>> 1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>> index fe4f9556239ac..c6c00e8779ab5 100644
>>>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>> @@ -76,6 +76,7 @@ struct rockchip_hdmi {
>>>> const struct rockchip_hdmi_chip_data *chip_data;
>>>> struct clk *ref_clk;
>>>> struct clk *grf_clk;
>>>> + struct clk *hclk_clk;
>>>> struct dw_hdmi *hdmi;
>>>> struct regulator *avdd_0v9;
>>>> struct regulator *avdd_1v8;
>>>> @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
>>>> return PTR_ERR(hdmi->grf_clk);
>>>> }
>>>>
>>>> + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
>>>> + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
>>>
>>> Have you tried to investigate the hclk? I'm still thinking that's not
>>> only HDMI that needs this clock and then the hardware description
>>> doesn't look correct.
>>
>> I am still not sure what you mean. Yes, it's not only the HDMI that
>> needs this clock. The VOP2 needs it as well and the driver handles that.
>
> I'm curious whether DSI/DP also need that clock to be enabled. If they
> do, then you aren't modeling h/w properly AFAICS.
Assuming nobody at Rockchip decided to make things needlessly
inconsistent with previous SoCs, HCLK_VOP should be the clock for the
VOP's AHB slave interface. Usually, if that affected anything other than
accessing VOP registers, indeed it would smell of something being wrong
in the clock tree, but in this case I'd also be suspicious of whether it
might have ended up clocking related GRF registers as well (either
directly, or indirectly via some gate that the clock driver hasn't
modelled yet).
If the symptom of not claiming HCLK_VOP is hanging on some register
access in the HDMI driver while the VOP is idle, then it should be
relatively straightforward to narrow down with some logging, and see if
it looks like this is really just another "grf" clock. If not, then
we're back to suspecting something more insidiously wrong elsewhere.
Robin.
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-25 12:41 ` Robin Murphy
@ 2022-02-25 13:11 ` Sascha Hauer
2022-02-25 13:33 ` Robin Murphy
2022-02-28 14:19 ` Sascha Hauer
0 siblings, 2 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 13:11 UTC (permalink / raw)
To: Robin Murphy
Cc: Dmitry Osipenko, dri-devel, devicetree, Benjamin Gaignard,
Peter Geis, Sandy Huang, linux-rockchip, Michael Riesch, kernel,
Andy Yan, linux-arm-kernel
On Fri, Feb 25, 2022 at 12:41:23PM +0000, Robin Murphy wrote:
> On 2022-02-25 11:10, Dmitry Osipenko wrote:
> > 25.02.2022 13:49, Sascha Hauer пишет:
> > > On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
> > > > 25.02.2022 10:51, Sascha Hauer пишет:
> > > > > The rk3568 HDMI has an additional clock that needs to be enabled for the
> > > > > HDMI controller to work. The purpose of that clock is not clear. It is
> > > > > named "hclk" in the downstream driver, so use the same name.
> > > > >
> > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > > > ---
> > > > >
> > > > > Notes:
> > > > > Changes since v5:
> > > > > - Use devm_clk_get_optional rather than devm_clk_get
> > > > >
> > > > > drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
> > > > > 1 file changed, 16 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > index fe4f9556239ac..c6c00e8779ab5 100644
> > > > > --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > @@ -76,6 +76,7 @@ struct rockchip_hdmi {
> > > > > const struct rockchip_hdmi_chip_data *chip_data;
> > > > > struct clk *ref_clk;
> > > > > struct clk *grf_clk;
> > > > > + struct clk *hclk_clk;
> > > > > struct dw_hdmi *hdmi;
> > > > > struct regulator *avdd_0v9;
> > > > > struct regulator *avdd_1v8;
> > > > > @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
> > > > > return PTR_ERR(hdmi->grf_clk);
> > > > > }
> > > > > + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
> > > > > + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
> > > >
> > > > Have you tried to investigate the hclk? I'm still thinking that's not
> > > > only HDMI that needs this clock and then the hardware description
> > > > doesn't look correct.
> > >
> > > I am still not sure what you mean. Yes, it's not only the HDMI that
> > > needs this clock. The VOP2 needs it as well and the driver handles that.
> >
> > I'm curious whether DSI/DP also need that clock to be enabled. If they
> > do, then you aren't modeling h/w properly AFAICS.
>
> Assuming nobody at Rockchip decided to make things needlessly inconsistent
> with previous SoCs, HCLK_VOP should be the clock for the VOP's AHB slave
> interface. Usually, if that affected anything other than accessing VOP
> registers, indeed it would smell of something being wrong in the clock tree,
> but in this case I'd also be suspicious of whether it might have ended up
> clocking related GRF registers as well (either directly, or indirectly via
> some gate that the clock driver hasn't modelled yet).
Ok, I am beginning to understand. I verified that hdmi, mipi and dp are
hanging when HCLK_VOP is disabled by disabling that clock via sysfs
using CLOCK_ALLOW_WRITE_DEBUGFS. When it's disabled then the registers
of that units can't be accessed. However, when I disable HCLK_VOP by
directly writing to the gate bit RK3568_CLKGATE_CON(20) then only
accessing VOP registers hangs, the other units stay functional.
So it seems it must be the parent clock which must be enabled. The
parent clock is hclk_vo. This clock should be handled as part of the
RK3568_PD_VO power domain:
power-domain@RK3568_PD_VO {
reg = <RK3568_PD_VO>;
clocks = <&cru HCLK_VO>,
<&cru PCLK_VO>,
<&cru ACLK_VOP_PRE>;
pm_qos = <&qos_hdcp>,
<&qos_vop_m0>,
<&qos_vop_m1>;
#power-domain-cells = <0>;
};
The HDMI controller is part of that domain, so I think this should work,
but it doesn't. That's where I am now, I'll have a closer look.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-25 13:11 ` Sascha Hauer
@ 2022-02-25 13:33 ` Robin Murphy
2022-02-28 14:19 ` Sascha Hauer
1 sibling, 0 replies; 56+ messages in thread
From: Robin Murphy @ 2022-02-25 13:33 UTC (permalink / raw)
To: Sascha Hauer
Cc: Dmitry Osipenko, dri-devel, devicetree, Benjamin Gaignard,
Peter Geis, Sandy Huang, linux-rockchip, Michael Riesch, kernel,
Andy Yan, linux-arm-kernel
On 2022-02-25 13:11, Sascha Hauer wrote:
> On Fri, Feb 25, 2022 at 12:41:23PM +0000, Robin Murphy wrote:
>> On 2022-02-25 11:10, Dmitry Osipenko wrote:
>>> 25.02.2022 13:49, Sascha Hauer пишет:
>>>> On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
>>>>> 25.02.2022 10:51, Sascha Hauer пишет:
>>>>>> The rk3568 HDMI has an additional clock that needs to be enabled for the
>>>>>> HDMI controller to work. The purpose of that clock is not clear. It is
>>>>>> named "hclk" in the downstream driver, so use the same name.
>>>>>>
>>>>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>>>>> ---
>>>>>>
>>>>>> Notes:
>>>>>> Changes since v5:
>>>>>> - Use devm_clk_get_optional rather than devm_clk_get
>>>>>>
>>>>>> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
>>>>>> 1 file changed, 16 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>> index fe4f9556239ac..c6c00e8779ab5 100644
>>>>>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>> @@ -76,6 +76,7 @@ struct rockchip_hdmi {
>>>>>> const struct rockchip_hdmi_chip_data *chip_data;
>>>>>> struct clk *ref_clk;
>>>>>> struct clk *grf_clk;
>>>>>> + struct clk *hclk_clk;
>>>>>> struct dw_hdmi *hdmi;
>>>>>> struct regulator *avdd_0v9;
>>>>>> struct regulator *avdd_1v8;
>>>>>> @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
>>>>>> return PTR_ERR(hdmi->grf_clk);
>>>>>> }
>>>>>> + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
>>>>>> + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
>>>>>
>>>>> Have you tried to investigate the hclk? I'm still thinking that's not
>>>>> only HDMI that needs this clock and then the hardware description
>>>>> doesn't look correct.
>>>>
>>>> I am still not sure what you mean. Yes, it's not only the HDMI that
>>>> needs this clock. The VOP2 needs it as well and the driver handles that.
>>>
>>> I'm curious whether DSI/DP also need that clock to be enabled. If they
>>> do, then you aren't modeling h/w properly AFAICS.
>>
>> Assuming nobody at Rockchip decided to make things needlessly inconsistent
>> with previous SoCs, HCLK_VOP should be the clock for the VOP's AHB slave
>> interface. Usually, if that affected anything other than accessing VOP
>> registers, indeed it would smell of something being wrong in the clock tree,
>> but in this case I'd also be suspicious of whether it might have ended up
>> clocking related GRF registers as well (either directly, or indirectly via
>> some gate that the clock driver hasn't modelled yet).
>
> Ok, I am beginning to understand. I verified that hdmi, mipi and dp are
> hanging when HCLK_VOP is disabled by disabling that clock via sysfs
> using CLOCK_ALLOW_WRITE_DEBUGFS. When it's disabled then the registers
> of that units can't be accessed. However, when I disable HCLK_VOP by
> directly writing to the gate bit RK3568_CLKGATE_CON(20) then only
> accessing VOP registers hangs, the other units stay functional.
> So it seems it must be the parent clock which must be enabled. The
> parent clock is hclk_vo. This clock should be handled as part of the
> RK3568_PD_VO power domain:
>
> power-domain@RK3568_PD_VO {
> reg = <RK3568_PD_VO>;
> clocks = <&cru HCLK_VO>,
> <&cru PCLK_VO>,
> <&cru ACLK_VOP_PRE>;
> pm_qos = <&qos_hdcp>,
> <&qos_vop_m0>,
> <&qos_vop_m1>;
> #power-domain-cells = <0>;
> };
>
> The HDMI controller is part of that domain, so I think this should work,
> but it doesn't. That's where I am now, I'll have a closer look.
Ah, interesting. Looking at the clock driver, I'd also be suspicious
whether pclk_vo is somehow messed up such that we're currently relying
on hclk_vo to keep the common grandparent enabled. Seems like the DSI
and eDP (and HDCP if anyone ever used it) registers would be similarly
affected if so, and sure enough they both have a similarly suspect extra
"hclk" in the downstream DT too.
Robin.
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-25 13:11 ` Sascha Hauer
2022-02-25 13:33 ` Robin Murphy
@ 2022-02-28 14:19 ` Sascha Hauer
2022-02-28 22:56 ` Dmitry Osipenko
2022-03-01 13:39 ` Robin Murphy
1 sibling, 2 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-28 14:19 UTC (permalink / raw)
To: Robin Murphy
Cc: Dmitry Osipenko, dri-devel, devicetree, Benjamin Gaignard,
Peter Geis, Sandy Huang, linux-rockchip, Michael Riesch, kernel,
Andy Yan, linux-arm-kernel
On Fri, Feb 25, 2022 at 02:11:54PM +0100, Sascha Hauer wrote:
> On Fri, Feb 25, 2022 at 12:41:23PM +0000, Robin Murphy wrote:
> > On 2022-02-25 11:10, Dmitry Osipenko wrote:
> > > 25.02.2022 13:49, Sascha Hauer пишет:
> > > > On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
> > > > > 25.02.2022 10:51, Sascha Hauer пишет:
> > > > > > The rk3568 HDMI has an additional clock that needs to be enabled for the
> > > > > > HDMI controller to work. The purpose of that clock is not clear. It is
> > > > > > named "hclk" in the downstream driver, so use the same name.
> > > > > >
> > > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > > > > ---
> > > > > >
> > > > > > Notes:
> > > > > > Changes since v5:
> > > > > > - Use devm_clk_get_optional rather than devm_clk_get
> > > > > >
> > > > > > drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
> > > > > > 1 file changed, 16 insertions(+)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > > index fe4f9556239ac..c6c00e8779ab5 100644
> > > > > > --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > > +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > > @@ -76,6 +76,7 @@ struct rockchip_hdmi {
> > > > > > const struct rockchip_hdmi_chip_data *chip_data;
> > > > > > struct clk *ref_clk;
> > > > > > struct clk *grf_clk;
> > > > > > + struct clk *hclk_clk;
> > > > > > struct dw_hdmi *hdmi;
> > > > > > struct regulator *avdd_0v9;
> > > > > > struct regulator *avdd_1v8;
> > > > > > @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
> > > > > > return PTR_ERR(hdmi->grf_clk);
> > > > > > }
> > > > > > + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
> > > > > > + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
> > > > >
> > > > > Have you tried to investigate the hclk? I'm still thinking that's not
> > > > > only HDMI that needs this clock and then the hardware description
> > > > > doesn't look correct.
> > > >
> > > > I am still not sure what you mean. Yes, it's not only the HDMI that
> > > > needs this clock. The VOP2 needs it as well and the driver handles that.
> > >
> > > I'm curious whether DSI/DP also need that clock to be enabled. If they
> > > do, then you aren't modeling h/w properly AFAICS.
> >
> > Assuming nobody at Rockchip decided to make things needlessly inconsistent
> > with previous SoCs, HCLK_VOP should be the clock for the VOP's AHB slave
> > interface. Usually, if that affected anything other than accessing VOP
> > registers, indeed it would smell of something being wrong in the clock tree,
> > but in this case I'd also be suspicious of whether it might have ended up
> > clocking related GRF registers as well (either directly, or indirectly via
> > some gate that the clock driver hasn't modelled yet).
>
> Ok, I am beginning to understand. I verified that hdmi, mipi and dp are
> hanging when HCLK_VOP is disabled by disabling that clock via sysfs
> using CLOCK_ALLOW_WRITE_DEBUGFS. When it's disabled then the registers
> of that units can't be accessed. However, when I disable HCLK_VOP by
> directly writing to the gate bit RK3568_CLKGATE_CON(20) then only
> accessing VOP registers hangs, the other units stay functional.
> So it seems it must be the parent clock which must be enabled. The
> parent clock is hclk_vo. This clock should be handled as part of the
> RK3568_PD_VO power domain:
>
> power-domain@RK3568_PD_VO {
> reg = <RK3568_PD_VO>;
> clocks = <&cru HCLK_VO>,
> <&cru PCLK_VO>,
> <&cru ACLK_VOP_PRE>;
> pm_qos = <&qos_hdcp>,
> <&qos_vop_m0>,
> <&qos_vop_m1>;
> #power-domain-cells = <0>;
> };
Forget this. The clocks in this node are only enabled during enabling or
disabling the power domain, they are disabled again immediately afterwards.
OK, I need HCLK_VO to access the HDMI registers. I verified that by
disabling HCLK_VO at register level (CRU_GATE_CON(20) BIT(1)). The
HDMI registers become inaccessible then. This means I'll replace
HCLK_VOP in the HDMI node with HCLK_VO. Does this sound sane?
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-28 14:19 ` Sascha Hauer
@ 2022-02-28 22:56 ` Dmitry Osipenko
2022-03-01 8:37 ` Sascha Hauer
2022-03-01 13:39 ` Robin Murphy
1 sibling, 1 reply; 56+ messages in thread
From: Dmitry Osipenko @ 2022-02-28 22:56 UTC (permalink / raw)
To: Sascha Hauer, Robin Murphy
Cc: devicetree, Benjamin Gaignard, kernel, Sandy Huang, dri-devel,
linux-rockchip, Michael Riesch, Peter Geis, Andy Yan,
Dmitry Osipenko, linux-arm-kernel
On 2/28/22 17:19, Sascha Hauer wrote:
> On Fri, Feb 25, 2022 at 02:11:54PM +0100, Sascha Hauer wrote:
>> On Fri, Feb 25, 2022 at 12:41:23PM +0000, Robin Murphy wrote:
>>> On 2022-02-25 11:10, Dmitry Osipenko wrote:
>>>> 25.02.2022 13:49, Sascha Hauer пишет:
>>>>> On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
>>>>>> 25.02.2022 10:51, Sascha Hauer пишет:
>>>>>>> The rk3568 HDMI has an additional clock that needs to be enabled for the
>>>>>>> HDMI controller to work. The purpose of that clock is not clear. It is
>>>>>>> named "hclk" in the downstream driver, so use the same name.
>>>>>>>
>>>>>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>>>>>> ---
>>>>>>>
>>>>>>> Notes:
>>>>>>> Changes since v5:
>>>>>>> - Use devm_clk_get_optional rather than devm_clk_get
>>>>>>>
>>>>>>> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
>>>>>>> 1 file changed, 16 insertions(+)
>>>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>> index fe4f9556239ac..c6c00e8779ab5 100644
>>>>>>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>> @@ -76,6 +76,7 @@ struct rockchip_hdmi {
>>>>>>> const struct rockchip_hdmi_chip_data *chip_data;
>>>>>>> struct clk *ref_clk;
>>>>>>> struct clk *grf_clk;
>>>>>>> + struct clk *hclk_clk;
>>>>>>> struct dw_hdmi *hdmi;
>>>>>>> struct regulator *avdd_0v9;
>>>>>>> struct regulator *avdd_1v8;
>>>>>>> @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
>>>>>>> return PTR_ERR(hdmi->grf_clk);
>>>>>>> }
>>>>>>> + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
>>>>>>> + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
>>>>>>
>>>>>> Have you tried to investigate the hclk? I'm still thinking that's not
>>>>>> only HDMI that needs this clock and then the hardware description
>>>>>> doesn't look correct.
>>>>>
>>>>> I am still not sure what you mean. Yes, it's not only the HDMI that
>>>>> needs this clock. The VOP2 needs it as well and the driver handles that.
>>>>
>>>> I'm curious whether DSI/DP also need that clock to be enabled. If they
>>>> do, then you aren't modeling h/w properly AFAICS.
>>>
>>> Assuming nobody at Rockchip decided to make things needlessly inconsistent
>>> with previous SoCs, HCLK_VOP should be the clock for the VOP's AHB slave
>>> interface. Usually, if that affected anything other than accessing VOP
>>> registers, indeed it would smell of something being wrong in the clock tree,
>>> but in this case I'd also be suspicious of whether it might have ended up
>>> clocking related GRF registers as well (either directly, or indirectly via
>>> some gate that the clock driver hasn't modelled yet).
>>
>> Ok, I am beginning to understand. I verified that hdmi, mipi and dp are
>> hanging when HCLK_VOP is disabled by disabling that clock via sysfs
>> using CLOCK_ALLOW_WRITE_DEBUGFS. When it's disabled then the registers
>> of that units can't be accessed. However, when I disable HCLK_VOP by
>> directly writing to the gate bit RK3568_CLKGATE_CON(20) then only
>> accessing VOP registers hangs, the other units stay functional.
>> So it seems it must be the parent clock which must be enabled. The
>> parent clock is hclk_vo. This clock should be handled as part of the
>> RK3568_PD_VO power domain:
>>
>> power-domain@RK3568_PD_VO {
>> reg = <RK3568_PD_VO>;
>> clocks = <&cru HCLK_VO>,
>> <&cru PCLK_VO>,
>> <&cru ACLK_VOP_PRE>;
>> pm_qos = <&qos_hdcp>,
>> <&qos_vop_m0>,
>> <&qos_vop_m1>;
>> #power-domain-cells = <0>;
>> };
>
> Forget this. The clocks in this node are only enabled during enabling or
> disabling the power domain, they are disabled again immediately afterwards.
>
> OK, I need HCLK_VO to access the HDMI registers. I verified that by
> disabling HCLK_VO at register level (CRU_GATE_CON(20) BIT(1)). The
> HDMI registers become inaccessible then. This means I'll replace
> HCLK_VOP in the HDMI node with HCLK_VO. Does this sound sane?
The RK3568_PD_VO already has HCLK_VO and the domain should be
auto-enabled before HDMI registers are accessed, hence you should do the
opposite and remove the HCLK_VO/P clock from the HDMI DT, not add it. If
the HCLK_VO clock isn't enabled by the domain driver, then you need to
check why. Or am I missing something?
What about DSI and DP? Don't they depend on RK3568_PD_VO as well?
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-28 22:56 ` Dmitry Osipenko
@ 2022-03-01 8:37 ` Sascha Hauer
2022-03-01 13:22 ` Dmitry Osipenko
0 siblings, 1 reply; 56+ messages in thread
From: Sascha Hauer @ 2022-03-01 8:37 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Robin Murphy, devicetree, Benjamin Gaignard, kernel, Sandy Huang,
dri-devel, linux-rockchip, Michael Riesch, Peter Geis, Andy Yan,
Dmitry Osipenko, linux-arm-kernel
On Tue, Mar 01, 2022 at 01:56:59AM +0300, Dmitry Osipenko wrote:
> On 2/28/22 17:19, Sascha Hauer wrote:
> > On Fri, Feb 25, 2022 at 02:11:54PM +0100, Sascha Hauer wrote:
> >> On Fri, Feb 25, 2022 at 12:41:23PM +0000, Robin Murphy wrote:
> >>> On 2022-02-25 11:10, Dmitry Osipenko wrote:
> >>>> 25.02.2022 13:49, Sascha Hauer пишет:
> >>>>> On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
> >>>>>> 25.02.2022 10:51, Sascha Hauer пишет:
> >>>>>>> The rk3568 HDMI has an additional clock that needs to be enabled for the
> >>>>>>> HDMI controller to work. The purpose of that clock is not clear. It is
> >>>>>>> named "hclk" in the downstream driver, so use the same name.
> >>>>>>>
> >>>>>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> >>>>>>> ---
> >>>>>>>
> >>>>>>> Notes:
> >>>>>>> Changes since v5:
> >>>>>>> - Use devm_clk_get_optional rather than devm_clk_get
> >>>>>>>
> >>>>>>> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
> >>>>>>> 1 file changed, 16 insertions(+)
> >>>>>>>
> >>>>>>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> >>>>>>> index fe4f9556239ac..c6c00e8779ab5 100644
> >>>>>>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> >>>>>>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> >>>>>>> @@ -76,6 +76,7 @@ struct rockchip_hdmi {
> >>>>>>> const struct rockchip_hdmi_chip_data *chip_data;
> >>>>>>> struct clk *ref_clk;
> >>>>>>> struct clk *grf_clk;
> >>>>>>> + struct clk *hclk_clk;
> >>>>>>> struct dw_hdmi *hdmi;
> >>>>>>> struct regulator *avdd_0v9;
> >>>>>>> struct regulator *avdd_1v8;
> >>>>>>> @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
> >>>>>>> return PTR_ERR(hdmi->grf_clk);
> >>>>>>> }
> >>>>>>> + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
> >>>>>>> + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
> >>>>>>
> >>>>>> Have you tried to investigate the hclk? I'm still thinking that's not
> >>>>>> only HDMI that needs this clock and then the hardware description
> >>>>>> doesn't look correct.
> >>>>>
> >>>>> I am still not sure what you mean. Yes, it's not only the HDMI that
> >>>>> needs this clock. The VOP2 needs it as well and the driver handles that.
> >>>>
> >>>> I'm curious whether DSI/DP also need that clock to be enabled. If they
> >>>> do, then you aren't modeling h/w properly AFAICS.
> >>>
> >>> Assuming nobody at Rockchip decided to make things needlessly inconsistent
> >>> with previous SoCs, HCLK_VOP should be the clock for the VOP's AHB slave
> >>> interface. Usually, if that affected anything other than accessing VOP
> >>> registers, indeed it would smell of something being wrong in the clock tree,
> >>> but in this case I'd also be suspicious of whether it might have ended up
> >>> clocking related GRF registers as well (either directly, or indirectly via
> >>> some gate that the clock driver hasn't modelled yet).
> >>
> >> Ok, I am beginning to understand. I verified that hdmi, mipi and dp are
> >> hanging when HCLK_VOP is disabled by disabling that clock via sysfs
> >> using CLOCK_ALLOW_WRITE_DEBUGFS. When it's disabled then the registers
> >> of that units can't be accessed. However, when I disable HCLK_VOP by
> >> directly writing to the gate bit RK3568_CLKGATE_CON(20) then only
> >> accessing VOP registers hangs, the other units stay functional.
> >> So it seems it must be the parent clock which must be enabled. The
> >> parent clock is hclk_vo. This clock should be handled as part of the
> >> RK3568_PD_VO power domain:
> >>
> >> power-domain@RK3568_PD_VO {
> >> reg = <RK3568_PD_VO>;
> >> clocks = <&cru HCLK_VO>,
> >> <&cru PCLK_VO>,
> >> <&cru ACLK_VOP_PRE>;
> >> pm_qos = <&qos_hdcp>,
> >> <&qos_vop_m0>,
> >> <&qos_vop_m1>;
> >> #power-domain-cells = <0>;
> >> };
> >
> > Forget this. The clocks in this node are only enabled during enabling or
> > disabling the power domain, they are disabled again immediately afterwards.
> >
> > OK, I need HCLK_VO to access the HDMI registers. I verified that by
> > disabling HCLK_VO at register level (CRU_GATE_CON(20) BIT(1)). The
> > HDMI registers become inaccessible then. This means I'll replace
> > HCLK_VOP in the HDMI node with HCLK_VO. Does this sound sane?
>
> The RK3568_PD_VO already has HCLK_VO and the domain should be
> auto-enabled before HDMI registers are accessed,
As said, the clocks given in the power domain are only enabled during
the process of enabling/disabling the power domain and are disabled
again directly afterwards:
> if (rockchip_pmu_domain_is_on(pd) != power_on) {
They are enabled here:
> ret = clk_bulk_enable(pd->num_clks, pd->clks);
> if (ret < 0) {
> dev_err(pmu->dev, "failed to enable clocks\n");
> mutex_unlock(&pmu->mutex);
> return ret;
> }
>
> if (!power_on) {
> rockchip_pmu_save_qos(pd);
>
> /* if powering down, idle request to NIU first */
> rockchip_pmu_set_idle_request(pd, true);
> }
>
Then the power domain is switched:
> rockchip_do_pmu_set_power_domain(pd, power_on);
>
> if (power_on) {
> /* if powering up, leave idle mode */
> rockchip_pmu_set_idle_request(pd, false);
>
> rockchip_pmu_restore_qos(pd);
> }
>
And here the clocks are disabled again:
> clk_bulk_disable(pd->num_clks, pd->clks);
> }
> hence you should do the
> opposite and remove the HCLK_VO/P clock from the HDMI DT, not add it. If
> the HCLK_VO clock isn't enabled by the domain driver, then you need to
> check why. Or am I missing something?
What the power domain driver additionally does is: It does a of_clk_get()
on all the clocks found in the node of a power domains consumer. It then
does a pm_clk_add_clk() on the clocks and sets the GENPD_FLAG_PM_CLK
flag. This has the effect that all clocks of a device in a power domain
are enabled as long as the power domain itself is enabled. This means
when I just add HCLK_VO to the DSI node, then the power domain driver
will enable it, even when the clock is not touched in the DSI driver at
all. To me this looks really fishy because I think a device itself
should have control over its clocks. I don't know how many devices
really depend on the power domain driver controlling their clocks, but
everyone of them will stop working when the power domain driver is not
compiled in.
>
> What about DSI and DP? Don't they depend on RK3568_PD_VO as well?
Yes, they depend on that power domain as well.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-03-01 8:37 ` Sascha Hauer
@ 2022-03-01 13:22 ` Dmitry Osipenko
0 siblings, 0 replies; 56+ messages in thread
From: Dmitry Osipenko @ 2022-03-01 13:22 UTC (permalink / raw)
To: Sascha Hauer
Cc: Robin Murphy, devicetree, Benjamin Gaignard, kernel, Sandy Huang,
dri-devel, linux-rockchip, Michael Riesch, Peter Geis, Andy Yan,
Dmitry Osipenko, linux-arm-kernel
On 3/1/22 11:37, Sascha Hauer wrote:
> On Tue, Mar 01, 2022 at 01:56:59AM +0300, Dmitry Osipenko wrote:
>> On 2/28/22 17:19, Sascha Hauer wrote:
>>> On Fri, Feb 25, 2022 at 02:11:54PM +0100, Sascha Hauer wrote:
>>>> On Fri, Feb 25, 2022 at 12:41:23PM +0000, Robin Murphy wrote:
>>>>> On 2022-02-25 11:10, Dmitry Osipenko wrote:
>>>>>> 25.02.2022 13:49, Sascha Hauer пишет:
>>>>>>> On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
>>>>>>>> 25.02.2022 10:51, Sascha Hauer пишет:
>>>>>>>>> The rk3568 HDMI has an additional clock that needs to be enabled for the
>>>>>>>>> HDMI controller to work. The purpose of that clock is not clear. It is
>>>>>>>>> named "hclk" in the downstream driver, so use the same name.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>>>>>>>> ---
>>>>>>>>>
>>>>>>>>> Notes:
>>>>>>>>> Changes since v5:
>>>>>>>>> - Use devm_clk_get_optional rather than devm_clk_get
>>>>>>>>>
>>>>>>>>> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
>>>>>>>>> 1 file changed, 16 insertions(+)
>>>>>>>>>
>>>>>>>>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>>>> index fe4f9556239ac..c6c00e8779ab5 100644
>>>>>>>>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>>>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>>>> @@ -76,6 +76,7 @@ struct rockchip_hdmi {
>>>>>>>>> const struct rockchip_hdmi_chip_data *chip_data;
>>>>>>>>> struct clk *ref_clk;
>>>>>>>>> struct clk *grf_clk;
>>>>>>>>> + struct clk *hclk_clk;
>>>>>>>>> struct dw_hdmi *hdmi;
>>>>>>>>> struct regulator *avdd_0v9;
>>>>>>>>> struct regulator *avdd_1v8;
>>>>>>>>> @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
>>>>>>>>> return PTR_ERR(hdmi->grf_clk);
>>>>>>>>> }
>>>>>>>>> + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
>>>>>>>>> + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
>>>>>>>>
>>>>>>>> Have you tried to investigate the hclk? I'm still thinking that's not
>>>>>>>> only HDMI that needs this clock and then the hardware description
>>>>>>>> doesn't look correct.
>>>>>>>
>>>>>>> I am still not sure what you mean. Yes, it's not only the HDMI that
>>>>>>> needs this clock. The VOP2 needs it as well and the driver handles that.
>>>>>>
>>>>>> I'm curious whether DSI/DP also need that clock to be enabled. If they
>>>>>> do, then you aren't modeling h/w properly AFAICS.
>>>>>
>>>>> Assuming nobody at Rockchip decided to make things needlessly inconsistent
>>>>> with previous SoCs, HCLK_VOP should be the clock for the VOP's AHB slave
>>>>> interface. Usually, if that affected anything other than accessing VOP
>>>>> registers, indeed it would smell of something being wrong in the clock tree,
>>>>> but in this case I'd also be suspicious of whether it might have ended up
>>>>> clocking related GRF registers as well (either directly, or indirectly via
>>>>> some gate that the clock driver hasn't modelled yet).
>>>>
>>>> Ok, I am beginning to understand. I verified that hdmi, mipi and dp are
>>>> hanging when HCLK_VOP is disabled by disabling that clock via sysfs
>>>> using CLOCK_ALLOW_WRITE_DEBUGFS. When it's disabled then the registers
>>>> of that units can't be accessed. However, when I disable HCLK_VOP by
>>>> directly writing to the gate bit RK3568_CLKGATE_CON(20) then only
>>>> accessing VOP registers hangs, the other units stay functional.
>>>> So it seems it must be the parent clock which must be enabled. The
>>>> parent clock is hclk_vo. This clock should be handled as part of the
>>>> RK3568_PD_VO power domain:
>>>>
>>>> power-domain@RK3568_PD_VO {
>>>> reg = <RK3568_PD_VO>;
>>>> clocks = <&cru HCLK_VO>,
>>>> <&cru PCLK_VO>,
>>>> <&cru ACLK_VOP_PRE>;
>>>> pm_qos = <&qos_hdcp>,
>>>> <&qos_vop_m0>,
>>>> <&qos_vop_m1>;
>>>> #power-domain-cells = <0>;
>>>> };
>>>
>>> Forget this. The clocks in this node are only enabled during enabling or
>>> disabling the power domain, they are disabled again immediately afterwards.
>>>
>>> OK, I need HCLK_VO to access the HDMI registers. I verified that by
>>> disabling HCLK_VO at register level (CRU_GATE_CON(20) BIT(1)). The
>>> HDMI registers become inaccessible then. This means I'll replace
>>> HCLK_VOP in the HDMI node with HCLK_VO. Does this sound sane?
>>
>> The RK3568_PD_VO already has HCLK_VO and the domain should be
>> auto-enabled before HDMI registers are accessed,
>
> As said, the clocks given in the power domain are only enabled during
> the process of enabling/disabling the power domain and are disabled
> again directly afterwards:
>
>> if (rockchip_pmu_domain_is_on(pd) != power_on) {
>
> They are enabled here:
>
>> ret = clk_bulk_enable(pd->num_clks, pd->clks);
>> if (ret < 0) {
>> dev_err(pmu->dev, "failed to enable clocks\n");
>> mutex_unlock(&pmu->mutex);
>> return ret;
>> }
>>
>> if (!power_on) {
>> rockchip_pmu_save_qos(pd);
>>
>> /* if powering down, idle request to NIU first */
>> rockchip_pmu_set_idle_request(pd, true);
>> }
>>
>
> Then the power domain is switched:
>
>> rockchip_do_pmu_set_power_domain(pd, power_on);
>>
>> if (power_on) {
>> /* if powering up, leave idle mode */
>> rockchip_pmu_set_idle_request(pd, false);
>>
>> rockchip_pmu_restore_qos(pd);
>> }
>>
>
> And here the clocks are disabled again:
>
>> clk_bulk_disable(pd->num_clks, pd->clks);
>> }
>
>> hence you should do the
>> opposite and remove the HCLK_VO/P clock from the HDMI DT, not add it. If
>> the HCLK_VO clock isn't enabled by the domain driver, then you need to
>> check why. Or am I missing something?
>
> What the power domain driver additionally does is: It does a of_clk_get()
> on all the clocks found in the node of a power domains consumer. It then
> does a pm_clk_add_clk() on the clocks and sets the GENPD_FLAG_PM_CLK
> flag. This has the effect that all clocks of a device in a power domain
> are enabled as long as the power domain itself is enabled. This means
> when I just add HCLK_VO to the DSI node, then the power domain driver
> will enable it, even when the clock is not touched in the DSI driver at
> all. To me this looks really fishy because I think a device itself
> should have control over its clocks. I don't know how many devices
> really depend on the power domain driver controlling their clocks, but
> everyone of them will stop working when the power domain driver is not
> compiled in.
This is a correct behaviour of the GENPD driver. Thank you for the
clarification, I completely forgot that clocks should be kept disabled
by GENPD after power-on.
Now I see why you want to add HCLK_VO to the HDMI node, it's good to me
to add the HCLK_VO to the HDMI node. You may copy this clarification to
the commit message of the HDMI DT patch in v8.
I think it's okay that PD driver uses pm_clk_add_clk(). Shouldn't be a
problem to change that later on if some specific driver will want to
have an explicit control over clocks.
But yes, CONFIG_ROCKCHIP_PM_DOMAINS must be enabled (auto-selected?). Is
ARCH_ROCKCHIP available on ARM64 at all?
>> What about DSI and DP? Don't they depend on RK3568_PD_VO as well?
>
> Yes, they depend on that power domain as well.
So DSI/DP bindings will require a similar HCLK_VO change. You're not
using DP/DSI in this patchset, hence should be okay to postpone the
DSI/DP changes if you don't want to touch them for now.
Seems nothing holds back you now from making the v8.
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^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-02-28 14:19 ` Sascha Hauer
2022-02-28 22:56 ` Dmitry Osipenko
@ 2022-03-01 13:39 ` Robin Murphy
2022-03-02 11:25 ` Sascha Hauer
1 sibling, 1 reply; 56+ messages in thread
From: Robin Murphy @ 2022-03-01 13:39 UTC (permalink / raw)
To: Sascha Hauer
Cc: Dmitry Osipenko, dri-devel, devicetree, Benjamin Gaignard,
Peter Geis, Sandy Huang, linux-rockchip, Michael Riesch, kernel,
Andy Yan, linux-arm-kernel
On 2022-02-28 14:19, Sascha Hauer wrote:
> On Fri, Feb 25, 2022 at 02:11:54PM +0100, Sascha Hauer wrote:
>> On Fri, Feb 25, 2022 at 12:41:23PM +0000, Robin Murphy wrote:
>>> On 2022-02-25 11:10, Dmitry Osipenko wrote:
>>>> 25.02.2022 13:49, Sascha Hauer пишет:
>>>>> On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
>>>>>> 25.02.2022 10:51, Sascha Hauer пишет:
>>>>>>> The rk3568 HDMI has an additional clock that needs to be enabled for the
>>>>>>> HDMI controller to work. The purpose of that clock is not clear. It is
>>>>>>> named "hclk" in the downstream driver, so use the same name.
>>>>>>>
>>>>>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>>>>>> ---
>>>>>>>
>>>>>>> Notes:
>>>>>>> Changes since v5:
>>>>>>> - Use devm_clk_get_optional rather than devm_clk_get
>>>>>>>
>>>>>>> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
>>>>>>> 1 file changed, 16 insertions(+)
>>>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>> index fe4f9556239ac..c6c00e8779ab5 100644
>>>>>>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>> @@ -76,6 +76,7 @@ struct rockchip_hdmi {
>>>>>>> const struct rockchip_hdmi_chip_data *chip_data;
>>>>>>> struct clk *ref_clk;
>>>>>>> struct clk *grf_clk;
>>>>>>> + struct clk *hclk_clk;
>>>>>>> struct dw_hdmi *hdmi;
>>>>>>> struct regulator *avdd_0v9;
>>>>>>> struct regulator *avdd_1v8;
>>>>>>> @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
>>>>>>> return PTR_ERR(hdmi->grf_clk);
>>>>>>> }
>>>>>>> + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
>>>>>>> + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
>>>>>>
>>>>>> Have you tried to investigate the hclk? I'm still thinking that's not
>>>>>> only HDMI that needs this clock and then the hardware description
>>>>>> doesn't look correct.
>>>>>
>>>>> I am still not sure what you mean. Yes, it's not only the HDMI that
>>>>> needs this clock. The VOP2 needs it as well and the driver handles that.
>>>>
>>>> I'm curious whether DSI/DP also need that clock to be enabled. If they
>>>> do, then you aren't modeling h/w properly AFAICS.
>>>
>>> Assuming nobody at Rockchip decided to make things needlessly inconsistent
>>> with previous SoCs, HCLK_VOP should be the clock for the VOP's AHB slave
>>> interface. Usually, if that affected anything other than accessing VOP
>>> registers, indeed it would smell of something being wrong in the clock tree,
>>> but in this case I'd also be suspicious of whether it might have ended up
>>> clocking related GRF registers as well (either directly, or indirectly via
>>> some gate that the clock driver hasn't modelled yet).
>>
>> Ok, I am beginning to understand. I verified that hdmi, mipi and dp are
>> hanging when HCLK_VOP is disabled by disabling that clock via sysfs
>> using CLOCK_ALLOW_WRITE_DEBUGFS. When it's disabled then the registers
>> of that units can't be accessed. However, when I disable HCLK_VOP by
>> directly writing to the gate bit RK3568_CLKGATE_CON(20) then only
>> accessing VOP registers hangs, the other units stay functional.
>> So it seems it must be the parent clock which must be enabled. The
>> parent clock is hclk_vo. This clock should be handled as part of the
>> RK3568_PD_VO power domain:
>>
>> power-domain@RK3568_PD_VO {
>> reg = <RK3568_PD_VO>;
>> clocks = <&cru HCLK_VO>,
>> <&cru PCLK_VO>,
>> <&cru ACLK_VOP_PRE>;
>> pm_qos = <&qos_hdcp>,
>> <&qos_vop_m0>,
>> <&qos_vop_m1>;
>> #power-domain-cells = <0>;
>> };
>
> Forget this. The clocks in this node are only enabled during enabling or
> disabling the power domain, they are disabled again immediately afterwards.
>
> OK, I need HCLK_VO to access the HDMI registers. I verified that by
> disabling HCLK_VO at register level (CRU_GATE_CON(20) BIT(1)). The
> HDMI registers become inaccessible then. This means I'll replace
> HCLK_VOP in the HDMI node with HCLK_VO. Does this sound sane?
Well, it's still a mystery hack overall, and in some ways it seems even
more suspect to be claiming a whole branch of the clock tree rather than
a leaf gate with a specific purpose. I'm really starting to think that
the underlying issue here is a bug in the clock driver, or a hardware
mishap that should logically be worked around by the clock driver,
rather than individual the consumers.
Does it work if you hack the clock driver to think that PCLK_VO is a
child of HCLK_VO? Even if that's not technically true, it would seem to
effectively match the observed behaviour (i.e. all 3 things whose
register access apparently *should* be enabled by a gate off PCLK_VO,
seem to also require HCLK_VO).
Thanks,
Robin.
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-03-01 13:39 ` Robin Murphy
@ 2022-03-02 11:25 ` Sascha Hauer
2022-03-04 14:22 ` Sascha Hauer
0 siblings, 1 reply; 56+ messages in thread
From: Sascha Hauer @ 2022-03-02 11:25 UTC (permalink / raw)
To: Robin Murphy
Cc: Dmitry Osipenko, dri-devel, devicetree, Benjamin Gaignard,
Peter Geis, Sandy Huang, linux-rockchip, Michael Riesch, kernel,
Andy Yan, linux-arm-kernel
On Tue, Mar 01, 2022 at 01:39:31PM +0000, Robin Murphy wrote:
> On 2022-02-28 14:19, Sascha Hauer wrote:
> > On Fri, Feb 25, 2022 at 02:11:54PM +0100, Sascha Hauer wrote:
> > > On Fri, Feb 25, 2022 at 12:41:23PM +0000, Robin Murphy wrote:
> > > > On 2022-02-25 11:10, Dmitry Osipenko wrote:
> > > > > 25.02.2022 13:49, Sascha Hauer пишет:
> > > > > > On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
> > > > > > > 25.02.2022 10:51, Sascha Hauer пишет:
> > > > > > > > The rk3568 HDMI has an additional clock that needs to be enabled for the
> > > > > > > > HDMI controller to work. The purpose of that clock is not clear. It is
> > > > > > > > named "hclk" in the downstream driver, so use the same name.
> > > > > > > >
> > > > > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > > > > > > ---
> > > > > > > >
> > > > > > > > Notes:
> > > > > > > > Changes since v5:
> > > > > > > > - Use devm_clk_get_optional rather than devm_clk_get
> > > > > > > >
> > > > > > > > drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
> > > > > > > > 1 file changed, 16 insertions(+)
> > > > > > > >
> > > > > > > > diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > > > > index fe4f9556239ac..c6c00e8779ab5 100644
> > > > > > > > --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > > > > +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > > > > @@ -76,6 +76,7 @@ struct rockchip_hdmi {
> > > > > > > > const struct rockchip_hdmi_chip_data *chip_data;
> > > > > > > > struct clk *ref_clk;
> > > > > > > > struct clk *grf_clk;
> > > > > > > > + struct clk *hclk_clk;
> > > > > > > > struct dw_hdmi *hdmi;
> > > > > > > > struct regulator *avdd_0v9;
> > > > > > > > struct regulator *avdd_1v8;
> > > > > > > > @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
> > > > > > > > return PTR_ERR(hdmi->grf_clk);
> > > > > > > > }
> > > > > > > > + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
> > > > > > > > + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
> > > > > > >
> > > > > > > Have you tried to investigate the hclk? I'm still thinking that's not
> > > > > > > only HDMI that needs this clock and then the hardware description
> > > > > > > doesn't look correct.
> > > > > >
> > > > > > I am still not sure what you mean. Yes, it's not only the HDMI that
> > > > > > needs this clock. The VOP2 needs it as well and the driver handles that.
> > > > >
> > > > > I'm curious whether DSI/DP also need that clock to be enabled. If they
> > > > > do, then you aren't modeling h/w properly AFAICS.
> > > >
> > > > Assuming nobody at Rockchip decided to make things needlessly inconsistent
> > > > with previous SoCs, HCLK_VOP should be the clock for the VOP's AHB slave
> > > > interface. Usually, if that affected anything other than accessing VOP
> > > > registers, indeed it would smell of something being wrong in the clock tree,
> > > > but in this case I'd also be suspicious of whether it might have ended up
> > > > clocking related GRF registers as well (either directly, or indirectly via
> > > > some gate that the clock driver hasn't modelled yet).
> > >
> > > Ok, I am beginning to understand. I verified that hdmi, mipi and dp are
> > > hanging when HCLK_VOP is disabled by disabling that clock via sysfs
> > > using CLOCK_ALLOW_WRITE_DEBUGFS. When it's disabled then the registers
> > > of that units can't be accessed. However, when I disable HCLK_VOP by
> > > directly writing to the gate bit RK3568_CLKGATE_CON(20) then only
> > > accessing VOP registers hangs, the other units stay functional.
> > > So it seems it must be the parent clock which must be enabled. The
> > > parent clock is hclk_vo. This clock should be handled as part of the
> > > RK3568_PD_VO power domain:
> > >
> > > power-domain@RK3568_PD_VO {
> > > reg = <RK3568_PD_VO>;
> > > clocks = <&cru HCLK_VO>,
> > > <&cru PCLK_VO>,
> > > <&cru ACLK_VOP_PRE>;
> > > pm_qos = <&qos_hdcp>,
> > > <&qos_vop_m0>,
> > > <&qos_vop_m1>;
> > > #power-domain-cells = <0>;
> > > };
> >
> > Forget this. The clocks in this node are only enabled during enabling or
> > disabling the power domain, they are disabled again immediately afterwards.
> >
> > OK, I need HCLK_VO to access the HDMI registers. I verified that by
> > disabling HCLK_VO at register level (CRU_GATE_CON(20) BIT(1)). The
> > HDMI registers become inaccessible then. This means I'll replace
> > HCLK_VOP in the HDMI node with HCLK_VO. Does this sound sane?
>
> Well, it's still a mystery hack overall, and in some ways it seems even more
> suspect to be claiming a whole branch of the clock tree rather than a leaf
> gate with a specific purpose. I'm really starting to think that the
> underlying issue here is a bug in the clock driver, or a hardware mishap
> that should logically be worked around by the clock driver, rather than
> individual the consumers.
>
> Does it work if you hack the clock driver to think that PCLK_VO is a child
> of HCLK_VO? Even if that's not technically true, it would seem to
> effectively match the observed behaviour (i.e. all 3 things whose register
> access apparently *should* be enabled by a gate off PCLK_VO, seem to also
> require HCLK_VO).
Yes, that works as expected. I am not sure though if we really want to
go that path. The pclk rates will become completely bogus with this and
should we have to play with the rates in the future we might regret this
step.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-03-02 11:25 ` Sascha Hauer
@ 2022-03-04 14:22 ` Sascha Hauer
2022-03-04 23:55 ` Dmitry Osipenko
0 siblings, 1 reply; 56+ messages in thread
From: Sascha Hauer @ 2022-03-04 14:22 UTC (permalink / raw)
To: Robin Murphy
Cc: Dmitry Osipenko, dri-devel, devicetree, Benjamin Gaignard,
Peter Geis, Sandy Huang, linux-rockchip, Michael Riesch, kernel,
Andy Yan, linux-arm-kernel
On Wed, Mar 02, 2022 at 12:25:28PM +0100, Sascha Hauer wrote:
> On Tue, Mar 01, 2022 at 01:39:31PM +0000, Robin Murphy wrote:
> > On 2022-02-28 14:19, Sascha Hauer wrote:
> > > On Fri, Feb 25, 2022 at 02:11:54PM +0100, Sascha Hauer wrote:
> > > > On Fri, Feb 25, 2022 at 12:41:23PM +0000, Robin Murphy wrote:
> > > > > On 2022-02-25 11:10, Dmitry Osipenko wrote:
> > > > > > 25.02.2022 13:49, Sascha Hauer пишет:
> > > > > > > On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
> > > > > > > > 25.02.2022 10:51, Sascha Hauer пишет:
> > > > > > > > > The rk3568 HDMI has an additional clock that needs to be enabled for the
> > > > > > > > > HDMI controller to work. The purpose of that clock is not clear. It is
> > > > > > > > > named "hclk" in the downstream driver, so use the same name.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > > > > > > > ---
> > > > > > > > >
> > > > > > > > > Notes:
> > > > > > > > > Changes since v5:
> > > > > > > > > - Use devm_clk_get_optional rather than devm_clk_get
> > > > > > > > >
> > > > > > > > > drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
> > > > > > > > > 1 file changed, 16 insertions(+)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > > > > > index fe4f9556239ac..c6c00e8779ab5 100644
> > > > > > > > > --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > > > > > +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> > > > > > > > > @@ -76,6 +76,7 @@ struct rockchip_hdmi {
> > > > > > > > > const struct rockchip_hdmi_chip_data *chip_data;
> > > > > > > > > struct clk *ref_clk;
> > > > > > > > > struct clk *grf_clk;
> > > > > > > > > + struct clk *hclk_clk;
> > > > > > > > > struct dw_hdmi *hdmi;
> > > > > > > > > struct regulator *avdd_0v9;
> > > > > > > > > struct regulator *avdd_1v8;
> > > > > > > > > @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
> > > > > > > > > return PTR_ERR(hdmi->grf_clk);
> > > > > > > > > }
> > > > > > > > > + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
> > > > > > > > > + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
> > > > > > > >
> > > > > > > > Have you tried to investigate the hclk? I'm still thinking that's not
> > > > > > > > only HDMI that needs this clock and then the hardware description
> > > > > > > > doesn't look correct.
> > > > > > >
> > > > > > > I am still not sure what you mean. Yes, it's not only the HDMI that
> > > > > > > needs this clock. The VOP2 needs it as well and the driver handles that.
> > > > > >
> > > > > > I'm curious whether DSI/DP also need that clock to be enabled. If they
> > > > > > do, then you aren't modeling h/w properly AFAICS.
> > > > >
> > > > > Assuming nobody at Rockchip decided to make things needlessly inconsistent
> > > > > with previous SoCs, HCLK_VOP should be the clock for the VOP's AHB slave
> > > > > interface. Usually, if that affected anything other than accessing VOP
> > > > > registers, indeed it would smell of something being wrong in the clock tree,
> > > > > but in this case I'd also be suspicious of whether it might have ended up
> > > > > clocking related GRF registers as well (either directly, or indirectly via
> > > > > some gate that the clock driver hasn't modelled yet).
> > > >
> > > > Ok, I am beginning to understand. I verified that hdmi, mipi and dp are
> > > > hanging when HCLK_VOP is disabled by disabling that clock via sysfs
> > > > using CLOCK_ALLOW_WRITE_DEBUGFS. When it's disabled then the registers
> > > > of that units can't be accessed. However, when I disable HCLK_VOP by
> > > > directly writing to the gate bit RK3568_CLKGATE_CON(20) then only
> > > > accessing VOP registers hangs, the other units stay functional.
> > > > So it seems it must be the parent clock which must be enabled. The
> > > > parent clock is hclk_vo. This clock should be handled as part of the
> > > > RK3568_PD_VO power domain:
> > > >
> > > > power-domain@RK3568_PD_VO {
> > > > reg = <RK3568_PD_VO>;
> > > > clocks = <&cru HCLK_VO>,
> > > > <&cru PCLK_VO>,
> > > > <&cru ACLK_VOP_PRE>;
> > > > pm_qos = <&qos_hdcp>,
> > > > <&qos_vop_m0>,
> > > > <&qos_vop_m1>;
> > > > #power-domain-cells = <0>;
> > > > };
> > >
> > > Forget this. The clocks in this node are only enabled during enabling or
> > > disabling the power domain, they are disabled again immediately afterwards.
> > >
> > > OK, I need HCLK_VO to access the HDMI registers. I verified that by
> > > disabling HCLK_VO at register level (CRU_GATE_CON(20) BIT(1)). The
> > > HDMI registers become inaccessible then. This means I'll replace
> > > HCLK_VOP in the HDMI node with HCLK_VO. Does this sound sane?
> >
> > Well, it's still a mystery hack overall, and in some ways it seems even more
> > suspect to be claiming a whole branch of the clock tree rather than a leaf
> > gate with a specific purpose. I'm really starting to think that the
> > underlying issue here is a bug in the clock driver, or a hardware mishap
> > that should logically be worked around by the clock driver, rather than
> > individual the consumers.
> >
> > Does it work if you hack the clock driver to think that PCLK_VO is a child
> > of HCLK_VO? Even if that's not technically true, it would seem to
> > effectively match the observed behaviour (i.e. all 3 things whose register
> > access apparently *should* be enabled by a gate off PCLK_VO, seem to also
> > require HCLK_VO).
>
> Yes, that works as expected. I am not sure though if we really want to
> go that path. The pclk rates will become completely bogus with this and
> should we have to play with the rates in the future we might regret this
> step.
How do we proceed here? I can include a patch which makes PCLK_VO a
child of HCLK_VO if that's what we agree upon.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-03-04 14:22 ` Sascha Hauer
@ 2022-03-04 23:55 ` Dmitry Osipenko
2022-03-08 3:31 ` Andy Yan
0 siblings, 1 reply; 56+ messages in thread
From: Dmitry Osipenko @ 2022-03-04 23:55 UTC (permalink / raw)
To: Sascha Hauer, Robin Murphy, Andy Yan
Cc: devicetree, Benjamin Gaignard, kernel, Sandy Huang, dri-devel,
linux-rockchip, Michael Riesch, Peter Geis, Dmitry Osipenko,
linux-arm-kernel
On 3/4/22 17:22, Sascha Hauer wrote:
> On Wed, Mar 02, 2022 at 12:25:28PM +0100, Sascha Hauer wrote:
>> On Tue, Mar 01, 2022 at 01:39:31PM +0000, Robin Murphy wrote:
>>> On 2022-02-28 14:19, Sascha Hauer wrote:
>>>> On Fri, Feb 25, 2022 at 02:11:54PM +0100, Sascha Hauer wrote:
>>>>> On Fri, Feb 25, 2022 at 12:41:23PM +0000, Robin Murphy wrote:
>>>>>> On 2022-02-25 11:10, Dmitry Osipenko wrote:
>>>>>>> 25.02.2022 13:49, Sascha Hauer пишет:
>>>>>>>> On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
>>>>>>>>> 25.02.2022 10:51, Sascha Hauer пишет:
>>>>>>>>>> The rk3568 HDMI has an additional clock that needs to be enabled for the
>>>>>>>>>> HDMI controller to work. The purpose of that clock is not clear. It is
>>>>>>>>>> named "hclk" in the downstream driver, so use the same name.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>>>>>>>>> ---
>>>>>>>>>>
>>>>>>>>>> Notes:
>>>>>>>>>> Changes since v5:
>>>>>>>>>> - Use devm_clk_get_optional rather than devm_clk_get
>>>>>>>>>>
>>>>>>>>>> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
>>>>>>>>>> 1 file changed, 16 insertions(+)
>>>>>>>>>>
>>>>>>>>>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>>>>> index fe4f9556239ac..c6c00e8779ab5 100644
>>>>>>>>>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>>>>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>>>>> @@ -76,6 +76,7 @@ struct rockchip_hdmi {
>>>>>>>>>> const struct rockchip_hdmi_chip_data *chip_data;
>>>>>>>>>> struct clk *ref_clk;
>>>>>>>>>> struct clk *grf_clk;
>>>>>>>>>> + struct clk *hclk_clk;
>>>>>>>>>> struct dw_hdmi *hdmi;
>>>>>>>>>> struct regulator *avdd_0v9;
>>>>>>>>>> struct regulator *avdd_1v8;
>>>>>>>>>> @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
>>>>>>>>>> return PTR_ERR(hdmi->grf_clk);
>>>>>>>>>> }
>>>>>>>>>> + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
>>>>>>>>>> + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
>>>>>>>>>
>>>>>>>>> Have you tried to investigate the hclk? I'm still thinking that's not
>>>>>>>>> only HDMI that needs this clock and then the hardware description
>>>>>>>>> doesn't look correct.
>>>>>>>>
>>>>>>>> I am still not sure what you mean. Yes, it's not only the HDMI that
>>>>>>>> needs this clock. The VOP2 needs it as well and the driver handles that.
>>>>>>>
>>>>>>> I'm curious whether DSI/DP also need that clock to be enabled. If they
>>>>>>> do, then you aren't modeling h/w properly AFAICS.
>>>>>>
>>>>>> Assuming nobody at Rockchip decided to make things needlessly inconsistent
>>>>>> with previous SoCs, HCLK_VOP should be the clock for the VOP's AHB slave
>>>>>> interface. Usually, if that affected anything other than accessing VOP
>>>>>> registers, indeed it would smell of something being wrong in the clock tree,
>>>>>> but in this case I'd also be suspicious of whether it might have ended up
>>>>>> clocking related GRF registers as well (either directly, or indirectly via
>>>>>> some gate that the clock driver hasn't modelled yet).
>>>>>
>>>>> Ok, I am beginning to understand. I verified that hdmi, mipi and dp are
>>>>> hanging when HCLK_VOP is disabled by disabling that clock via sysfs
>>>>> using CLOCK_ALLOW_WRITE_DEBUGFS. When it's disabled then the registers
>>>>> of that units can't be accessed. However, when I disable HCLK_VOP by
>>>>> directly writing to the gate bit RK3568_CLKGATE_CON(20) then only
>>>>> accessing VOP registers hangs, the other units stay functional.
>>>>> So it seems it must be the parent clock which must be enabled. The
>>>>> parent clock is hclk_vo. This clock should be handled as part of the
>>>>> RK3568_PD_VO power domain:
>>>>>
>>>>> power-domain@RK3568_PD_VO {
>>>>> reg = <RK3568_PD_VO>;
>>>>> clocks = <&cru HCLK_VO>,
>>>>> <&cru PCLK_VO>,
>>>>> <&cru ACLK_VOP_PRE>;
>>>>> pm_qos = <&qos_hdcp>,
>>>>> <&qos_vop_m0>,
>>>>> <&qos_vop_m1>;
>>>>> #power-domain-cells = <0>;
>>>>> };
>>>>
>>>> Forget this. The clocks in this node are only enabled during enabling or
>>>> disabling the power domain, they are disabled again immediately afterwards.
>>>>
>>>> OK, I need HCLK_VO to access the HDMI registers. I verified that by
>>>> disabling HCLK_VO at register level (CRU_GATE_CON(20) BIT(1)). The
>>>> HDMI registers become inaccessible then. This means I'll replace
>>>> HCLK_VOP in the HDMI node with HCLK_VO. Does this sound sane?
>>>
>>> Well, it's still a mystery hack overall, and in some ways it seems even more
>>> suspect to be claiming a whole branch of the clock tree rather than a leaf
>>> gate with a specific purpose. I'm really starting to think that the
>>> underlying issue here is a bug in the clock driver, or a hardware mishap
>>> that should logically be worked around by the clock driver, rather than
>>> individual the consumers.
>>>
>>> Does it work if you hack the clock driver to think that PCLK_VO is a child
>>> of HCLK_VO? Even if that's not technically true, it would seem to
>>> effectively match the observed behaviour (i.e. all 3 things whose register
>>> access apparently *should* be enabled by a gate off PCLK_VO, seem to also
>>> require HCLK_VO).
>>
>> Yes, that works as expected. I am not sure though if we really want to
>> go that path. The pclk rates will become completely bogus with this and
>> should we have to play with the rates in the future we might regret this
>> step.
>
> How do we proceed here? I can include a patch which makes PCLK_VO a
> child of HCLK_VO if that's what we agree upon.
Couldn't Andy clarify the actual clock tree structure of the h/w for us?
This will be the best option because datasheet doesn't give the clear
answer, or at least I couldn't find it. Technically, PCLK indeed should
be a child of the HCLK in general, so Robin could be right.
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk
2022-03-04 23:55 ` Dmitry Osipenko
@ 2022-03-08 3:31 ` Andy Yan
[not found] ` <20220309094139198367142@rock-chips.com>
0 siblings, 1 reply; 56+ messages in thread
From: Andy Yan @ 2022-03-08 3:31 UTC (permalink / raw)
To: Dmitry Osipenko, Sascha Hauer, Robin Murphy, elaine.zhang
Cc: devicetree, Benjamin Gaignard, kernel, Sandy Huang, dri-devel,
linux-rockchip, Michael Riesch, Peter Geis, Dmitry Osipenko,
linux-arm-kernel, Kever Yang, algea.cao, huangtao
Hi :
On 3/5/22 07:55, Dmitry Osipenko wrote:
> On 3/4/22 17:22, Sascha Hauer wrote:
>> On Wed, Mar 02, 2022 at 12:25:28PM +0100, Sascha Hauer wrote:
>>> On Tue, Mar 01, 2022 at 01:39:31PM +0000, Robin Murphy wrote:
>>>> On 2022-02-28 14:19, Sascha Hauer wrote:
>>>>> On Fri, Feb 25, 2022 at 02:11:54PM +0100, Sascha Hauer wrote:
>>>>>> On Fri, Feb 25, 2022 at 12:41:23PM +0000, Robin Murphy wrote:
>>>>>>> On 2022-02-25 11:10, Dmitry Osipenko wrote:
>>>>>>>> 25.02.2022 13:49, Sascha Hauer пишет:
>>>>>>>>> On Fri, Feb 25, 2022 at 01:26:14PM +0300, Dmitry Osipenko wrote:
>>>>>>>>>> 25.02.2022 10:51, Sascha Hauer пишет:
>>>>>>>>>>> The rk3568 HDMI has an additional clock that needs to be enabled for the
>>>>>>>>>>> HDMI controller to work. The purpose of that clock is not clear. It is
>>>>>>>>>>> named "hclk" in the downstream driver, so use the same name.
>>>>>>>>>>>
>>>>>>>>>>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>>>>>>>>>>> ---
>>>>>>>>>>>
>>>>>>>>>>> Notes:
>>>>>>>>>>> Changes since v5:
>>>>>>>>>>> - Use devm_clk_get_optional rather than devm_clk_get
>>>>>>>>>>>
>>>>>>>>>>> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++
>>>>>>>>>>> 1 file changed, 16 insertions(+)
>>>>>>>>>>>
>>>>>>>>>>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>>>>>> index fe4f9556239ac..c6c00e8779ab5 100644
>>>>>>>>>>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>>>>>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>>>>>>>>>>> @@ -76,6 +76,7 @@ struct rockchip_hdmi {
>>>>>>>>>>> const struct rockchip_hdmi_chip_data *chip_data;
>>>>>>>>>>> struct clk *ref_clk;
>>>>>>>>>>> struct clk *grf_clk;
>>>>>>>>>>> + struct clk *hclk_clk;
>>>>>>>>>>> struct dw_hdmi *hdmi;
>>>>>>>>>>> struct regulator *avdd_0v9;
>>>>>>>>>>> struct regulator *avdd_1v8;
>>>>>>>>>>> @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
>>>>>>>>>>> return PTR_ERR(hdmi->grf_clk);
>>>>>>>>>>> }
>>>>>>>>>>> + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk");
>>>>>>>>>>> + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
>>>>>>>>>> Have you tried to investigate the hclk? I'm still thinking that's not
>>>>>>>>>> only HDMI that needs this clock and then the hardware description
>>>>>>>>>> doesn't look correct.
>>>>>>>>> I am still not sure what you mean. Yes, it's not only the HDMI that
>>>>>>>>> needs this clock. The VOP2 needs it as well and the driver handles that.
>>>>>>>> I'm curious whether DSI/DP also need that clock to be enabled. If they
>>>>>>>> do, then you aren't modeling h/w properly AFAICS.
>>>>>>> Assuming nobody at Rockchip decided to make things needlessly inconsistent
>>>>>>> with previous SoCs, HCLK_VOP should be the clock for the VOP's AHB slave
>>>>>>> interface. Usually, if that affected anything other than accessing VOP
>>>>>>> registers, indeed it would smell of something being wrong in the clock tree,
>>>>>>> but in this case I'd also be suspicious of whether it might have ended up
>>>>>>> clocking related GRF registers as well (either directly, or indirectly via
>>>>>>> some gate that the clock driver hasn't modelled yet).
>>>>>> Ok, I am beginning to understand. I verified that hdmi, mipi and dp are
>>>>>> hanging when HCLK_VOP is disabled by disabling that clock via sysfs
>>>>>> using CLOCK_ALLOW_WRITE_DEBUGFS. When it's disabled then the registers
>>>>>> of that units can't be accessed. However, when I disable HCLK_VOP by
>>>>>> directly writing to the gate bit RK3568_CLKGATE_CON(20) then only
>>>>>> accessing VOP registers hangs, the other units stay functional.
>>>>>> So it seems it must be the parent clock which must be enabled. The
>>>>>> parent clock is hclk_vo. This clock should be handled as part of the
>>>>>> RK3568_PD_VO power domain:
>>>>>>
>>>>>> power-domain@RK3568_PD_VO {
>>>>>> reg = <RK3568_PD_VO>;
>>>>>> clocks = <&cru HCLK_VO>,
>>>>>> <&cru PCLK_VO>,
>>>>>> <&cru ACLK_VOP_PRE>;
>>>>>> pm_qos = <&qos_hdcp>,
>>>>>> <&qos_vop_m0>,
>>>>>> <&qos_vop_m1>;
>>>>>> #power-domain-cells = <0>;
>>>>>> };
>>>>> Forget this. The clocks in this node are only enabled during enabling or
>>>>> disabling the power domain, they are disabled again immediately afterwards.
>>>>>
>>>>> OK, I need HCLK_VO to access the HDMI registers. I verified that by
>>>>> disabling HCLK_VO at register level (CRU_GATE_CON(20) BIT(1)). The
>>>>> HDMI registers become inaccessible then. This means I'll replace
>>>>> HCLK_VOP in the HDMI node with HCLK_VO. Does this sound sane?
>>>> Well, it's still a mystery hack overall, and in some ways it seems even more
>>>> suspect to be claiming a whole branch of the clock tree rather than a leaf
>>>> gate with a specific purpose. I'm really starting to think that the
>>>> underlying issue here is a bug in the clock driver, or a hardware mishap
>>>> that should logically be worked around by the clock driver, rather than
>>>> individual the consumers.
>>>>
>>>> Does it work if you hack the clock driver to think that PCLK_VO is a child
>>>> of HCLK_VO? Even if that's not technically true, it would seem to
>>>> effectively match the observed behaviour (i.e. all 3 things whose register
>>>> access apparently *should* be enabled by a gate off PCLK_VO, seem to also
>>>> require HCLK_VO).
>>> Yes, that works as expected. I am not sure though if we really want to
>>> go that path. The pclk rates will become completely bogus with this and
>>> should we have to play with the rates in the future we might regret this
>>> step.
>> How do we proceed here? I can include a patch which makes PCLK_VO a
>> child of HCLK_VO if that's what we agree upon.
> Couldn't Andy clarify the actual clock tree structure of the h/w for us?
>
> This will be the best option because datasheet doesn't give the clear
> answer, or at least I couldn't find it. Technically, PCLK indeed should
> be a child of the HCLK in general, so Robin could be right.
Add our clk expert Elaine, she will share some information about the
actual clock structure.
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
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^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v7 11/24] dt-bindings: display: rockchip: dw-hdmi: Add additional clock
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (9 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-03-09 12:06 ` Robin Murphy
2022-02-25 7:51 ` [PATCH v7 12/24] drm/rockchip: dw_hdmi: Use auto-generated tables Sascha Hauer
` (12 subsequent siblings)
23 siblings, 1 reply; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer, Rob Herring
The rk3568 HDMI has an additional clock that needs to be enabled for the
HDMI controller to work. The purpose of that clock is not clear. It is
named "hclk" in the downstream driver, so use the same name.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes since v4:
- Add Robs Ack
.../bindings/display/rockchip/rockchip,dw-hdmi.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index 38ebb69830287..67a76f51637a7 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -44,12 +44,13 @@ properties:
items:
- {}
- {}
- # The next three clocks are all optional, but shall be specified in this
+ # The next four clocks are all optional, but shall be specified in this
# order when present.
- description: The HDMI CEC controller main clock
- description: Power for GRF IO
- description: External clock for some HDMI PHY (old clock name, deprecated)
- description: External clock for some HDMI PHY (new name)
+ - description: hclk
clock-names:
minItems: 2
@@ -61,13 +62,17 @@ properties:
- grf
- vpll
- ref
+ - hclk
- enum:
- grf
- vpll
- ref
+ - hclk
- enum:
- vpll
- ref
+ - hclk
+ - const: hclk
ddc-i2c-bus:
$ref: /schemas/types.yaml#/definitions/phandle
--
2.30.2
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^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v7 11/24] dt-bindings: display: rockchip: dw-hdmi: Add additional clock
2022-02-25 7:51 ` [PATCH v7 11/24] dt-bindings: display: rockchip: dw-hdmi: Add additional clock Sascha Hauer
@ 2022-03-09 12:06 ` Robin Murphy
0 siblings, 0 replies; 56+ messages in thread
From: Robin Murphy @ 2022-03-09 12:06 UTC (permalink / raw)
To: Sascha Hauer, dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Rob Herring
On 2022-02-25 07:51, Sascha Hauer wrote:
> The rk3568 HDMI has an additional clock that needs to be enabled for the
> HDMI controller to work. The purpose of that clock is not clear. It is
> named "hclk" in the downstream driver, so use the same name.
Further to the clarification of the underlying purpose on the other
thread, I suggest we call the new clock "niu" and describe it as
something like "Additional clock required to ungate the bus interface on
certain SoCs".
Cheers,
Robin.
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>
> Notes:
> Changes since v4:
> - Add Robs Ack
>
> .../bindings/display/rockchip/rockchip,dw-hdmi.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> index 38ebb69830287..67a76f51637a7 100644
> --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> @@ -44,12 +44,13 @@ properties:
> items:
> - {}
> - {}
> - # The next three clocks are all optional, but shall be specified in this
> + # The next four clocks are all optional, but shall be specified in this
> # order when present.
> - description: The HDMI CEC controller main clock
> - description: Power for GRF IO
> - description: External clock for some HDMI PHY (old clock name, deprecated)
> - description: External clock for some HDMI PHY (new name)
> + - description: hclk
>
> clock-names:
> minItems: 2
> @@ -61,13 +62,17 @@ properties:
> - grf
> - vpll
> - ref
> + - hclk
> - enum:
> - grf
> - vpll
> - ref
> + - hclk
> - enum:
> - vpll
> - ref
> + - hclk
> + - const: hclk
>
> ddc-i2c-bus:
> $ref: /schemas/types.yaml#/definitions/phandle
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^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v7 12/24] drm/rockchip: dw_hdmi: Use auto-generated tables
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (10 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 11/24] dt-bindings: display: rockchip: dw-hdmi: Add additional clock Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 13/24] drm/rockchip: dw_hdmi: drop mode_valid hook Sascha Hauer
` (11 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Douglas Anderson, Yakir Yang,
Sascha Hauer
From: Douglas Anderson <dianders@chromium.org>
The previous tables for mpll_cfg and curr_ctrl were created using the
20-pages of example settings provided by the PHY vendor. Those
example settings weren't particularly dense, so there were places
where we were guessing what the settings would be for 10-bit and
12-bit (not that we use those anyway). It was also always a lot of
extra work every time we wanted to add a new clock rate since we had
to cross-reference several tables.
In <https://crrev.com/c/285855> I've gone through the work to figure
out how to generate this table automatically. Let's now use the
automatically generated table and then we'll never need to look at it
again.
We only support 8-bit mode right now and only support a small number
of clock rates and I've verified that the only 8-bit rate that was
affected was 148.5. That mode appears to have been wrong in the old
table.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Notes:
Changes since v5:
- Add missing Signed-off-by me
Changes since v3:
- new patch
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 130 +++++++++++---------
1 file changed, 69 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index c6c00e8779ab5..2f5264a7d558a 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -92,80 +92,88 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
{
- 27000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
+ 30666000, {
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40f3, 0x0000 },
},
- }, {
- 36000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
+ }, {
+ 36800000, {
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40a2, 0x0001 },
},
- }, {
- 40000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
+ }, {
+ 46000000, {
+ { 0x00b3, 0x0000 },
+ { 0x2142, 0x0001 },
+ { 0x40a2, 0x0001 },
},
- }, {
- 54000000, {
- { 0x0072, 0x0001},
- { 0x2142, 0x0001},
- { 0x40a2, 0x0001},
+ }, {
+ 61333000, {
+ { 0x0072, 0x0001 },
+ { 0x2142, 0x0001 },
+ { 0x40a2, 0x0001 },
},
- }, {
- 65000000, {
- { 0x0072, 0x0001},
- { 0x2142, 0x0001},
- { 0x40a2, 0x0001},
+ }, {
+ 73600000, {
+ { 0x0072, 0x0001 },
+ { 0x2142, 0x0001 },
+ { 0x4061, 0x0002 },
},
- }, {
- 66000000, {
- { 0x013e, 0x0003},
- { 0x217e, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 92000000, {
+ { 0x0072, 0x0001 },
+ { 0x2145, 0x0002 },
+ { 0x4061, 0x0002 },
},
- }, {
- 74250000, {
- { 0x0072, 0x0001},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 122666000, {
+ { 0x0051, 0x0002 },
+ { 0x2145, 0x0002 },
+ { 0x4061, 0x0002 },
},
- }, {
- 83500000, {
- { 0x0072, 0x0001},
+ }, {
+ 147200000, {
+ { 0x0051, 0x0002 },
+ { 0x2145, 0x0002 },
+ { 0x4064, 0x0003 },
},
- }, {
- 108000000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 184000000, {
+ { 0x0051, 0x0002 },
+ { 0x214c, 0x0003 },
+ { 0x4064, 0x0003 },
},
- }, {
- 106500000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 226666000, {
+ { 0x0040, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x4064, 0x0003 },
},
- }, {
- 146250000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 272000000, {
+ { 0x0040, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x5a64, 0x0003 },
},
- }, {
- 148500000, {
- { 0x0051, 0x0003},
- { 0x214c, 0x0003},
- { 0x4064, 0x0003}
+ }, {
+ 340000000, {
+ { 0x0040, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
},
- }, {
+ }, {
+ 600000000, {
+ { 0x1a40, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
+ },
+ }, {
~0UL, {
- { 0x00a0, 0x000a },
- { 0x2001, 0x000f },
- { 0x4002, 0x000f },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
},
}
};
--
2.30.2
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^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 13/24] drm/rockchip: dw_hdmi: drop mode_valid hook
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (11 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 12/24] drm/rockchip: dw_hdmi: Use auto-generated tables Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 14/24] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always Sascha Hauer
` (10 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
The driver checks if the pixel clock of the given mode matches an entry
in the mpll config table. The frequencies in the mpll table are meant as
a frequency range up to which the entry works, not as a frequency that
must match the pixel clock. The downstream Kernel also does not have
this check, so drop it to allow for more display resolutions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Notes:
Changes since v3:
- new patch
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 25 ---------------------
1 file changed, 25 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 2f5264a7d558a..d1fe4d9299c96 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -257,26 +257,6 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
return 0;
}
-static enum drm_mode_status
-dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
- const struct drm_display_info *info,
- const struct drm_display_mode *mode)
-{
- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
- int pclk = mode->clock * 1000;
- bool valid = false;
- int i;
-
- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
- if (pclk == mpll_cfg[i].mpixelclock) {
- valid = true;
- break;
- }
- }
-
- return (valid) ? MODE_OK : MODE_BAD;
-}
-
static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
{
}
@@ -442,7 +422,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = {
};
static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -459,7 +438,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = {
};
static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -479,7 +457,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = {
};
static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -497,7 +474,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = {
};
static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -510,7 +486,6 @@ static struct rockchip_hdmi_chip_data rk3568_chip_data = {
};
static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
--
2.30.2
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^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 14/24] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (12 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 13/24] drm/rockchip: dw_hdmi: drop mode_valid hook Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 15/24] drm/rockchip: dw_hdmi: add default 594Mhz clk for 4K@60hz Sascha Hauer
` (9 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Douglas Anderson, Yakir Yang,
Sascha Hauer
From: Douglas Anderson <dianders@chromium.org>
Jitter was improved by lowering the MPLL bandwidth to account for high
frequency noise in the rk3288 PLL. In each case MPLL bandwidth was
lowered only enough to get us a comfortable margin. We believe that
lowering the bandwidth like this is safe given sufficient testing.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Notes:
Changes since v3:
- new patch
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++--------------
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index d1fe4d9299c96..e97ba072a097b 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -181,20 +181,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
/* pixelclk bpp8 bpp10 bpp12 */
{
- 40000000, { 0x0018, 0x0018, 0x0018 },
- }, {
- 65000000, { 0x0028, 0x0028, 0x0028 },
- }, {
- 66000000, { 0x0038, 0x0038, 0x0038 },
- }, {
- 74250000, { 0x0028, 0x0038, 0x0038 },
- }, {
- 83500000, { 0x0028, 0x0038, 0x0038 },
- }, {
- 146250000, { 0x0038, 0x0038, 0x0038 },
- }, {
- 148500000, { 0x0000, 0x0038, 0x0038 },
- }, {
+ 600000000, { 0x0000, 0x0000, 0x0000 },
+ }, {
~0UL, { 0x0000, 0x0000, 0x0000},
}
};
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 15/24] drm/rockchip: dw_hdmi: add default 594Mhz clk for 4K@60hz
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (13 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 14/24] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-03-07 12:06 ` Andy Yan
2022-02-25 7:51 ` [PATCH v7 16/24] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional Sascha Hauer
` (8 subsequent siblings)
23 siblings, 1 reply; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Nickey Yang, Sascha Hauer
From: Nickey Yang <nickey.yang@rock-chips.com>
add 594Mhz configuration parameters in rockchip_phy_config
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Notes:
Changes since v3:
- new patch
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index e97ba072a097b..03cda7229e559 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -192,6 +192,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
{ 74250000, 0x8009, 0x0004, 0x0272},
{ 148500000, 0x802b, 0x0004, 0x028d},
{ 297000000, 0x8039, 0x0005, 0x028d},
+ { 594000000, 0x8039, 0x0000, 0x019d},
{ ~0UL, 0x0000, 0x0000, 0x0000}
};
--
2.30.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v7 15/24] drm/rockchip: dw_hdmi: add default 594Mhz clk for 4K@60hz
2022-02-25 7:51 ` [PATCH v7 15/24] drm/rockchip: dw_hdmi: add default 594Mhz clk for 4K@60hz Sascha Hauer
@ 2022-03-07 12:06 ` Andy Yan
0 siblings, 0 replies; 56+ messages in thread
From: Andy Yan @ 2022-03-07 12:06 UTC (permalink / raw)
To: Sascha Hauer, dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Nickey Yang
Hi:
I have a test with the 24 patches applied on Linux-5.17-rc5 on
rk3568-evb1-v10 board with Sony XR-75z9j HDMI TV,
4K don't work, the tv shows no signal.
1080P can work.
On 2/25/22 15:51, Sascha Hauer wrote:
> From: Nickey Yang <nickey.yang@rock-chips.com>
>
> add 594Mhz configuration parameters in rockchip_phy_config
>
> Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>
> Notes:
> Changes since v3:
> - new patch
>
> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> index e97ba072a097b..03cda7229e559 100644
> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> @@ -192,6 +192,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
> { 74250000, 0x8009, 0x0004, 0x0272},
> { 148500000, 0x802b, 0x0004, 0x028d},
> { 297000000, 0x8039, 0x0005, 0x028d},
> + { 594000000, 0x8039, 0x0000, 0x019d},
> { ~0UL, 0x0000, 0x0000, 0x0000}
> };
>
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^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v7 16/24] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (14 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 15/24] drm/rockchip: dw_hdmi: add default 594Mhz clk for 4K@60hz Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 17/24] arm64: dts: rockchip: rk356x: Add VOP2 nodes Sascha Hauer
` (7 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer, Rob Herring
None of the upstream device tree files has a "unwedge" pinctrl
specified. Make it optional.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes since v4:
- Add Robs Ack
.../devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index 67a76f51637a7..7dd753630b46a 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -94,6 +94,7 @@ properties:
The unwedge pinctrl entry shall drive the DDC SDA line low. This is
intended to work around a hardware errata that can cause the DDC I2C
bus to be wedged.
+ minItems: 1
items:
- const: default
- const: unwedge
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 17/24] arm64: dts: rockchip: rk356x: Add VOP2 nodes
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (15 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 16/24] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 8:04 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 18/24] arm64: dts: rockchip: rk356x: Add HDMI nodes Sascha Hauer
` (6 subsequent siblings)
23 siblings, 1 reply; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer, Rob Herring
The VOP2 is the display output controller on the RK3568. Add the node
for it to the dtsi file along with the required display-subsystem node
and the iommu node.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes since v4:
- Add Robs Ack
Changes since v3:
- Bring back gamma_lut regs
- Drop redundant _vop suffix from clock names
arch/arm64/boot/dts/rockchip/rk3566.dtsi | 4 ++
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 51 ++++++++++++++++++++++++
include/dt-bindings/soc/rockchip,vop2.h | 14 +++++++
4 files changed, 73 insertions(+)
create mode 100644 include/dt-bindings/soc/rockchip,vop2.h
diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
index 3839eef5e4f76..595fa2562cb8e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
@@ -18,3 +18,7 @@ power-domain@RK3568_PD_PIPE {
#power-domain-cells = <0>;
};
};
+
+&vop {
+ compatible = "rockchip,rk3566-vop";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 2fd313a295f8a..1e55efb6fcfde 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -95,3 +95,7 @@ power-domain@RK3568_PD_PIPE {
#power-domain-cells = <0>;
};
};
+
+&vop {
+ compatible = "rockchip,rk3568-vop";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index a68033a239750..19d8e67c4698b 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -129,6 +129,11 @@ opp-1800000000 {
};
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
+
firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
@@ -451,6 +456,52 @@ gmac1_mtl_tx_setup: tx-queues-config {
};
};
+ vop: vop@fe040000 {
+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
+ reg-names = "regs", "gamma_lut";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
+ clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
+ iommus = <&vop_mmu>;
+ power-domains = <&power RK3568_PD_VO>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ vop_out: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vp0: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ vp1: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ vp2: port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
+ vop_mmu: iommu@fe043e00 {
+ compatible = "rockchip,rk3568-iommu";
+ reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
qos_gpu: qos@fe128000 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe128000 0x0 0x20>;
diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h
new file mode 100644
index 0000000000000..6e66a802b96a5
--- /dev/null
+++ b/include/dt-bindings/soc/rockchip,vop2.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+
+#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
+#define __DT_BINDINGS_ROCKCHIP_VOP2_H
+
+#define ROCKCHIP_VOP2_EP_RGB0 1
+#define ROCKCHIP_VOP2_EP_HDMI0 2
+#define ROCKCHIP_VOP2_EP_EDP0 3
+#define ROCKCHIP_VOP2_EP_MIPI0 4
+#define ROCKCHIP_VOP2_EP_LVDS0 5
+#define ROCKCHIP_VOP2_EP_MIPI1 6
+#define ROCKCHIP_VOP2_EP_LVDS1 7
+
+#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */
--
2.30.2
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^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v7 17/24] arm64: dts: rockchip: rk356x: Add VOP2 nodes
2022-02-25 7:51 ` [PATCH v7 17/24] arm64: dts: rockchip: rk356x: Add VOP2 nodes Sascha Hauer
@ 2022-02-25 8:04 ` Sascha Hauer
0 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 8:04 UTC (permalink / raw)
To: dri-devel
Cc: devicetree, Benjamin Gaignard, Heiko Stübner, Peter Geis,
Rob Herring, Sandy Huang, linux-rockchip, Michael Riesch, kernel,
Andy Yan, linux-arm-kernel
On Fri, Feb 25, 2022 at 08:51:43AM +0100, Sascha Hauer wrote:
> The VOP2 is the display output controller on the RK3568. Add the node
> for it to the dtsi file along with the required display-subsystem node
> and the iommu node.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>
> Notes:
> Changes since v4:
> - Add Robs Ack
>
> Changes since v3:
> - Bring back gamma_lut regs
> - Drop redundant _vop suffix from clock names
>
> arch/arm64/boot/dts/rockchip/rk3566.dtsi | 4 ++
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 51 ++++++++++++++++++++++++
> include/dt-bindings/soc/rockchip,vop2.h | 14 +++++++
> 4 files changed, 73 insertions(+)
> create mode 100644 include/dt-bindings/soc/rockchip,vop2.h
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
> index 3839eef5e4f76..595fa2562cb8e 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
> @@ -18,3 +18,7 @@ power-domain@RK3568_PD_PIPE {
> #power-domain-cells = <0>;
> };
> };
> +
> +&vop {
> + compatible = "rockchip,rk3566-vop";
> +};
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 2fd313a295f8a..1e55efb6fcfde 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -95,3 +95,7 @@ power-domain@RK3568_PD_PIPE {
> #power-domain-cells = <0>;
> };
> };
> +
> +&vop {
> + compatible = "rockchip,rk3568-vop";
> +};
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index a68033a239750..19d8e67c4698b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -129,6 +129,11 @@ opp-1800000000 {
> };
> };
>
> + display_subsystem: display-subsystem {
> + compatible = "rockchip,display-subsystem";
> + ports = <&vop_out>;
> + };
> +
> firmware {
> scmi: scmi {
> compatible = "arm,scmi-smc";
> @@ -451,6 +456,52 @@ gmac1_mtl_tx_setup: tx-queues-config {
> };
> };
>
> + vop: vop@fe040000 {
> + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
> + reg-names = "regs", "gamma_lut";
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
> + <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
> + clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
> + iommus = <&vop_mmu>;
> + power-domains = <&power RK3568_PD_VO>;
> + rockchip,grf = <&grf>;
> + status = "disabled";
> +
> + vop_out: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vp0: port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + vp1: port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + vp2: port@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + };
> +
> + vop_mmu: iommu@fe043e00 {
> + compatible = "rockchip,rk3568-iommu";
> + reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
> + clock-names = "aclk", "iface";
> + #iommu-cells = <0>;
> + status = "disabled";
> + };
> +
> qos_gpu: qos@fe128000 {
> compatible = "rockchip,rk3568-qos", "syscon";
> reg = <0x0 0xfe128000 0x0 0x20>;
> diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h
> new file mode 100644
> index 0000000000000..6e66a802b96a5
> --- /dev/null
> +++ b/include/dt-bindings/soc/rockchip,vop2.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +
> +#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
> +#define __DT_BINDINGS_ROCKCHIP_VOP2_H
> +
> +#define ROCKCHIP_VOP2_EP_RGB0 1
> +#define ROCKCHIP_VOP2_EP_HDMI0 2
> +#define ROCKCHIP_VOP2_EP_EDP0 3
> +#define ROCKCHIP_VOP2_EP_MIPI0 4
> +#define ROCKCHIP_VOP2_EP_LVDS0 5
> +#define ROCKCHIP_VOP2_EP_MIPI1 6
> +#define ROCKCHIP_VOP2_EP_LVDS1 7
One thing I missed to log in the changelog: These defines now have a
ROCKCHIP_ prefix rather than a RK3568_ prefix so that they can be reused
by future SoCs. Also I start counting from one now so that a zero
initialized variable becomes an invalid value.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v7 18/24] arm64: dts: rockchip: rk356x: Add HDMI nodes
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (16 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 17/24] arm64: dts: rockchip: rk356x: Add VOP2 nodes Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 19/24] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi Sascha Hauer
` (5 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
Add support for the HDMI port found on RK3568.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Notes:
Changes since v5:
- Drop unnecessary #size-cells/#address-cells from nodes with only single endpoint
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 32 ++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 19d8e67c4698b..229ed7a755f3b 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -502,6 +502,38 @@ vop_mmu: iommu@fe043e00 {
status = "disabled";
};
+ hdmi: hdmi@fe0a0000 {
+ compatible = "rockchip,rk3568-dw-hdmi";
+ reg = <0x0 0xfe0a0000 0x0 0x20000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI_HOST>,
+ <&cru CLK_HDMI_SFR>,
+ <&cru CLK_HDMI_CEC>,
+ <&pmucru CLK_HDMI_REF>,
+ <&cru HCLK_VOP>;
+ clock-names = "iahb", "isfr", "cec", "ref", "hclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
+ power-domains = <&power RK3568_PD_VO>;
+ reg-io-width = <4>;
+ rockchip,grf = <&grf>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
qos_gpu: qos@fe128000 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe128000 0x0 0x20>;
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 19/24] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (17 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 18/24] arm64: dts: rockchip: rk356x: Add HDMI nodes Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 20/24] arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a Sascha Hauer
` (4 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
This enabled the VOP2 display controller along with hdmi and the
required port routes which is enough to get a picture out of the
hdmi port of the board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Notes:
Changes since v5:
- Drop reg property from single endpoint node
Changes since v4:
- Sort nodes alphabetically
Changes since v3:
- Fix HDMI connector type
.../boot/dts/rockchip/rk3568-evb1-v10.dts | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
index 184e2aa2416af..792735d424716 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
/ {
@@ -33,6 +34,17 @@ dc_12v: dc-12v {
regulator-max-microvolt = <12000000>;
};
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
@@ -106,6 +118,24 @@ &gmac1m1_rgmii_clk
status = "okay";
};
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
status = "okay";
@@ -390,3 +420,20 @@ &sdmmc0 {
&uart2 {
status = "okay";
};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 20/24] arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (18 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 19/24] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 21/24] drm/rockchip: Make VOP driver optional Sascha Hauer
` (3 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
From: Michael Riesch <michael.riesch@wolfvision.net>
Enable the RK356x Video Output Processor (VOP) 2 on the Pine64
Quartz64 Model A.
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Notes:
Changes since v5:
- Drop reg property from single endpoint node
Changes since v4:
- Sort nodes alphabetically
Changes since v3:
- Fix HDMI connector type
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 166399b7f13f0..ddb7857bef099 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3566.dtsi"
/ {
@@ -35,6 +36,17 @@ fan: gpio_fan {
#cooling-cells = <2>;
};
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -205,6 +217,24 @@ &gmac1m0_clkinout
status = "okay";
};
+&hdmi {
+ avdd-0v9-supply = <&vdda_0v9>;
+ avdd-1v8-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
status = "okay";
@@ -551,3 +581,20 @@ bluetooth {
&uart2 {
status = "okay";
};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 21/24] drm/rockchip: Make VOP driver optional
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (19 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 20/24] arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 23/24] dt-bindings: display: rockchip: Add binding for VOP2 Sascha Hauer
` (2 subsequent siblings)
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
With upcoming VOP2 support VOP won't be the only choice anymore, so make
the VOP driver optional.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/gpu/drm/rockchip/Kconfig | 8 ++++++++
drivers/gpu/drm/rockchip/Makefile | 3 ++-
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +-
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 9f1ecefc39332..b9b156308460a 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -21,8 +21,16 @@ config DRM_ROCKCHIP
if DRM_ROCKCHIP
+config ROCKCHIP_VOP
+ bool "Rockchip VOP driver"
+ default y
+ help
+ This selects support for the VOP driver. You should enable it
+ on all older SoCs up to RK3399.
+
config ROCKCHIP_ANALOGIX_DP
bool "Rockchip specific extensions for Analogix DP driver"
+ depends on ROCKCHIP_VOP
help
This selects support for Rockchip SoC specific extensions
for the Analogix Core DP driver. If you want to enable DP
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index 1a56f696558ca..dfc5512fdb9f1 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -4,8 +4,9 @@
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
- rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o
+ rockchip_drm_gem.o
+rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o
rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index 7920a4f44f693..cf8dba96a7dee 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -491,7 +491,7 @@ static int __init rockchip_drm_init(void)
int ret;
num_rockchip_sub_drivers = 0;
- ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP);
+ ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP);
ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver,
CONFIG_ROCKCHIP_LVDS);
ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver,
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 23/24] dt-bindings: display: rockchip: Add binding for VOP2
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (20 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 21/24] drm/rockchip: Make VOP driver optional Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
2022-02-25 7:51 ` [PATCH v7 24/24] dt-bindings: display: rockchip: dw-hdmi: fix ports description Sascha Hauer
[not found] ` <20220225075150.2729401-23-s.hauer@pengutronix.de>
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer, Rob Herring
The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
The binding differs slightly from the existing VOP binding, so add a new
binding file for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes since v5:
- Add Robs Reviewed-by:
Changes since v4:
- Fix clk names in example
- Drop unnecessary assigned-clocks, assigned-clock-rates and assigned-clock-parents
Changes since v3:
- drop redundant _vop suffix from clock names
Changes since v3:
- new patch
.../display/rockchip/rockchip-vop2.yaml | 140 ++++++++++++++++++
1 file changed, 140 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
new file mode 100644
index 0000000000000..655d9b327f7d3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC display controller (VOP2)
+
+description:
+ VOP2 (Video Output Processor v2) is the display controller for the Rockchip
+ series of SoCs which transfers the image data from a video memory
+ buffer to an external LCD interface.
+
+maintainers:
+ - Sandy Huang <hjc@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3566-vop
+ - rockchip,rk3568-vop
+
+ reg:
+ minItems: 1
+ items:
+ - description:
+ Must contain one entry corresponding to the base address and length
+ of the register space.
+ - description:
+ Can optionally contain a second entry corresponding to
+ the CRTC gamma LUT address.
+
+ interrupts:
+ maxItems: 1
+ description:
+ The VOP interrupt is shared by several interrupt sources, such as
+ frame start (VSYNC), line flag and other status interrupts.
+
+ clocks:
+ items:
+ - description: Clock for ddr buffer transfer.
+ - description: Clock for the ahb bus to R/W the phy regs.
+ - description: Pixel clock for video port 0.
+ - description: Pixel clock for video port 1.
+ - description: Pixel clock for video port 2.
+
+ clock-names:
+ items:
+ - const: aclk
+ - const: hclk
+ - const: dclk_vp0
+ - const: dclk_vp1
+ - const: dclk_vp2
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to GRF regs used for misc control
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output endpoint of VP0
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output endpoint of VP1
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output endpoint of VP2
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3568-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3568-power.h>
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ vop: vop@fe040000 {
+ compatible = "rockchip,rk3568-vop";
+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>;
+ clock-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2";
+ power-domains = <&power RK3568_PD_VO>;
+ iommus = <&vop_mmu>;
+ vop_out: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vp0: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ vp1: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ vp2: port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+ };
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v7 24/24] dt-bindings: display: rockchip: dw-hdmi: fix ports description
2022-02-25 7:51 [PATCH v7 00/24] drm/rockchip: RK356x VOP2 support Sascha Hauer
` (21 preceding siblings ...)
2022-02-25 7:51 ` [PATCH v7 23/24] dt-bindings: display: rockchip: Add binding for VOP2 Sascha Hauer
@ 2022-02-25 7:51 ` Sascha Hauer
[not found] ` <20220225075150.2729401-23-s.hauer@pengutronix.de>
23 siblings, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-02-25 7:51 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer, Rob Herring
Current port description doesn't cover all possible cases. It currently
expects one single port with two endpoints.
When the HDMI connector is described in the device tree there can be two
ports, first one going to the VOP and the second one going to the connector.
Also on SoCs which only have a single VOP there will be only one
endpoint instead of two.
This patch addresses both issues. With this there can either be a single
port ("port") , or two of them ("port@0", "port@1") when the connector
is also in the device tree. Also the first or only port can either have
one endpoint ("endpoint") for single VOP SoCs or two ("endpoint@0",
"endpoint@1") for dual VOP SoCs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes since v6:
- Add Reviewed-by: Rob Herring <robh@kernel.org>
Changes since v5:
- new patch
.../display/rockchip/rockchip,dw-hdmi.yaml | 24 +++++++------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index 7dd753630b46a..fc26f1d4d001c 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -102,27 +102,21 @@ properties:
ports:
$ref: /schemas/graph.yaml#/properties/ports
- properties:
- port:
- $ref: /schemas/graph.yaml#/$defs/port-base
- unevaluatedProperties: false
+ patternProperties:
+ "^port(@0)?$":
+ $ref: /schemas/graph.yaml#/properties/port
description: Input of the DWC HDMI TX
-
properties:
+ endpoint:
+ description: Connection to the VOP
endpoint@0:
- $ref: /schemas/graph.yaml#/properties/endpoint
description: Connection to the VOPB
-
endpoint@1:
- $ref: /schemas/graph.yaml#/properties/endpoint
description: Connection to the VOPL
-
- required:
- - endpoint@0
- - endpoint@1
-
- required:
- - port
+ properties:
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output of the DWC HDMI TX
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 56+ messages in thread[parent not found: <20220225075150.2729401-23-s.hauer@pengutronix.de>]
* Aw: [PATCH v7 22/24] drm: rockchip: Add VOP2 driver
[not found] ` <20220225075150.2729401-23-s.hauer@pengutronix.de>
@ 2022-03-03 16:07 ` Frank Wunderlich
[not found] ` <bb077f34-333e-a07a-1fcb-702a6807f941@rock-chips.com>
1 sibling, 0 replies; 56+ messages in thread
From: Frank Wunderlich @ 2022-03-03 16:07 UTC (permalink / raw)
To: Sascha Hauer
Cc: dri-devel, linux-arm-kernel, linux-rockchip, devicetree, kernel,
Andy Yan, Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis, Sascha Hauer
Tested this Series on my rk3568 Bananapi R2 Pro v00
Tested-by: Frank Wunderlich <frank-w@public-files.de>
regards Frank
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 56+ messages in thread[parent not found: <bb077f34-333e-a07a-1fcb-702a6807f941@rock-chips.com>]
* Re: [PATCH v7 22/24] drm: rockchip: Add VOP2 driver
[not found] ` <bb077f34-333e-a07a-1fcb-702a6807f941@rock-chips.com>
@ 2022-03-07 12:54 ` Sascha Hauer
2022-03-07 13:09 ` Daniel Stone
1 sibling, 0 replies; 56+ messages in thread
From: Sascha Hauer @ 2022-03-07 12:54 UTC (permalink / raw)
To: Andy Yan
Cc: dri-devel, linux-arm-kernel, linux-rockchip, devicetree, kernel,
Benjamin Gaignard, Michael Riesch, Sandy Huang,
Heiko Stübner, Peter Geis
Hi Andy,
On Mon, Mar 07, 2022 at 08:18:08PM +0800, Andy Yan wrote:
> Hi Sascha:
>
> On 2/25/22 15:51, Sascha Hauer wrote:
> > From: Andy Yan <andy.yan@rock-chips.com>
> >
> > The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
> > It replaces the VOP unit found in the older Rockchip SoCs.
> >
> > This driver has been derived from the downstream Rockchip Kernel and
> > heavily modified:
> >
> > - All nonstandard DRM properties have been removed
> > - dropped struct vop2_plane_state and pass around less data between
> > functions
> > - Dropped all DRM_FORMAT_* not known on upstream
> > - rework register access to get rid of excessively used macros
> > - Drop all waiting for framesyncs
> >
> > The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB
> > board. Overlay support is tested with the modetest utility. AFBC support
> > on the cluster windows is tested with weston-simple-dmabuf-egl on
> > weston using the (yet to be upstreamed) panfrost driver support.
>
>
> When run a weston 10.0.0:
I used weston 9.0.90 during testing. I'll try to reproduce the issue
with weston 10.
Could you maybe have a look at the HCLK issue we are discussing? This
thread could use some input from someone who has contact to the hardware
guys.
Regards,
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 22/24] drm: rockchip: Add VOP2 driver
[not found] ` <bb077f34-333e-a07a-1fcb-702a6807f941@rock-chips.com>
2022-03-07 12:54 ` Sascha Hauer
@ 2022-03-07 13:09 ` Daniel Stone
2022-03-08 8:42 ` Andy Yan
1 sibling, 1 reply; 56+ messages in thread
From: Daniel Stone @ 2022-03-07 13:09 UTC (permalink / raw)
To: Andy Yan
Cc: Sascha Hauer, dri-devel, devicetree, Benjamin Gaignard,
Sandy Huang, linux-rockchip, Michael Riesch, kernel, Peter Geis,
linux-arm-kernel
Hi Andy,
On Mon, 7 Mar 2022 at 12:18, Andy Yan <andy.yan@rock-chips.com> wrote:
> On 2/25/22 15:51, Sascha Hauer wrote:
> > The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
> > It replaces the VOP unit found in the older Rockchip SoCs.
> >
> > This driver has been derived from the downstream Rockchip Kernel and
> > heavily modified:
> >
> > - All nonstandard DRM properties have been removed
> > - dropped struct vop2_plane_state and pass around less data between
> > functions
> > - Dropped all DRM_FORMAT_* not known on upstream
> > - rework register access to get rid of excessively used macros
> > - Drop all waiting for framesyncs
> >
> > The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB
> > board. Overlay support is tested with the modetest utility. AFBC support
> > on the cluster windows is tested with weston-simple-dmabuf-egl on
> > weston using the (yet to be upstreamed) panfrost driver support.
>
> When run a weston 10.0.0:
>
> # export XDG_RUNTIME_DIR=/tmp
> # weston --backend=drm-backend.so --use-pixma --tty=2
> --continue=without-input
>
> I got the following error:
>
> drm_atomic_check_only [PLANE:31:Smart0-win0] CRTC set but no FB
Can you please start Weston with --logger-scopes=log,drm-backend and
attach the output?
Cheers,
Daniel
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 22/24] drm: rockchip: Add VOP2 driver
2022-03-07 13:09 ` Daniel Stone
@ 2022-03-08 8:42 ` Andy Yan
2022-03-08 14:04 ` Daniel Stone
0 siblings, 1 reply; 56+ messages in thread
From: Andy Yan @ 2022-03-08 8:42 UTC (permalink / raw)
To: Daniel Stone
Cc: Sascha Hauer, dri-devel, devicetree, Benjamin Gaignard,
Sandy Huang, linux-rockchip, Michael Riesch, kernel, Peter Geis,
linux-arm-kernel
Hi Daniel:
On 3/7/22 21:09, Daniel Stone wrote:
> Hi Andy,
>
> On Mon, 7 Mar 2022 at 12:18, Andy Yan <andy.yan@rock-chips.com> wrote:
>> On 2/25/22 15:51, Sascha Hauer wrote:
>>> The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
>>> It replaces the VOP unit found in the older Rockchip SoCs.
>>>
>>> This driver has been derived from the downstream Rockchip Kernel and
>>> heavily modified:
>>>
>>> - All nonstandard DRM properties have been removed
>>> - dropped struct vop2_plane_state and pass around less data between
>>> functions
>>> - Dropped all DRM_FORMAT_* not known on upstream
>>> - rework register access to get rid of excessively used macros
>>> - Drop all waiting for framesyncs
>>>
>>> The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB
>>> board. Overlay support is tested with the modetest utility. AFBC support
>>> on the cluster windows is tested with weston-simple-dmabuf-egl on
>>> weston using the (yet to be upstreamed) panfrost driver support.
>> When run a weston 10.0.0:
>>
>> # export XDG_RUNTIME_DIR=/tmp
>> # weston --backend=drm-backend.so --use-pixma --tty=2
>> --continue=without-input
>>
>> I got the following error:
>>
>> drm_atomic_check_only [PLANE:31:Smart0-win0] CRTC set but no FB
> Can you please start Weston with --logger-scopes=log,drm-backend and
> attach the output?
Please see the weston ouput here[0]
This failed is from drm_atom_plane_check: both CRTC and FB must be set
or neither.
static int drm_atomic_plane_check(const struct drm_plane_state
*old_plane_state,
const struct drm_plane_state
*new_plane_state)
{
struct drm_plane *plane = new_plane_state->plane;
struct drm_crtc *crtc = new_plane_state->crtc;
const struct drm_framebuffer *fb = new_plane_state->fb;
unsigned int fb_width, fb_height;
struct drm_mode_rect *clips;
uint32_t num_clips;
int ret;
/* either *both* CRTC and FB must be set, or neither */
if (crtc && !fb) {
drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] CRTC set but
no FB\n",
plane->base.id, plane->name);
return -EINVAL;
} else if (fb && !crtc) {
drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] FB set but no
CRTC\n",
plane->base.id, plane->name);
return -EINVAL;
}
[0]https://pastebin.com/mGXKqD2S
> Cheers,
> Daniel
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v7 22/24] drm: rockchip: Add VOP2 driver
2022-03-08 8:42 ` Andy Yan
@ 2022-03-08 14:04 ` Daniel Stone
2022-03-09 2:03 ` Andy Yan
0 siblings, 1 reply; 56+ messages in thread
From: Daniel Stone @ 2022-03-08 14:04 UTC (permalink / raw)
To: Andy Yan
Cc: Sascha Hauer, dri-devel, devicetree, Benjamin Gaignard,
Sandy Huang, linux-rockchip, Michael Riesch, kernel, Peter Geis,
linux-arm-kernel
On Tue, 8 Mar 2022 at 08:42, Andy Yan <andy.yan@rock-chips.com> wrote:
> On 3/7/22 21:09, Daniel Stone wrote:
> > On Mon, 7 Mar 2022 at 12:18, Andy Yan <andy.yan@rock-chips.com> wrote:
> >> When run a weston 10.0.0:
> >>
> >> # export XDG_RUNTIME_DIR=/tmp
> >> # weston --backend=drm-backend.so --use-pixma --tty=2
> >> --continue=without-input
> >>
> >> I got the following error:
> >>
> >> drm_atomic_check_only [PLANE:31:Smart0-win0] CRTC set but no FB
> > Can you please start Weston with --logger-scopes=log,drm-backend and
> > attach the output?
>
> Please see the weston ouput here[0]
Are you running with musl perhaps? Either way, please make sure your
libdrm build includes commit 79fa377c8bdc84fde99c6a6ac17e554971c617be.
Cheers,
Daniel
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^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 22/24] drm: rockchip: Add VOP2 driver
2022-03-08 14:04 ` Daniel Stone
@ 2022-03-09 2:03 ` Andy Yan
2022-03-09 7:37 ` Andy Yan
0 siblings, 1 reply; 56+ messages in thread
From: Andy Yan @ 2022-03-09 2:03 UTC (permalink / raw)
To: Daniel Stone
Cc: Sascha Hauer, dri-devel, devicetree, Benjamin Gaignard,
Sandy Huang, linux-rockchip, Michael Riesch, kernel, Peter Geis,
linux-arm-kernel
Hi Daniel:
On 3/8/22 22:04, Daniel Stone wrote:
> On Tue, 8 Mar 2022 at 08:42, Andy Yan <andy.yan@rock-chips.com> wrote:
>> On 3/7/22 21:09, Daniel Stone wrote:
>>> On Mon, 7 Mar 2022 at 12:18, Andy Yan <andy.yan@rock-chips.com> wrote:
>>>> When run a weston 10.0.0:
>>>>
>>>> # export XDG_RUNTIME_DIR=/tmp
>>>> # weston --backend=drm-backend.so --use-pixma --tty=2
>>>> --continue=without-input
>>>>
>>>> I got the following error:
>>>>
>>>> drm_atomic_check_only [PLANE:31:Smart0-win0] CRTC set but no FB
>>> Can you please start Weston with --logger-scopes=log,drm-backend and
>>> attach the output?
>> Please see the weston ouput here[0]
> Are you running with musl perhaps?
Do you mean the C library? I chose uClib-ng in buildroot, not use musl.
> Either way, please make sure your
> libdrm build includes commit 79fa377c8bdc84fde99c6a6ac17e554971c617be.
The upstream buildroot use libdrm2.4.109, this commit[0] if from
libdrm2.4.110
I cherry-pick this patch to my local libdrm, but has no effect, still
has "atomic: couldn't commit new state" error.
I have do a search in libdrm and weston, but find no one call
drmModeAtomicMerge, is that right?
[0]https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/167
>
> Cheers,
> Daniel
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^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 22/24] drm: rockchip: Add VOP2 driver
2022-03-09 2:03 ` Andy Yan
@ 2022-03-09 7:37 ` Andy Yan
2022-03-14 11:02 ` Andy Yan
0 siblings, 1 reply; 56+ messages in thread
From: Andy Yan @ 2022-03-09 7:37 UTC (permalink / raw)
To: Daniel Stone
Cc: Sascha Hauer, dri-devel, devicetree, Benjamin Gaignard,
Sandy Huang, linux-rockchip, Michael Riesch, kernel, Peter Geis,
linux-arm-kernel
Hi Daniel:
On 3/9/22 10:03, Andy Yan wrote:
> Hi Daniel:
>
> On 3/8/22 22:04, Daniel Stone wrote:
>> On Tue, 8 Mar 2022 at 08:42, Andy Yan <andy.yan@rock-chips.com> wrote:
>>> On 3/7/22 21:09, Daniel Stone wrote:
>>>> On Mon, 7 Mar 2022 at 12:18, Andy Yan <andy.yan@rock-chips.com> wrote:
>>>>> When run a weston 10.0.0:
>>>>>
>>>>> # export XDG_RUNTIME_DIR=/tmp
>>>>> # weston --backend=drm-backend.so --use-pixma --tty=2
>>>>> --continue=without-input
>>>>>
>>>>> I got the following error:
>>>>>
>>>>> drm_atomic_check_only [PLANE:31:Smart0-win0] CRTC set but no FB
>>>> Can you please start Weston with --logger-scopes=log,drm-backend and
>>>> attach the output?
>>> Please see the weston ouput here[0]
>> Are you running with musl perhaps?
> Do you mean the C library? I chose uClib-ng in buildroot, not use musl.
>> Either way, please make sure your
>> libdrm build includes commit 79fa377c8bdc84fde99c6a6ac17e554971c617be.
>
>
> The upstream buildroot use libdrm2.4.109, this commit[0] if from
> libdrm2.4.110
>
> I cherry-pick this patch to my local libdrm, but has no effect, still
> has "atomic: couldn't commit new state" error.
>
> I have do a search in libdrm and weston, but find no one call
> drmModeAtomicMerge, is that right?
>
> [0]https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/167
>
With your patch applied from libdrm2.4.110, I do a make clean for
buidlroot, than build it again, That's take effect.
I can see only the second value (non-zero FB) of plane 31 commit to the
kernel. So this is works.
Maybe the buidroot should update libdrm package.
Thank you.
>>
>> Cheers,
>> Daniel
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
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^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 22/24] drm: rockchip: Add VOP2 driver
2022-03-09 7:37 ` Andy Yan
@ 2022-03-14 11:02 ` Andy Yan
2022-03-14 13:38 ` Daniel Stone
0 siblings, 1 reply; 56+ messages in thread
From: Andy Yan @ 2022-03-14 11:02 UTC (permalink / raw)
To: Daniel Stone
Cc: Sascha Hauer, dri-devel, devicetree, Benjamin Gaignard,
Sandy Huang, linux-rockchip, Michael Riesch, kernel, Peter Geis,
linux-arm-kernel
Hi Daniel:
Remember you said our downstream vop2 driver is very slow on weston.
Would you please share the case you run ? or how can i test frame rate
on weston?
On 3/9/22 15:37, Andy Yan wrote:
> Hi Daniel:
>
> On 3/9/22 10:03, Andy Yan wrote:
>> Hi Daniel:
>>
>> On 3/8/22 22:04, Daniel Stone wrote:
>>> On Tue, 8 Mar 2022 at 08:42, Andy Yan <andy.yan@rock-chips.com> wrote:
>>>> On 3/7/22 21:09, Daniel Stone wrote:
>>>>> On Mon, 7 Mar 2022 at 12:18, Andy Yan <andy.yan@rock-chips.com>
>>>>> wrote:
>>>>>> When run a weston 10.0.0:
>>>>>>
>>>>>> # export XDG_RUNTIME_DIR=/tmp
>>>>>> # weston --backend=drm-backend.so --use-pixma --tty=2
>>>>>> --continue=without-input
>>>>>>
>>>>>> I got the following error:
>>>>>>
>>>>>> drm_atomic_check_only [PLANE:31:Smart0-win0] CRTC set but no FB
>>>>> Can you please start Weston with --logger-scopes=log,drm-backend and
>>>>> attach the output?
>>>> Please see the weston ouput here[0]
>>> Are you running with musl perhaps?
>> Do you mean the C library? I chose uClib-ng in buildroot, not use musl.
>>> Either way, please make sure your
>>> libdrm build includes commit 79fa377c8bdc84fde99c6a6ac17e554971c617be.
>>
>>
>> The upstream buildroot use libdrm2.4.109, this commit[0] if from
>> libdrm2.4.110
>>
>> I cherry-pick this patch to my local libdrm, but has no effect, still
>> has "atomic: couldn't commit new state" error.
>>
>> I have do a search in libdrm and weston, but find no one call
>> drmModeAtomicMerge, is that right?
>>
>> [0]https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/167
>>
>
> With your patch applied from libdrm2.4.110, I do a make clean for
> buidlroot, than build it again, That's take effect.
>
> I can see only the second value (non-zero FB) of plane 31 commit to
> the kernel. So this is works.
>
> Maybe the buidroot should update libdrm package.
>
> Thank you.
>
>>>
>>> Cheers,
>>> Daniel
>>
>> _______________________________________________
>> Linux-rockchip mailing list
>> Linux-rockchip@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
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^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v7 22/24] drm: rockchip: Add VOP2 driver
2022-03-14 11:02 ` Andy Yan
@ 2022-03-14 13:38 ` Daniel Stone
0 siblings, 0 replies; 56+ messages in thread
From: Daniel Stone @ 2022-03-14 13:38 UTC (permalink / raw)
To: Andy Yan
Cc: Sascha Hauer, dri-devel, devicetree, Benjamin Gaignard,
Sandy Huang, linux-rockchip, Michael Riesch, kernel, Peter Geis,
linux-arm-kernel
Hi Andy,
On Mon, 14 Mar 2022 at 11:02, Andy Yan <andy.yan@rock-chips.com> wrote:
> Remember you said our downstream vop2 driver is very slow on weston.
>
> Would you please share the case you run ? or how can i test frame rate
> on weston?
We were able to observe this by just using either waylandsink (using
dmabuf from the V4L2 rkvdec/rkvpu drivers), or even weston-simple-egl.
I have not been able to do a full review of Sascha's submission, but
from what I've seen of it, it should have fixed those issues. (I don't
have RK3568 hardware to hand anymore.)
Cheers,
Daniel
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^ permalink raw reply [flat|nested] 56+ messages in thread