* [PATCH v2 0/4] Fix MediaTek display dt-bindings issues
@ 2022-03-09 13:46 jason-jh.lin
2022-03-09 13:46 ` [PATCH v2 1/4] Revert "dt-bindings: display: mediatek: add ethdr definition for mt8195" jason-jh.lin
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: jason-jh.lin @ 2022-03-09 13:46 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Enric Balletbo i Serra, Maxime Coquelin,
David Airlie, Daniel Vetter, Alexandre Torgue, jason-jh . lin,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
The vdosys0 series carried a nice dt-bindings conversion of the old
txt documentation for the entire mediatek-drm driver, but some of
the issues in there weren't seen.
This series is fixing all of the issues pointed out by a
`dt_binding_check` run, followed by `dtbs_check`.
Change in v2:
- remove mediatek,ethdr.yaml file
- change include header of mediatek,ovl-2l.yaml from mt8173 to mt8183
AngeloGioacchino Del Regno (3):
dt-bindings: display: mediatek, mutex: Fix mediatek, gce-events type
dt-bindings: display: mediatek, ovl: Fix 'iommu' required property
typo
dt-bindings: display: mediatek: Fix examples on new bindings
jason-jh.lin (1):
Revert "dt-bindings: display: mediatek: add ethdr definition for
mt8195"
.../display/mediatek/mediatek,aal.yaml | 23 ++-
.../display/mediatek/mediatek,ccorr.yaml | 23 ++-
.../display/mediatek/mediatek,color.yaml | 23 ++-
.../display/mediatek/mediatek,dither.yaml | 23 ++-
.../display/mediatek/mediatek,dpi.yaml | 3 +-
.../display/mediatek/mediatek,dsc.yaml | 23 ++-
.../display/mediatek/mediatek,ethdr.yaml | 147 ------------------
.../display/mediatek/mediatek,gamma.yaml | 23 ++-
.../display/mediatek/mediatek,merge.yaml | 49 +++---
.../display/mediatek/mediatek,mutex.yaml | 27 ++--
.../display/mediatek/mediatek,od.yaml | 14 +-
.../display/mediatek/mediatek,ovl-2l.yaml | 26 +++-
.../display/mediatek/mediatek,ovl.yaml | 28 ++--
.../display/mediatek/mediatek,postmask.yaml | 23 ++-
.../display/mediatek/mediatek,rdma.yaml | 28 ++--
.../display/mediatek/mediatek,split.yaml | 17 +-
.../display/mediatek/mediatek,ufoe.yaml | 19 ++-
.../display/mediatek/mediatek,wdma.yaml | 26 +++-
18 files changed, 262 insertions(+), 283 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/4] Revert "dt-bindings: display: mediatek: add ethdr definition for mt8195"
2022-03-09 13:46 [PATCH v2 0/4] Fix MediaTek display dt-bindings issues jason-jh.lin
@ 2022-03-09 13:46 ` jason-jh.lin
2022-03-09 13:47 ` [PATCH v2 2/4] dt-bindings: display: mediatek, mutex: Fix mediatek, gce-events type jason-jh.lin
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: jason-jh.lin @ 2022-03-09 13:46 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Enric Balletbo i Serra, Maxime Coquelin,
David Airlie, Daniel Vetter, Alexandre Torgue, jason-jh . lin,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
This reverts commit e7dcfe64204a5cd9a74a9ca7d9c7a22434dc7fe5.
Because examples property of mediatek,ethdr.yaml should base on [1][2].
Reverting it until [1][2] are applied.
[1] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20220217113453.13658-2-yong.wu@mediatek.com/
[2] dt-bindings: reset: mt8195: add vdosys1 reset control bit
https://patchwork.kernel.org/project/linux-mediatek/patch/20220222100741.30138-5-nancy.lin@mediatek.com/
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../display/mediatek/mediatek,ethdr.yaml | 147 ------------------
1 file changed, 147 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
deleted file mode 100644
index 131eed5eeeb7..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+++ /dev/null
@@ -1,147 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Mediatek Ethdr Device Tree Bindings
-
-maintainers:
- - Chun-Kuang Hu <chunkuang.hu@kernel.org>
- - Philipp Zabel <p.zabel@pengutronix.de>
-
-description: |
- ETHDR is designed for HDR video and graphics conversion in the external display path.
- It handles multiple HDR input types and performs tone mapping, color space/color
- format conversion, and then combine different layers, output the required HDR or
- SDR signal to the subsequent display path. This engine is composed of two video
- frontends, two graphic frontends, one video backend and a mixer. ETHDR has two
- DMA function blocks, DS and ADL. These two function blocks read the pre-programmed
- registers from DRAM and set them to HW in the v-blanking period.
-
-properties:
- compatible:
- items:
- - const: mediatek,mt8195-disp-ethdr
- reg:
- maxItems: 7
- reg-names:
- items:
- - const: mixer
- - const: vdo_fe0
- - const: vdo_fe1
- - const: gfx_fe0
- - const: gfx_fe1
- - const: vdo_be
- - const: adl_ds
- interrupts:
- minItems: 1
- iommus:
- description: The compatible property is DMA function blocks.
- Should point to the respective IOMMU block with master port as argument,
- see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
- details.
- minItems: 1
- maxItems: 2
- clocks:
- items:
- - description: mixer clock
- - description: video frontend 0 clock
- - description: video frontend 1 clock
- - description: graphic frontend 0 clock
- - description: graphic frontend 1 clock
- - description: video backend clock
- - description: autodownload and menuload clock
- - description: video frontend 0 async clock
- - description: video frontend 1 async clock
- - description: graphic frontend 0 async clock
- - description: graphic frontend 1 async clock
- - description: video backend async clock
- - description: ethdr top clock
- clock-names:
- items:
- - const: mixer
- - const: vdo_fe0
- - const: vdo_fe1
- - const: gfx_fe0
- - const: gfx_fe1
- - const: vdo_be
- - const: adl_ds
- - const: vdo_fe0_async
- - const: vdo_fe1_async
- - const: gfx_fe0_async
- - const: gfx_fe1_async
- - const: vdo_be_async
- - const: ethdr_top
- power-domains:
- maxItems: 1
- resets:
- maxItems: 5
- mediatek,gce-client-reg:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- description: The register of display function block to be set by gce.
- There are 4 arguments in this property, gce node, subsys id, offset and
- register size. The subsys id is defined in the gce header of each chips
- include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
- display function block.
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - interrupts
- - power-domains
-
-additionalProperties: false
-
-examples:
- - |
-
- disp_ethdr@1c114000 {
- compatible = "mediatek,mt8195-disp-ethdr";
- reg = <0 0x1c114000 0 0x1000>,
- <0 0x1c115000 0 0x1000>,
- <0 0x1c117000 0 0x1000>,
- <0 0x1c119000 0 0x1000>,
- <0 0x1c11A000 0 0x1000>,
- <0 0x1c11B000 0 0x1000>,
- <0 0x1c11C000 0 0x1000>;
- reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
- "vdo_be", "adl_ds";
- mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0xA000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0xB000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0xC000 0x1000>;
- clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
- <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
- <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
- <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
- <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
- <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
- <&vdosys1 CLK_VDO1_26M_SLOW>,
- <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
- <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
- <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
- <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
- <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
- <&topckgen CLK_TOP_ETHDR_SEL>;
- clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
- "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
- "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
- "ethdr_top";
- power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
- iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
- <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
- interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
- resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
- <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
- <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
- <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
- <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
- };
-
-...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/4] dt-bindings: display: mediatek, mutex: Fix mediatek, gce-events type
2022-03-09 13:46 [PATCH v2 0/4] Fix MediaTek display dt-bindings issues jason-jh.lin
2022-03-09 13:46 ` [PATCH v2 1/4] Revert "dt-bindings: display: mediatek: add ethdr definition for mt8195" jason-jh.lin
@ 2022-03-09 13:47 ` jason-jh.lin
2022-03-09 13:47 ` [PATCH v2 3/4] dt-bindings: display: mediatek, ovl: Fix 'iommu' required property typo jason-jh.lin
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: jason-jh.lin @ 2022-03-09 13:47 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Enric Balletbo i Serra, Maxime Coquelin,
David Airlie, Daniel Vetter, Alexandre Torgue, jason-jh . lin,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
The mediatek,gce-events property needs as value an array of uint32
corresponding to the CMDQ events to listen to, and not any phandle.
Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
.../devicetree/bindings/display/mediatek/mediatek,mutex.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
index 6eca525eced0..842ba7b07a34 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
@@ -58,7 +58,7 @@ properties:
The event id which is mapping to the specific hardware event signal
to gce. The event id is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
- $ref: /schemas/types.yaml#/definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/uint32-array
required:
- compatible
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/4] dt-bindings: display: mediatek, ovl: Fix 'iommu' required property typo
2022-03-09 13:46 [PATCH v2 0/4] Fix MediaTek display dt-bindings issues jason-jh.lin
2022-03-09 13:46 ` [PATCH v2 1/4] Revert "dt-bindings: display: mediatek: add ethdr definition for mt8195" jason-jh.lin
2022-03-09 13:47 ` [PATCH v2 2/4] dt-bindings: display: mediatek, mutex: Fix mediatek, gce-events type jason-jh.lin
@ 2022-03-09 13:47 ` jason-jh.lin
2022-03-09 13:47 ` [PATCH v2 4/4] dt-bindings: display: mediatek: Fix examples on new bindings jason-jh.lin
2022-03-23 14:09 ` [PATCH v2 0/4] Fix MediaTek display dt-bindings issues Rob Herring
4 siblings, 0 replies; 8+ messages in thread
From: jason-jh.lin @ 2022-03-09 13:47 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Enric Balletbo i Serra, Maxime Coquelin,
David Airlie, Daniel Vetter, Alexandre Torgue, jason-jh . lin,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
The property is called 'iommus' and not 'iommu'. Fix this typo.
Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
.../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index 93d5c68a2dbd..fc691d00c60e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -75,7 +75,7 @@ required:
- interrupts
- power-domains
- clocks
- - iommu
+ - iommus
additionalProperties: false
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 4/4] dt-bindings: display: mediatek: Fix examples on new bindings
2022-03-09 13:46 [PATCH v2 0/4] Fix MediaTek display dt-bindings issues jason-jh.lin
` (2 preceding siblings ...)
2022-03-09 13:47 ` [PATCH v2 3/4] dt-bindings: display: mediatek, ovl: Fix 'iommu' required property typo jason-jh.lin
@ 2022-03-09 13:47 ` jason-jh.lin
2022-03-23 14:09 ` [PATCH v2 0/4] Fix MediaTek display dt-bindings issues Rob Herring
4 siblings, 0 replies; 8+ messages in thread
From: jason-jh.lin @ 2022-03-09 13:47 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Philipp Zabel, Enric Balletbo i Serra, Maxime Coquelin,
David Airlie, Daniel Vetter, Alexandre Torgue, jason-jh . lin,
hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
nancy.lin, singo.chang, devicetree, linux-stm32,
linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To avoid failure of dt_binding_check perform a slight refactoring
of the examples: the main block is kept, but that required fixing
the address and size cells, plus the inclusion of missing dt-bindings
headers, required to parse some of the values assigned to various
properties.
Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Tested-by: jason-jh.lin <jason-jh.lin@medaitek.com>
---
.../display/mediatek/mediatek,aal.yaml | 23 ++++++---
.../display/mediatek/mediatek,ccorr.yaml | 23 ++++++---
.../display/mediatek/mediatek,color.yaml | 23 ++++++---
.../display/mediatek/mediatek,dither.yaml | 23 ++++++---
.../display/mediatek/mediatek,dpi.yaml | 3 +-
.../display/mediatek/mediatek,dsc.yaml | 23 ++++++---
.../display/mediatek/mediatek,gamma.yaml | 23 ++++++---
.../display/mediatek/mediatek,merge.yaml | 49 +++++++++----------
.../display/mediatek/mediatek,mutex.yaml | 25 +++++++---
.../display/mediatek/mediatek,od.yaml | 14 ++++--
.../display/mediatek/mediatek,ovl-2l.yaml | 26 +++++++---
.../display/mediatek/mediatek,ovl.yaml | 26 +++++++---
.../display/mediatek/mediatek,postmask.yaml | 23 ++++++---
.../display/mediatek/mediatek,rdma.yaml | 28 +++++++----
.../display/mediatek/mediatek,split.yaml | 17 +++++--
.../display/mediatek/mediatek,ufoe.yaml | 19 ++++---
.../display/mediatek/mediatek,wdma.yaml | 26 +++++++---
17 files changed, 260 insertions(+), 134 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
index 225f9dd726d2..61f0ed1e388f 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -66,12 +66,21 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
- aal@14015000 {
- compatible = "mediatek,mt8173-disp-aal";
- reg = <0 0x14015000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_AAL>;
- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aal@14015000 {
+ compatible = "mediatek,mt8173-disp-aal";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_AAL>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index 6894b6999412..0ed53b6238f0 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -65,12 +65,21 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
- ccorr0: ccorr@1400f000 {
- compatible = "mediatek,mt8183-disp-ccorr";
- reg = <0 0x1400f000 0 0x1000>;
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
- clocks = <&mmsys CLK_MM_DISP_CCORR0>;
- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ccorr0: ccorr@1400f000 {
+ compatible = "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
index bc83155b3b4c..3ad842eb5668 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -75,12 +75,21 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
- color0: color@14013000 {
- compatible = "mediatek,mt8173-disp-color";
- reg = <0 0x14013000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_COLOR0>;
- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ color0: color@14013000 {
+ compatible = "mediatek,mt8173-disp-color";
+ reg = <0 0x14013000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
index 9d89297f5f1d..6657549af165 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -65,12 +65,21 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
- dither0: dither@14012000 {
- compatible = "mediatek,mt8183-disp-dither";
- reg = <0 0x14012000 0 0x1000>;
- interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
- clocks = <&mmsys CLK_MM_DISP_DITHER0>;
- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dither0: dither@14012000 {
+ compatible = "mediatek,mt8183-disp-dither";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index dd2896a40ff0..843f89d6053f 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -70,8 +70,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
+
dpi0: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0x1401d000 0x1000>;
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
index 1ec083eff824..49248864514b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
@@ -60,12 +60,21 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/power/mt8195-power.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
- dsc0: disp_dsc_wrap@1c009000 {
- compatible = "mediatek,mt8195-disp-dsc";
- reg = <0 0x1c009000 0 0x1000>;
- interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
- power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
- clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
- mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dsc0: disp_dsc_wrap@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
index 247baad147b3..78442339314f 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -66,12 +66,21 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
- gamma@14016000 {
- compatible = "mediatek,mt8173-disp-gamma";
- reg = <0 0x14016000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_GAMMA>;
- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gamma@14016000 {
+ compatible = "mediatek,mt8173-disp-gamma";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index d5cd69b7f501..d635c5dcb68b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -38,18 +38,16 @@ properties:
Documentation/devicetree/bindings/power/power-domain.yaml for details.
clocks:
+ minItems: 1
maxItems: 2
- items:
- - description: MERGE Clock
- - description: MERGE Async Clock
- Controlling the synchronous process between MERGE and other display
- function blocks cross clock domain.
clock-names:
- maxItems: 2
- items:
- - const: merge
- - const: merge_async
+ oneOf:
+ - items:
+ - const: merge
+ - items:
+ - const: merge
+ - const: merge_async
mediatek,merge-fifo-en:
description:
@@ -88,23 +86,20 @@ additionalProperties: false
examples:
- |
-
- merge@14017000 {
- compatible = "mediatek,mt8173-disp-merge";
- reg = <0 0x14017000 0 0x1000>;
- power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_MERGE>;
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ merge@14017000 {
+ compatible = "mediatek,mt8173-disp-merge";
+ reg = <0 0x14017000 0 0x1000>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_MERGE>;
+ clock-names = "merge";
+ };
};
- merge5: disp_vpp_merge5@1c110000 {
- compatible = "mediatek,mt8195-disp-merge";
- reg = <0 0x1c110000 0 0x1000>;
- interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
- <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
- clock-names = "merge","merge_async";
- power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
- mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
- mediatek,merge-fifo-en = <1>;
- resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
- };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
index 842ba7b07a34..00e6a1041a9b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
@@ -71,13 +71,22 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
- mutex: mutex@14020000 {
- compatible = "mediatek,mt8173-disp-mutex";
- reg = <0 0x14020000 0 0x1000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_MUTEX_32K>;
- mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
- <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mutex: mutex@14020000 {
+ compatible = "mediatek,mt8173-disp-mutex";
+ reg = <0 0x14020000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
+ <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
index 7519db315217..853fcb9db2be 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
@@ -45,9 +45,15 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/clock/mt8173-clk.h>
- od@14023000 {
- compatible = "mediatek,mt8173-disp-od";
- reg = <0 0x14023000 0 0x1000>;
- clocks = <&mmsys CLK_MM_DISP_OD>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ od@14023000 {
+ compatible = "mediatek,mt8173-disp-od";
+ reg = <0 0x14023000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_OD>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
index e3cef99d0f98..da999ba53b7c 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
@@ -66,13 +66,23 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
- ovl_2l0: ovl@14009000 {
- compatible = "mediatek,mt8183-disp-ovl-2l";
- reg = <0 0x14009000 0 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
- clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
- iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ovl_2l0: ovl@14009000 {
+ compatible = "mediatek,mt8183-disp-ovl-2l";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index fc691d00c60e..f77094e61443 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -81,13 +81,23 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+ #include <dt-bindings/memory/mt8173-larb-port.h>
- ovl0: ovl@1400c000 {
- compatible = "mediatek,mt8173-disp-ovl";
- reg = <0 0x1400c000 0 0x1000>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OVL0>;
- iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
index 6ac1da2e8871..2d769422e29f 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
@@ -58,12 +58,21 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8192-clk.h>
+ #include <dt-bindings/power/mt8192-power.h>
+ #include <dt-bindings/gce/mt8192-gce.h>
- postmask0: postmask@1400d000 {
- compatible = "mediatek,mt8192-disp-postmask";
- reg = <0 0x1400d000 0 0x1000>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
- power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
- clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ postmask0: postmask@1400d000 {
+ compatible = "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index b56e22fbcd52..e8c72afa0630 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -94,14 +94,24 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+ #include <dt-bindings/memory/mt8173-larb-port.h>
- rdma0: rdma@1400e000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x1400e000 0 0x1000>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA0>;
- iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,rdma-fifosize = <8192>;
- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ rdma0: rdma@1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,rdma-fifo-size = <8192>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
index 4f08e89c1067..35ace1f322e8 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
@@ -49,10 +49,17 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
- split0: split@14018000 {
- compatible = "mediatek,mt8173-disp-split";
- reg = <0 0x14018000 0 0x1000>;
- power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ split0: split@14018000 {
+ compatible = "mediatek,mt8173-disp-split";
+ reg = <0 0x14018000 0 0x1000>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
index 6e8748529e73..b8bb135fe96b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
@@ -51,11 +51,18 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
- ufoe@1401a000 {
- compatible = "mediatek,mt8173-disp-ufoe";
- reg = <0 0x1401a000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_UFOE>;
+ ufoe@1401a000 {
+ compatible = "mediatek,mt8173-disp-ufoe";
+ reg = <0 0x1401a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_UFOE>;
+ };
};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
index f9f00a518edf..7d7cc1ab526b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
@@ -64,13 +64,23 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+ #include <dt-bindings/gce/mt8173-gce.h>
+ #include <dt-bindings/memory/mt8173-larb-port.h>
- wdma0: wdma@14011000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14011000 0 0x1000>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA0>;
- iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ wdma0: wdma@14011000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+ };
};
--
2.18.0
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/4] Fix MediaTek display dt-bindings issues
2022-03-09 13:46 [PATCH v2 0/4] Fix MediaTek display dt-bindings issues jason-jh.lin
` (3 preceding siblings ...)
2022-03-09 13:47 ` [PATCH v2 4/4] dt-bindings: display: mediatek: Fix examples on new bindings jason-jh.lin
@ 2022-03-23 14:09 ` Rob Herring
2022-03-24 13:25 ` Chun-Kuang Hu
4 siblings, 1 reply; 8+ messages in thread
From: Rob Herring @ 2022-03-23 14:09 UTC (permalink / raw)
To: jason-jh.lin, David Airlie, Daniel Vetter
Cc: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno,
Philipp Zabel, Enric Balletbo i Serra, Maxime Coquelin,
Alexandre Torgue, Hsin-Yi Wang, Fei Shao, Moudy Ho, roy-cw.yeh,
CK Hu, Fabien Parent, Nancy Lin, singo.chang, devicetree,
moderated list:ARM/STM32 ARCHITECTURE, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Project_Global_Chrome_Upstream_Group
On Wed, Mar 9, 2022 at 7:47 AM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
>
> The vdosys0 series carried a nice dt-bindings conversion of the old
> txt documentation for the entire mediatek-drm driver, but some of
> the issues in there weren't seen.
>
> This series is fixing all of the issues pointed out by a
> `dt_binding_check` run, followed by `dtbs_check`.
>
> Change in v2:
> - remove mediatek,ethdr.yaml file
> - change include header of mediatek,ovl-2l.yaml from mt8173 to mt8183
>
> AngeloGioacchino Del Regno (3):
> dt-bindings: display: mediatek, mutex: Fix mediatek, gce-events type
> dt-bindings: display: mediatek, ovl: Fix 'iommu' required property
> typo
> dt-bindings: display: mediatek: Fix examples on new bindings
>
> jason-jh.lin (1):
> Revert "dt-bindings: display: mediatek: add ethdr definition for
> mt8195"
Can this series get applied soon? linux-next is still broken.
If it hits Linus' tree, I will be applying them.
Rob
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/4] Fix MediaTek display dt-bindings issues
2022-03-23 14:09 ` [PATCH v2 0/4] Fix MediaTek display dt-bindings issues Rob Herring
@ 2022-03-24 13:25 ` Chun-Kuang Hu
2022-03-24 21:19 ` Rob Herring
0 siblings, 1 reply; 8+ messages in thread
From: Chun-Kuang Hu @ 2022-03-24 13:25 UTC (permalink / raw)
To: Rob Herring
Cc: jason-jh.lin, David Airlie, Daniel Vetter, Matthias Brugger,
Chun-Kuang Hu, AngeloGioacchino Del Regno, Philipp Zabel,
Enric Balletbo i Serra, Maxime Coquelin, Alexandre Torgue,
Hsin-Yi Wang, Fei Shao, Moudy Ho, roy-cw.yeh, CK Hu,
Fabien Parent, Nancy Lin, singo.chang, DTML,
moderated list:ARM/STM32 ARCHITECTURE, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Project_Global_Chrome_Upstream_Group
Hi, Rob:
Rob Herring <robh@kernel.org> 於 2022年3月23日 週三 下午10:10寫道:
>
> On Wed, Mar 9, 2022 at 7:47 AM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
> >
> > The vdosys0 series carried a nice dt-bindings conversion of the old
> > txt documentation for the entire mediatek-drm driver, but some of
> > the issues in there weren't seen.
> >
> > This series is fixing all of the issues pointed out by a
> > `dt_binding_check` run, followed by `dtbs_check`.
> >
> > Change in v2:
> > - remove mediatek,ethdr.yaml file
> > - change include header of mediatek,ovl-2l.yaml from mt8173 to mt8183
> >
> > AngeloGioacchino Del Regno (3):
> > dt-bindings: display: mediatek, mutex: Fix mediatek, gce-events type
> > dt-bindings: display: mediatek, ovl: Fix 'iommu' required property
> > typo
> > dt-bindings: display: mediatek: Fix examples on new bindings
> >
> > jason-jh.lin (1):
> > Revert "dt-bindings: display: mediatek: add ethdr definition for
> > mt8195"
>
> Can this series get applied soon? linux-next is still broken.
>
> If it hits Linus' tree, I will be applying them.
I've applied this series to my tree [1], but now is merge window, so I
plan to send this series through Dave's tree after 5.18-rc1. Would
this be too late for you?
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-fixes
Regards,
Chun-Kuang.
>
> Rob
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/4] Fix MediaTek display dt-bindings issues
2022-03-24 13:25 ` Chun-Kuang Hu
@ 2022-03-24 21:19 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2022-03-24 21:19 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: jason-jh.lin, David Airlie, Daniel Vetter, Matthias Brugger,
AngeloGioacchino Del Regno, Philipp Zabel,
Enric Balletbo i Serra, Maxime Coquelin, Alexandre Torgue,
Hsin-Yi Wang, Fei Shao, Moudy Ho, roy-cw.yeh, CK Hu,
Fabien Parent, Nancy Lin, singo.chang, DTML,
moderated list:ARM/STM32 ARCHITECTURE, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Project_Global_Chrome_Upstream_Group
On Thu, Mar 24, 2022 at 09:25:44PM +0800, Chun-Kuang Hu wrote:
> Hi, Rob:
>
> Rob Herring <robh@kernel.org> 於 2022年3月23日 週三 下午10:10寫道:
> >
> > On Wed, Mar 9, 2022 at 7:47 AM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
> > >
> > > The vdosys0 series carried a nice dt-bindings conversion of the old
> > > txt documentation for the entire mediatek-drm driver, but some of
> > > the issues in there weren't seen.
> > >
> > > This series is fixing all of the issues pointed out by a
> > > `dt_binding_check` run, followed by `dtbs_check`.
> > >
> > > Change in v2:
> > > - remove mediatek,ethdr.yaml file
> > > - change include header of mediatek,ovl-2l.yaml from mt8173 to mt8183
> > >
> > > AngeloGioacchino Del Regno (3):
> > > dt-bindings: display: mediatek, mutex: Fix mediatek, gce-events type
> > > dt-bindings: display: mediatek, ovl: Fix 'iommu' required property
> > > typo
> > > dt-bindings: display: mediatek: Fix examples on new bindings
> > >
> > > jason-jh.lin (1):
> > > Revert "dt-bindings: display: mediatek: add ethdr definition for
> > > mt8195"
> >
> > Can this series get applied soon? linux-next is still broken.
> >
> > If it hits Linus' tree, I will be applying them.
>
> I've applied this series to my tree [1], but now is merge window, so I
> plan to send this series through Dave's tree after 5.18-rc1. Would
> this be too late for you?
Yes, people base their development on -rc1 and it would be nice to have
a functional tree.
There's not really any need to wait to send fixes.
Rob
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-03-24 21:21 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-09 13:46 [PATCH v2 0/4] Fix MediaTek display dt-bindings issues jason-jh.lin
2022-03-09 13:46 ` [PATCH v2 1/4] Revert "dt-bindings: display: mediatek: add ethdr definition for mt8195" jason-jh.lin
2022-03-09 13:47 ` [PATCH v2 2/4] dt-bindings: display: mediatek, mutex: Fix mediatek, gce-events type jason-jh.lin
2022-03-09 13:47 ` [PATCH v2 3/4] dt-bindings: display: mediatek, ovl: Fix 'iommu' required property typo jason-jh.lin
2022-03-09 13:47 ` [PATCH v2 4/4] dt-bindings: display: mediatek: Fix examples on new bindings jason-jh.lin
2022-03-23 14:09 ` [PATCH v2 0/4] Fix MediaTek display dt-bindings issues Rob Herring
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