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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v2 9/9] arm64/sysreg: Generate definitions for SCTLR_EL1
Date: Wed, 16 Mar 2022 17:08:49 +0000	[thread overview]
Message-ID: <20220316170849.1183941-10-broonie@kernel.org> (raw)
In-Reply-To: <20220316170849.1183941-1-broonie@kernel.org>

Automatically generate register definitions for SCTLR_EL1. No functional
change.

Several fields which are defined in the current revision of DDI0487 but
which are not yet used by the kernel are left as RES1 in order to ensure
that the SCTLR_EL1_RES1 mask used for early initialisation of SCTLR_EL1 is
not changed. These are LSMAOE, nTLSMD, EIS, TSCXT and EOS.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 29 --------------
 arch/arm64/tools/sysreg         | 70 +++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+), 29 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index ec985e918bb6..bb48fd537c51 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -197,7 +197,6 @@
 #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
 #define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
 
-#define SYS_SCTLR_EL1			sys_reg(3, 0, 1, 0, 0)
 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
 #define SYS_CPACR_EL1			sys_reg(3, 0, 1, 0, 2)
 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
@@ -673,34 +672,6 @@
 	(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
 
 /* SCTLR_EL1 specific flags. */
-#define SCTLR_EL1_EPAN		(BIT(57))
-#define SCTLR_EL1_ATA0		(BIT(42))
-
-#define SCTLR_EL1_TCF0_SHIFT	38
-#define SCTLR_EL1_TCF0_NONE	UL(0x0)
-#define SCTLR_EL1_TCF0_SYNC	UL(0x1)
-#define SCTLR_EL1_TCF0_ASYNC	UL(0x2)
-#define SCTLR_EL1_TCF0_ASYMM	UL(0x3)
-#define SCTLR_EL1_TCF0_MASK	UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
-
-#define SCTLR_EL1_BT1		(BIT(36))
-#define SCTLR_EL1_BT0		(BIT(35))
-#define SCTLR_EL1_UCI		(BIT(26))
-#define SCTLR_EL1_E0E		(BIT(24))
-#define SCTLR_EL1_SPAN		(BIT(23))
-#define SCTLR_EL1_nTWE		(BIT(18))
-#define SCTLR_EL1_nTWI		(BIT(16))
-#define SCTLR_EL1_UCT		(BIT(15))
-#define SCTLR_EL1_DZE		(BIT(14))
-#define SCTLR_EL1_UMA		(BIT(9))
-#define SCTLR_EL1_SED		(BIT(8))
-#define SCTLR_EL1_ITD		(BIT(7))
-#define SCTLR_EL1_CP15BEN	(BIT(5))
-#define SCTLR_EL1_SA0		(BIT(4))
-
-#define SCTLR_EL1_RES1	((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
-			 (BIT(29)))
-
 #ifdef CONFIG_CPU_BIG_ENDIAN
 #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
 #else
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index f6195ccbf9b8..6248cfbf5288 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -100,6 +100,76 @@ EndEnum
 Res0	3:0
 EndSysreg
 
+Sysreg	SCTLR_EL1	3	0	1	9	9
+Field	63	TIDCP
+Field	62	SPINMASK
+Field	61	NMI
+Field	60	EnTP2
+Res0	59:58
+Field	57	EPAN
+Field	56	EnALS
+Field	55	EnAS0
+Field	54	EnASR
+Field	53	TME
+Field	52	TME0
+Field	51	TMT
+Field	50	TMT0
+Field	49:46	TWEDEL
+Field	45	TWEDEn
+Field	44	DSSBS
+Field	43	ATA
+Field	42	ATA0
+Enum	41:40	TCF
+	0b00	NONE
+	0b01	SYNC
+	0b10	ASYNC
+	0b11	ASYMM
+EndEnum
+Enum	39:38	TCF0
+	0b00	NONE
+	0b01	SYNC
+	0b10	ASYNC
+	0b11	ASYMM
+EndEnum
+Field	37	ITFSB
+Field	36	BT1
+Field	35	BT0
+Res0	34
+Field	33	MSCEn
+Field	32	CMOW
+Field	31	EnIA
+Field	30	EnIB
+Res1	29:28
+Field	27	EnDA
+Field	26	UCI
+Field	25	EE
+Field	24	E0E
+Field	23	SPAN
+Res1	22
+Field	21	IESB
+Res1	20
+Field	19	WXN
+Field	18	nTWE
+Res0	17
+Field	16	nTWI
+Field	15	UCT
+Field	14	DZE
+Field	13	EnDB
+Field	12	I
+Res1	11
+Field	10	EnRCTX
+Field	9	UMA
+Field	8	SED
+Field	7	ITD
+Field	6	nAA
+Field	5	CP15BEN
+Field	4	SA0
+Field	3	SA
+Field	2	C
+Field	1	A
+Field	0	M
+EndSysreg
+
 Sysreg	TTBR0_EL1	3	0	2	0	0
 Field	63:48	ASID
 Field	47:1	BADDR
-- 
2.30.2


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      parent reply	other threads:[~2022-03-16 17:13 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-16 17:08 [PATCH v2 0/9] arm64: Automatic system register definition generation Mark Brown
2022-03-16 17:08 ` [PATCH v2 1/9] arm64/mte: Move shift from definition of TCF0 enumeration values Mark Brown
2022-03-16 17:08 ` [PATCH v2 2/9] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Mark Brown
2022-03-16 17:08 ` [PATCH v2 3/9] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI Mark Brown
2022-03-16 17:08 ` [PATCH v2 4/9] arm64/sysreg: Provide a helper macro for defining sysreg bitmasks Mark Brown
2022-03-23 17:58   ` Mark Rutland
2022-03-23 19:15     ` Mark Brown
2022-03-16 17:08 ` [PATCH v2 5/9] arm64: Add sysreg header generation scripting Mark Brown
2022-03-16 17:08 ` [PATCH v2 6/9] arm64/sysreg: Enable automatic generation of system register definitions Mark Brown
2022-03-16 17:08 ` [PATCH v2 7/9] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Mark Brown
2022-03-16 17:08 ` [PATCH v2 8/9] arm64/sysreg: Generate definitions for TTBRn_EL1 Mark Brown
2022-03-16 17:08 ` Mark Brown [this message]

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