[PATCH v2 00/12] ARM: suniv: dts: update Allwinner F1C100

[PATCH v2 00/12] ARM: suniv: dts: update Allwinner F1C100

[Andre Przywara]

Hi,

an update to the F1C100 DT update series. I dropped the defconfig
patches for now, there is more to them than it seems, and they warrant a
separate series and discussion. Also I dropped the MMC binding patch
(v1 07/14), since Ulf already applied that.
Other than that this tries to clarify the watchdog clock situation in a
new patch (02/12), and fixes some smaller issues, as pointed out by
Samuel (many thanks for that!).

----------

The Allwinner F1C100 SoC didn't see much love since its initial merge in
2018: the originally submitted .dts files were very basic, and didn't
cover such simple peripherals as MMC and SPI.
On top of that the watchdog compatible string was wrong, leading to a
non-functional watchdog and reset functionality.

This series aims to fix that, after the series MMC and SPI work, and
make dtbs_check comes back clean.
This was tested with mounting a filesystem on /dev/mmcblk0 on a
LicheePi Nano, also with accessing the SPI flash through /dev/mtdblock
and mtd_debug. Reboot and watchdog now also work.

Mainline U-Boot recently gained F1C100 support, and those DT updates are
needed there as well to get full MMC and SPI access.

The series is structured as follows:
- Patches 01/12 and 03/12 fix the watchdog, which allows to properly
  reboot the system.
- Patches 04-07 fix some shortcomings of the existing DT files, to make
  them DT binding compliant.
- Patches 08-09 are Jesse's recent MMC patches, with the comments from
  the last version addressed [1].
- Patches 10-12 add SPI support, to enable access to the SPI flash on
  the LicheePi Nano board.

Cheers,
Andre

Changelog v1 ... v2:
- drop multi_v5_defconfig patches (v1 13/14 and 14/14)
- drop MMC bindings patch (v1 07/14): already applied
- dt-binding: move watchdog compatible string among the others
- dt-binding: new patch to clarify watchdog clock source
- dtsi: add missing @0 to cpu node
- add Acks and R-b's
- dtsi: fix ordering of SPI nodes (plus typo in commit message)

Changelog for the MMC patches [1]:
- bindings doc: extend commit message
- .dtsi: extend commit message, re-order mmc0_pins node, add
  drive-strength
- .dts: extend commit message, add alias, regulator and disable-wp

[1] https://lore.kernel.org/linux-arm-kernel/20220130220325.1983918-1-Mr.Bossman075@gmail.com/
[2] https://lore.kernel.org/linux-usb/20200331170219.267732-1-thirtythreeforty@gmail.com/

Andre Przywara (9):
  dt-bindings: watchdog: sunxi: fix F1C100s compatible
  dt-bindings: watchdog: sunxi: clarify clock support
  ARM: dts: suniv: F1C100: fix watchdog compatible
  dt-bindings: arm: sunxi: document LicheePi Nano name
  ARM: dts: suniv: F1C100: fix CPU node
  ARM: dts: suniv: F1C100: fix timer node
  dt-bindings: spi: sunxi: document F1C100 controllers
  ARM: dts: suniv: F1C100: add SPI support
  ARM: dts: suniv: licheepi-nano: add SPI flash

Jesse Taube (3):
  ARM: dts: suniv: F1C100: add clock and reset macros
  ARM: dts: suniv: F1C100: add MMC controllers
  ARM: dts: suniv: licheepi-nano: add microSD card

 .../devicetree/bindings/arm/sunxi.yaml        |   5 +
 .../bindings/spi/allwinner,sun6i-a31-spi.yaml |   1 +
 .../watchdog/allwinner,sun4i-a10-wdt.yaml     |  24 ++--
 .../boot/dts/suniv-f1c100s-licheepi-nano.dts  |  31 ++++++
 arch/arm/boot/dts/suniv-f1c100s.dtsi          | 104 ++++++++++++++++--
 5 files changed, 140 insertions(+), 25 deletions(-)

-- 
2.25.1


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[PATCH v2 01/12] dt-bindings: watchdog: sunxi: fix F1C100s compatible

[Andre Przywara]

The F1C100 series actually features a newer generation watchdog IP, so
the compatible string was wrong.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
index 43afa24513b9..7a26cde0afdd 100644
--- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
@@ -26,10 +26,8 @@ properties:
               - allwinner,sun50i-h616-wdt
               - allwinner,sun50i-r329-wdt
               - allwinner,sun50i-r329-wdt-reset
+              - allwinner,suniv-f1c100s-wdt
           - const: allwinner,sun6i-a31-wdt
-      - items:
-          - const: allwinner,suniv-f1c100s-wdt
-          - const: allwinner,sun4i-a10-wdt
       - const: allwinner,sun20i-d1-wdt
       - items:
           - const: allwinner,sun20i-d1-wdt-reset
-- 
2.25.1


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Re: [PATCH v2 01/12] dt-bindings: watchdog: sunxi: fix F1C100s compatible

[Rob Herring]

On Thu, 17 Mar 2022 16:23:38 +0000, Andre Przywara wrote:
> The F1C100 series actually features a newer generation watchdog IP, so
> the compatible string was wrong.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v2 01/12] dt-bindings: watchdog: sunxi: fix F1C100s compatible

[Samuel Holland]

On 3/17/22 11:23 AM, Andre Przywara wrote:
> The F1C100 series actually features a newer generation watchdog IP, so
> the compatible string was wrong.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Samuel Holland <samuel@sholland.org>

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[PATCH v2 02/12] dt-bindings: watchdog: sunxi: clarify clock support

[Andre Przywara]

Most Allwinner SoCs have just one input clock to drive the watchdog
peripheral. So far this is the 24 MHz "HOSC" oscillator, divided down
internally to 32 KHz.
The F1C100 series watchdog however uses the unchanged 32 KHz "LOSC" as
its only clock input, which has the same effect, but let's the binding
description mismatch.

Change the binding description to name the clocks more loosely, so both
the LOSC and divided HOSC match the description. As the fixed clock names
now make less sense, drop them from SoCs supporting just one clock
input, they were not used by any DT anyway.

For the newer SoCs, supporting a choice of two input clocks, we keep
both the description and clock-names requirement.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../watchdog/allwinner,sun4i-a10-wdt.yaml     | 20 ++++++++-----------
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
index 7a26cde0afdd..cbcf19f51411 100644
--- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
@@ -39,14 +39,8 @@ properties:
   clocks:
     minItems: 1
     items:
-      - description: High-frequency oscillator input, divided internally
-      - description: Low-frequency oscillator input, only found on some variants
-
-  clock-names:
-    minItems: 1
-    items:
-      - const: hosc
-      - const: losc
+      - description: 32 KHz input clock
+      - description: secondary clock source
 
   interrupts:
     maxItems: 1
@@ -71,9 +65,14 @@ then:
   properties:
     clocks:
       minItems: 2
+      items:
+        - description: High-frequency oscillator input, divided internally
+        - description: Low-frequency oscillator input
 
     clock-names:
-      minItems: 2
+      items:
+        - const: hosc
+        - const: losc
 
   required:
     - clock-names
@@ -83,9 +82,6 @@ else:
     clocks:
       maxItems: 1
 
-    clock-names:
-      maxItems: 1
-
 unevaluatedProperties: false
 
 examples:
-- 
2.25.1


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Re: [PATCH v2 02/12] dt-bindings: watchdog: sunxi: clarify clock support

[Rob Herring]

On Thu, 17 Mar 2022 16:23:39 +0000, Andre Przywara wrote:
> Most Allwinner SoCs have just one input clock to drive the watchdog
> peripheral. So far this is the 24 MHz "HOSC" oscillator, divided down
> internally to 32 KHz.
> The F1C100 series watchdog however uses the unchanged 32 KHz "LOSC" as
> its only clock input, which has the same effect, but let's the binding
> description mismatch.
> 
> Change the binding description to name the clocks more loosely, so both
> the LOSC and divided HOSC match the description. As the fixed clock names
> now make less sense, drop them from SoCs supporting just one clock
> input, they were not used by any DT anyway.
> 
> For the newer SoCs, supporting a choice of two input clocks, we keep
> both the description and clock-names requirement.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  .../watchdog/allwinner,sun4i-a10-wdt.yaml     | 20 ++++++++-----------
>  1 file changed, 8 insertions(+), 12 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v2 02/12] dt-bindings: watchdog: sunxi: clarify clock support

[Samuel Holland]

On 3/17/22 11:23 AM, Andre Przywara wrote:
> Most Allwinner SoCs have just one input clock to drive the watchdog
> peripheral. So far this is the 24 MHz "HOSC" oscillator, divided down
> internally to 32 KHz.
> The F1C100 series watchdog however uses the unchanged 32 KHz "LOSC" as
> its only clock input, which has the same effect, but let's the binding
> description mismatch.
> 
> Change the binding description to name the clocks more loosely, so both
> the LOSC and divided HOSC match the description. As the fixed clock names
> now make less sense, drop them from SoCs supporting just one clock
> input, they were not used by any DT anyway.
> 
> For the newer SoCs, supporting a choice of two input clocks, we keep
> both the description and clock-names requirement.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Samuel Holland <samuel@sholland.org>

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Re: [PATCH v2 02/12] dt-bindings: watchdog: sunxi: clarify clock support

[Guenter Roeck]

On Thu, Mar 17, 2022 at 04:23:39PM +0000, Andre Przywara wrote:
> Most Allwinner SoCs have just one input clock to drive the watchdog
> peripheral. So far this is the 24 MHz "HOSC" oscillator, divided down
> internally to 32 KHz.
> The F1C100 series watchdog however uses the unchanged 32 KHz "LOSC" as
> its only clock input, which has the same effect, but let's the binding
> description mismatch.
> 
> Change the binding description to name the clocks more loosely, so both
> the LOSC and divided HOSC match the description. As the fixed clock names
> now make less sense, drop them from SoCs supporting just one clock
> input, they were not used by any DT anyway.
> 
> For the newer SoCs, supporting a choice of two input clocks, we keep
> both the description and clock-names requirement.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Samuel Holland <samuel@sholland.org>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

> ---
>  .../watchdog/allwinner,sun4i-a10-wdt.yaml     | 20 ++++++++-----------
>  1 file changed, 8 insertions(+), 12 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
> index 7a26cde0afdd..cbcf19f51411 100644
> --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
> @@ -39,14 +39,8 @@ properties:
>    clocks:
>      minItems: 1
>      items:
> -      - description: High-frequency oscillator input, divided internally
> -      - description: Low-frequency oscillator input, only found on some variants
> -
> -  clock-names:
> -    minItems: 1
> -    items:
> -      - const: hosc
> -      - const: losc
> +      - description: 32 KHz input clock
> +      - description: secondary clock source
>  
>    interrupts:
>      maxItems: 1
> @@ -71,9 +65,14 @@ then:
>    properties:
>      clocks:
>        minItems: 2
> +      items:
> +        - description: High-frequency oscillator input, divided internally
> +        - description: Low-frequency oscillator input
>  
>      clock-names:
> -      minItems: 2
> +      items:
> +        - const: hosc
> +        - const: losc
>  
>    required:
>      - clock-names
> @@ -83,9 +82,6 @@ else:
>      clocks:
>        maxItems: 1
>  
> -    clock-names:
> -      maxItems: 1
> -
>  unevaluatedProperties: false
>  
>  examples:

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[PATCH v2 03/12] ARM: dts: suniv: F1C100: fix watchdog compatible

[Andre Przywara]

The F1C100 series of SoCs actually have their watchdog IP being
compatible with the newer Allwinner generation, not the older one.

The currently described sun4i-a10-wdt actually does not work, neither
the watchdog functionality (just never fires), nor the reset part
(reboot hangs).

Replace the compatible string with the one used by the newer generation.
Verified to work with both the watchdog and reboot functionality on a
LicheePi Nano.

Also add the missing interrupt line and clock source, to make it binding
compliant.

Fixes: 4ba16d17efdd ("ARM: dts: suniv: add initial DTSI file for F1C100s")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 6100d3b75f61..def830101448 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -104,8 +104,10 @@ timer@1c20c00 {
 
 		wdt: watchdog@1c20ca0 {
 			compatible = "allwinner,suniv-f1c100s-wdt",
-				     "allwinner,sun4i-a10-wdt";
+				     "allwinner,sun6i-a31-wdt";
 			reg = <0x01c20ca0 0x20>;
+			interrupts = <16>;
+			clocks = <&osc32k>;
 		};
 
 		uart0: serial@1c25000 {
-- 
2.25.1


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[PATCH v2 04/12] dt-bindings: arm: sunxi: document LicheePi Nano name

[Andre Przywara]

The top level LicheePi Nano compatible name was never documented in the
bindings, so add the currently used string.

As for the manufacturer name, Samuel reports:
==========
From what  I can tell, "Lichee Pi Nano" [1][2] is the original board, and the
"Sipeed Lichee Nano" [3] is a newer batch by some of the same people [4].

Other than the silkscreen and the addition of the resistive touchscreen IC, the
boards look identical. And in fact I was able to find an intermediate version of
the schematic [5] that uses the old styling but includes the touchscreen IC.
==========

[1]: https://licheepizero.us/
[2]: http://nano.lichee.pro/
[3]: https://wiki.sipeed.com/hardware/en/lichee/Nano/Nano.html
[4]: see e.g. http://bbs.lichee.pro/
[5]:
https://github.com/hongxuyao/F1C100s_with_Keil_RTX4_emWin5/blob/spl-separated/doc/lichee-nano/lichee_nano-Schematic.pdf

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index c8a3102c0fde..a7e7b2e79616 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -391,6 +391,11 @@ properties:
           - const: libretech,all-h5-cc-h5
           - const: allwinner,sun50i-h5
 
+      - description: Lichee Pi Nano
+        items:
+          - const: licheepi,licheepi-nano
+          - const: allwinner,suniv-f1c100s
+
       - description: Lichee Pi One
         items:
           - const: licheepi,licheepi-one
-- 
2.25.1


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[PATCH v2 05/12] ARM: dts: suniv: F1C100: add clock and reset macros

[Andre Przywara]

From: Jesse Taube <mr.bossman075@gmail.com>

Include clock and reset macros and replace magic numbers.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index def830101448..922efd5e9457 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -4,6 +4,9 @@
  * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
  */
 
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -82,7 +85,7 @@ pio: pinctrl@1c20800 {
 			compatible = "allwinner,suniv-f1c100s-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <38>, <39>, <40>;
-			clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
@@ -116,8 +119,8 @@ uart0: serial@1c25000 {
 			interrupts = <1>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 38>;
-			resets = <&ccu 24>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
 			status = "disabled";
 		};
 
@@ -127,8 +130,8 @@ uart1: serial@1c25400 {
 			interrupts = <2>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 39>;
-			resets = <&ccu 25>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
 			status = "disabled";
 		};
 
@@ -138,8 +141,8 @@ uart2: serial@1c25800 {
 			interrupts = <3>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 40>;
-			resets = <&ccu 26>;
+			clocks = <&ccu CLK_BUS_UART2>;
+			resets = <&ccu RST_BUS_UART2>;
 			status = "disabled";
 		};
 	};
-- 
2.25.1


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[PATCH v2 06/12] ARM: dts: suniv: F1C100: fix CPU node

[Andre Przywara]

The /cpu node in the f1c100s.dtsi is not spec compliant, it's missing
the reg property, and the corresponding address and size cells
properties.

Add them to make the bindings check pass.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 922efd5e9457..0a7fa37bbd24 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -29,9 +29,13 @@ osc32k: clk-32k {
 	};
 
 	cpus {
-		cpu {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
 			compatible = "arm,arm926ej-s";
 			device_type = "cpu";
+			reg = <0x0>;
 		};
 	};
 
-- 
2.25.1


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Re: [PATCH v2 06/12] ARM: dts: suniv: F1C100: fix CPU node

[Samuel Holland]

On 3/17/22 11:23 AM, Andre Przywara wrote:
> The /cpu node in the f1c100s.dtsi is not spec compliant, it's missing
> the reg property, and the corresponding address and size cells
> properties.
> 
> Add them to make the bindings check pass.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Samuel Holland <samuel@sholland.org>

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[PATCH v2 07/12] ARM: dts: suniv: F1C100: fix timer node

[Andre Przywara]

The Allwinner F1C100s has three timer instances, each with their own
interrupt line.

Add the missing two interrupts to the DT node, to match the DT binding.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 0a7fa37bbd24..f455e276521e 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -105,7 +105,7 @@ uart0_pe_pins: uart0-pe-pins {
 		timer@1c20c00 {
 			compatible = "allwinner,suniv-f1c100s-timer";
 			reg = <0x01c20c00 0x90>;
-			interrupts = <13>;
+			interrupts = <13>, <14>, <15>;
 			clocks = <&osc24M>;
 		};
 
-- 
2.25.1


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[PATCH v2 08/12] ARM: dts: suniv: F1C100: add MMC controllers

[Andre Przywara]

From: Jesse Taube <mr.bossman075@gmail.com>

The F1C100 series contains two MMC controllers, where the first one is
typically connected to an (micro)SD card slot (as this is the one the
BROM is able to boot from).
Describe the two controllers in the SoC .dtsi.
We also add the pinctrl description for MMC0, since this is the only
pin set supporting that function anyway, and SD cards are very common
across boards.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 42 ++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index f455e276521e..59e0bd952f50 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -69,6 +69,42 @@ otg_sram: sram-section@0 {
 			};
 		};
 
+		mmc0: mmc@1c0f000 {
+			compatible = "allwinner,suniv-f1c100s-mmc",
+				     "allwinner,sun7i-a20-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC0>,
+				 <&ccu CLK_MMC0>,
+				 <&ccu CLK_MMC0_OUTPUT>,
+				 <&ccu CLK_MMC0_SAMPLE>;
+			clock-names = "ahb", "mmc", "output", "sample";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			interrupts = <23>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@1c10000 {
+			compatible = "allwinner,suniv-f1c100s-mmc",
+				     "allwinner,sun7i-a20-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC1>,
+				 <&ccu CLK_MMC1>,
+				 <&ccu CLK_MMC1_OUTPUT>,
+				 <&ccu CLK_MMC1_SAMPLE>;
+			clock-names = "ahb", "mmc", "output", "sample";
+			resets = <&ccu RST_BUS_MMC1>;
+			reset-names = "ahb";
+			interrupts = <24>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		ccu: clock@1c20000 {
 			compatible = "allwinner,suniv-f1c100s-ccu";
 			reg = <0x01c20000 0x400>;
@@ -96,6 +132,12 @@ pio: pinctrl@1c20800 {
 			#interrupt-cells = <3>;
 			#gpio-cells = <3>;
 
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+				function = "mmc0";
+				drive-strength = <30>;
+			};
+
 			uart0_pe_pins: uart0-pe-pins {
 				pins = "PE0", "PE1";
 				function = "uart0";
-- 
2.25.1


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[PATCH v2 09/12] ARM: dts: suniv: licheepi-nano: add microSD card

[Andre Przywara]

From: Jesse Taube <mr.bossman075@gmail.com>

Enable MMC0 and supply the board setting to enable the microSD card slot
on the LicheePi Nano board.
Apart from the always missing write protect switch on microSD slots,
the card-detect pin is not connected to anything, so we use the
broken-cd property.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Andre: add alias and vmmc supply]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
---
 .../arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index a1154e6c7cb5..8fa79a1d1d2d 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -11,12 +11,28 @@ / {
 	compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
 
 	aliases {
+		mmc0 = &mmc0;
 		serial0 = &uart0;
 	};
 
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&mmc0 {
+	broken-cd;
+	bus-width = <4>;
+	disable-wp;
+	status = "okay";
+	vmmc-supply = <&reg_vcc3v3>;
 };
 
 &uart0 {
-- 
2.25.1


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[PATCH v2 10/12] dt-bindings: spi: sunxi: document F1C100 controllers

[Andre Przywara]

The Allwinner F1C100 series contains two SPI controllers, which are
compatible to the IP block used in the Allwinner H3 as well.
The only difference in the integration is the missing mod clock in the
F1C100, but that does not affect the SPI controller binding, as we can
still supply the correct clock (AHB parent) easily.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
index 908248260afa..ca4c95345a49 100644
--- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
@@ -26,6 +26,7 @@ properties:
               - allwinner,sun8i-r40-spi
               - allwinner,sun50i-h6-spi
               - allwinner,sun50i-h616-spi
+              - allwinner,suniv-f1c100s-spi
           - const: allwinner,sun8i-h3-spi
 
   reg:
-- 
2.25.1


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[PATCH v2 11/12] ARM: dts: suniv: F1C100: add SPI support

[Andre Przywara]

The F1C100 series contains two SPI controllers, and many boards use SPI0
for a SPI flash, as the BROM is able to boot from that.

Describe the two controllers in the SoC .dtsi, and also add the PortC
pins for SPI0, since this is where BROM looks at when trying to boot
from the commonly used SPI flash.

The SPI controller seems to be the same as in the H3 chips, but it lacks
a separate mod clock. The manual says it's connected to AHB directly.
We don't export that AHB clock directly, but can use the AHB *gate* clock
as a clock source, since the SPI driver is not supposed to change the AHB
frequency anyway.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 33 ++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 59e0bd952f50..0edc1724407b 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -69,6 +69,34 @@ otg_sram: sram-section@0 {
 			};
 		};
 
+		spi0: spi@1c05000 {
+			compatible = "allwinner,suniv-f1c100s-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c05000 0x1000>;
+			interrupts = <10>;
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI0>;
+			status = "disabled";
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@1c06000 {
+			compatible = "allwinner,suniv-f1c100s-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c06000 0x1000>;
+			interrupts = <11>;
+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI1>;
+			status = "disabled";
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		mmc0: mmc@1c0f000 {
 			compatible = "allwinner,suniv-f1c100s-mmc",
 				     "allwinner,sun7i-a20-mmc";
@@ -138,6 +166,11 @@ mmc0_pins: mmc0-pins {
 				drive-strength = <30>;
 			};
 
+			spi0_pc_pins: spi0-pc-pins {
+				pins = "PC0", "PC1", "PC2", "PC3";
+				function = "spi0";
+			};
+
 			uart0_pe_pins: uart0-pe-pins {
 				pins = "PE0", "PE1";
 				function = "uart0";
-- 
2.25.1


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Re: [PATCH v2 11/12] ARM: dts: suniv: F1C100: add SPI support

[Samuel Holland]

On 3/17/22 11:23 AM, Andre Przywara wrote:
> The F1C100 series contains two SPI controllers, and many boards use SPI0
> for a SPI flash, as the BROM is able to boot from that.
> 
> Describe the two controllers in the SoC .dtsi, and also add the PortC
> pins for SPI0, since this is where BROM looks at when trying to boot
> from the commonly used SPI flash.
> 
> The SPI controller seems to be the same as in the H3 chips, but it lacks
> a separate mod clock. The manual says it's connected to AHB directly.
> We don't export that AHB clock directly, but can use the AHB *gate* clock
> as a clock source, since the SPI driver is not supposed to change the AHB
> frequency anyway.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Samuel Holland <samuel@sholland.org>

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[PATCH v2 12/12] ARM: dts: suniv: licheepi-nano: add SPI flash

[Andre Przywara]

Most LicheePi Nano boards come with soldered SPI flash, so enable SPI0
in the .dts and describe the flash chip. There is evidence of different
flash chips used, also of boards with no flash chip soldered, but the
Winbond 16MiB model is the most common, so use that for the compatible
string.  The actual flash chip model will be auto-detected at runtime
anyway.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
---
 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index 8fa79a1d1d2d..04e59b8381cb 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -13,6 +13,7 @@ / {
 	aliases {
 		mmc0 = &mmc0;
 		serial0 = &uart0;
+		spi0 = &spi0;
 	};
 
 	chosen {
@@ -35,6 +36,20 @@ &mmc0 {
 	vmmc-supply = <&reg_vcc3v3>;
 };
 
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pc_pins>;
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+	};
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pe_pins>;
-- 
2.25.1


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Re: [PATCH v2 00/12] ARM: suniv: dts: update Allwinner F1C100

[Jernej Škrabec]

Dne četrtek, 17. marec 2022 ob 17:23:37 CEST je Andre Przywara napisal(a):
> Hi,
> 
> an update to the F1C100 DT update series. I dropped the defconfig
> patches for now, there is more to them than it seems, and they warrant a
> separate series and discussion. Also I dropped the MMC binding patch
> (v1 07/14), since Ulf already applied that.
> Other than that this tries to clarify the watchdog clock situation in a
> new patch (02/12), and fixes some smaller issues, as pointed out by
> Samuel (many thanks for that!).
> 
> ----------
> 
> The Allwinner F1C100 SoC didn't see much love since its initial merge in
> 2018: the originally submitted .dts files were very basic, and didn't
> cover such simple peripherals as MMC and SPI.
> On top of that the watchdog compatible string was wrong, leading to a
> non-functional watchdog and reset functionality.
> 
> This series aims to fix that, after the series MMC and SPI work, and
> make dtbs_check comes back clean.
> This was tested with mounting a filesystem on /dev/mmcblk0 on a
> LicheePi Nano, also with accessing the SPI flash through /dev/mtdblock
> and mtd_debug. Reboot and watchdog now also work.
> 
> Mainline U-Boot recently gained F1C100 support, and those DT updates are
> needed there as well to get full MMC and SPI access.
> 
> The series is structured as follows:
> - Patches 01/12 and 03/12 fix the watchdog, which allows to properly
>   reboot the system.
> - Patches 04-07 fix some shortcomings of the existing DT files, to make
>   them DT binding compliant.
> - Patches 08-09 are Jesse's recent MMC patches, with the comments from
>   the last version addressed [1].
> - Patches 10-12 add SPI support, to enable access to the SPI flash on
>   the LicheePi Nano board.

Applied to sunxi/dt-for-5.19, thanks!

Best regards,
Jernej

> 
> Cheers,
> Andre
> 
> Changelog v1 ... v2:
> - drop multi_v5_defconfig patches (v1 13/14 and 14/14)
> - drop MMC bindings patch (v1 07/14): already applied
> - dt-binding: move watchdog compatible string among the others
> - dt-binding: new patch to clarify watchdog clock source
> - dtsi: add missing @0 to cpu node
> - add Acks and R-b's
> - dtsi: fix ordering of SPI nodes (plus typo in commit message)
> 
> Changelog for the MMC patches [1]:
> - bindings doc: extend commit message
> - .dtsi: extend commit message, re-order mmc0_pins node, add
>   drive-strength
> - .dts: extend commit message, add alias, regulator and disable-wp
> 
> [1] https://lore.kernel.org/linux-arm-kernel/20220130220325.1983918-1-Mr.Bossman075@gmail.com/
> [2] https://lore.kernel.org/linux-usb/20200331170219.267732-1-thirtythreeforty@gmail.com/
> 
> Andre Przywara (9):
>   dt-bindings: watchdog: sunxi: fix F1C100s compatible
>   dt-bindings: watchdog: sunxi: clarify clock support
>   ARM: dts: suniv: F1C100: fix watchdog compatible
>   dt-bindings: arm: sunxi: document LicheePi Nano name
>   ARM: dts: suniv: F1C100: fix CPU node
>   ARM: dts: suniv: F1C100: fix timer node
>   dt-bindings: spi: sunxi: document F1C100 controllers
>   ARM: dts: suniv: F1C100: add SPI support
>   ARM: dts: suniv: licheepi-nano: add SPI flash
> 
> Jesse Taube (3):
>   ARM: dts: suniv: F1C100: add clock and reset macros
>   ARM: dts: suniv: F1C100: add MMC controllers
>   ARM: dts: suniv: licheepi-nano: add microSD card
> 
>  .../devicetree/bindings/arm/sunxi.yaml        |   5 +
>  .../bindings/spi/allwinner,sun6i-a31-spi.yaml |   1 +
>  .../watchdog/allwinner,sun4i-a10-wdt.yaml     |  24 ++--
>  .../boot/dts/suniv-f1c100s-licheepi-nano.dts  |  31 ++++++
>  arch/arm/boot/dts/suniv-f1c100s.dtsi          | 104 ++++++++++++++++--
>  5 files changed, 140 insertions(+), 25 deletions(-)
> 
> -- 
> 2.25.1
> 
> 



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