From: Alexandre Bailon <abailon@baylibre.com>
To: robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com,
p.zabel@pengutronix.de
Cc: rafael@kernel.org, daniel.lezcano@linaro.org, amitk@kernel.org,
rui.zhang@intel.com, michael.kao@mediatek.com,
ben.tseng@mediatek.com, ethan.chang@mediatek.com,
frank-w@public-files.de, linux-pm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, khilman@baylibre.com,
Tinghan Shen <tinghan.shen@mediatek.com>,
Alexandre Bailon <abailon@baylibre.com>
Subject: [PATCH v6 7/7] arm64: dts: mt8195: Add thermal zone
Date: Thu, 12 May 2022 14:24:33 +0200 [thread overview]
Message-ID: <20220512122433.1399802-8-abailon@baylibre.com> (raw)
In-Reply-To: <20220512122433.1399802-1-abailon@baylibre.com>
From: Tinghan Shen <tinghan.shen@mediatek.com>
This adds the thermal zone for the mt8195.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Ben Tseng <ben.tseng@mediatek.com>
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 103 +++++++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 12887fb4d0d1..d6e5b595a89f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -823,6 +823,21 @@ spi0: spi@1100a000 {
status = "disabled";
};
+ lvts: lvts@1100b000 {
+ compatible = "mediatek,mt8195-lvts";
+ #thermal-sensor-cells = <1>;
+ reg = <0 0x1100b000 0 0x1000>,
+ <0 0x11278000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+ clock-names = "lvts_clk";
+ resets = <&infracfg_rst 1>,
+ <&infracfg_rst 2>;
+ nvmem-cells = <&lvts_e_data1 &lvts_e_data2>;
+ nvmem-cell-names = "e_data1","e_data2";
+ };
+
spi1: spi@11010000 {
compatible = "mediatek,mt8195-spi",
"mediatek,mt6765-spi";
@@ -1627,4 +1642,92 @@ vencsys_core1: clock-controller@1b000000 {
#clock-cells = <1>;
};
};
+
+ thermal_zones: thermal-zones {
+ cpu_big1 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 0>;
+ };
+ cpu_big2 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 1>;
+ };
+ cpu_big3 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 2>;
+ };
+ cpu_big4 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 3>;
+ };
+ cpu_little1{
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 4>;
+ };
+ cpu_little2 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 5>;
+ };
+ cpu_little3 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 6>;
+ };
+ cpu_little4 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 7>;
+ };
+ vpu1 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 8>;
+ };
+ vpu2 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 9>;
+ };
+ gpu1 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 10>;
+ };
+ gpu2 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 11>;
+ };
+ vdec {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 12>;
+ };
+ img {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 13>;
+ };
+ infra {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 14>;
+ };
+ cam1 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 15>;
+ };
+ cam2 {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 16>;
+ };
+ };
};
--
2.35.1
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next prev parent reply other threads:[~2022-05-12 13:34 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-12 12:24 [PATCH v6 0/7] Add LVTS architecture thermal Alexandre Bailon
2022-05-12 12:24 ` [PATCH v6 1/7] thermal: mediatek: Relocate driver to mediatek folder Alexandre Bailon
2022-05-17 11:54 ` Rex-BC Chen
2022-05-12 12:24 ` [PATCH v6 2/7] dt-bindings: thermal: Add binding document for mt6873 thermal controller Alexandre Bailon
2022-05-12 14:25 ` Krzysztof Kozlowski
2022-05-17 17:59 ` Rob Herring
2022-05-12 12:24 ` [PATCH v6 3/7] thermal: mediatek: Add LVTS drivers for SoC theraml zones Alexandre Bailon
2022-05-12 14:29 ` Krzysztof Kozlowski
2022-05-17 12:13 ` Rex-BC Chen
2022-05-12 12:24 ` [PATCH v6 4/7] dt-bindings: thermal: Add binding document for mt8195 thermal controller Alexandre Bailon
2022-05-12 14:30 ` Krzysztof Kozlowski
2022-05-12 12:24 ` [PATCH v6 5/7] thermal: mediatek: Add thermal zone settings for mt8195 Alexandre Bailon
2022-05-12 12:24 ` [PATCH v6 6/7] arm64: dts: mt8195: Add efuse node to mt8195 Alexandre Bailon
2022-05-12 12:24 ` Alexandre Bailon [this message]
2022-05-12 14:32 ` [PATCH v6 7/7] arm64: dts: mt8195: Add thermal zone Krzysztof Kozlowski
2022-05-12 12:33 ` [PATCH v6 0/7] Add LVTS architecture thermal Lothar Waßmann
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