* [PATCH v15 0/3] media: mediatek: support mdp3 on mt8183 platform
@ 2022-05-12 9:23 Moudy Ho
2022-05-12 9:23 ` [PATCH v15 1/3] dt-binding: mediatek: add bindings for MediaTek MDP3 components Moudy Ho
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Moudy Ho @ 2022-05-12 9:23 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Krzysztof Kozlowski, Hans Verkuil
Cc: Chun-Kuang Hu, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
Benjamin Gaignard, AngeloGioacchino Del Regno, daoyuan huang,
Ping-Hsun Wu, allen-kh.cheng, xiandong.wang, randy.wu, moudy.ho,
jason-jh.lin, roy-cw.yeh, river.cheng,
Project_Global_Chrome_Upstream_Group, cellopoint.kai
Change since v14:
- Rebase on v5.18-rc6
- Depend on:
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=640926
- In response to CMDQ API change, replace the function "cmdq_pkt_flush_async"
with the standard APIs of mbox
- Fix the description of "mediatek,gce-client-reg" property in MDP3-related
bindings
Change since v13:
- Rebase on v5.18-rc4
- Depend on:
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=636041
- Remove advanced functionality about ISP settings for direct link cases.
- Remove the software designation in the mt8183 dts and
revise corresponding bindings.
Change since v12:
- Rebase on linux-next
- Depend on:
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=630948
- Remove messages related to routing information in MDP3, and leave the related
settings in MMSYS.
- Remove unnecessary phandle and redundant property in RDMA dt-binding and
adjust the corresponding driver.
- Revise MDP3 node name in dts.
- Removed unnecessary functions, mutex and work queue in MDP3 driver
- Fixed format mapping error for V4L2_PIX_FMT_RGB565X
Change since v11:
- Rebase on linux-next tag:next-20220316
- Depend on:
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=624281
- Remove redundant hardware index in data-binding suggested by Rob Herring.
- Referring to Rob Herring's suggestion to improve some descriptions in the
RDMA dt-binding
- Move MDP3 file folder from "./drive/media/platform/mtk-mdp3" to
"./driver/media/platform/mediatek/mdp3"
- Fixed the V4L2 and MDP color format mapping error in RGB565 which
checked by Benjamin Gaignard
Change since v10:
- The routing table needs to be discarded, and the calculation result
on the SCP side is used to write a suitable mux setting for
1 input port and 2 output ports.
- Adjust dts parsing flow to remove redundant HW IDs.
- Fix memory leak caused by no free path information in function "mdp_cmdq_send".
Change since v9:
- Keep only the MDP3 driver patches and split the remaining mmsys and
mutex patches into another mail.
- Move mutex mod settings to corresponding driver and make relevant adjustments
for this in MDP3 driver.
- Fix compile warning reported by kernel test robot.
Change since v8:
- Rebase on v5.16-rc2.
- Refer to Angelo's suggestion, adjust the register writing format to increase
readability and significance.
- Refer to Angelo's suggestion, adjust or reduce inappropriate debugging
messages.
- Refer to Rob Herring's suggestion to correct the the binding file
to make it with the specification.
- Fix compile warning reported by kernel test robot.
Change since v7:
- Rebase on v5.15-rc6.
- Revise several V4L2 M2M settings to pass v4l2-compliance test.
- Integrate those same component dt-binding documents of DRM and MDP, and
move them under the MMSYS domain.
- Split MMSYS and MUTEX into two different files according to
their functional properties.
Changes since v6:
- Refactor GCE event to corresponding node.
- Fix dt_binding_check fail.
- Fix compilation errors.
Changes since v5:
- Rebase on v5.14-rc6.
- Move MMSYS/Mutex settings to corresponding driver.
- Revise the software license description and copyright.
- Remove unnecessary enum. or definitions.
- Optimize platform/chip definition conditions.
- Use general printing functions instead of MDP3 private ones.
- Fix compile warning.
Changes since v4:
- Rebase on v5.13-rc1.
- Remove the CMDQ flush flow to match the CMDQ API change.
- Integrate four of MDP's direct-link subcomponents into MDP controller node
from syscon node to avoid illegal clock usage.
- Rewrite dt-binding in a JSON compatible subset of YAML
- Fix a bit of macro argument precedence.
Changes since v3:
- Rebase on v5.9-rc1.
- modify code for review comment from Rob Herring, cancel multiple nodes using
same register base situation.
- control IOMMU port through pm runtime get/put to DMA components' device.
- SCP(VPU) driver revision.
- stop queuing jobs(remove flush_workqueue()) after mdp_m2m_release().
- add computation of plane address with data_offset.
- fix scale ratio check issue.
- add default v4l2_format setting.
Changes since v2:
- modify code for review comment from Tomasz Figa & Alexandre Courbot
- review comment from Rob Herring will offer code revision in v4, due to
it's related to device node modification, will need to modify code
architecture
Changes since v1:
- modify code for CMDQ v3 API support
- EC ipi cmd migration
- fix compliance test fail item (m2m cmd with -f) due to there is two problem in runing all format(-f) cmd:
1. out of memory before test complete
Due to capture buffer mmap (refcount + 1) after reqbuf but seems
no corresponding munmap called before device close.
There are total 12XX items(formats) in format test and each format
alloc 8 capture/output buffers.
2. unceasingly captureBufs() (randomly)
Seems the break statement didn't catch the count == 0 situation:
In v4l2-test-buffers.cpp, function: captureBufs()
...
count--;
if (!node->is_m2m && !count)
break;
Log is as attachment
Hi,
This patch is used to present Media Data Path 3 (MDP3)
which provided scaling and color format conversion.
support using GCE to write register in critical time limitation.
support V4L2 m2m device control.
Moudy Ho (3):
dt-binding: mediatek: add bindings for MediaTek MDP3 components
dts: arm64: mt8183: add Mediatek MDP3 nodes
media: platform: mtk-mdp3: add Mediatek MDP3 driver
.../bindings/media/mediatek,mdp3-rdma.yaml | 85 ++
.../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++
.../bindings/media/mediatek,mdp3-wrot.yaml | 70 ++
.../bindings/soc/mediatek/mediatek,ccorr.yaml | 58 +
.../bindings/soc/mediatek/mediatek,wdma.yaml | 71 ++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79 +-
drivers/media/platform/mediatek/Kconfig | 1 +
drivers/media/platform/mediatek/Makefile | 1 +
drivers/media/platform/mediatek/mdp3/Kconfig | 20 +
drivers/media/platform/mediatek/mdp3/Makefile | 6 +
.../platform/mediatek/mdp3/mdp_reg_ccorr.h | 19 +
.../platform/mediatek/mdp3/mdp_reg_rdma.h | 65 ++
.../platform/mediatek/mdp3/mdp_reg_rsz.h | 39 +
.../platform/mediatek/mdp3/mdp_reg_wdma.h | 47 +
.../platform/mediatek/mdp3/mdp_reg_wrot.h | 55 +
.../platform/mediatek/mdp3/mtk-img-ipi.h | 290 +++++
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 486 +++++++++
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.h | 48 +
.../platform/mediatek/mdp3/mtk-mdp3-comp.c | 987 ++++++++++++++++++
.../platform/mediatek/mdp3/mtk-mdp3-comp.h | 185 ++++
.../platform/mediatek/mdp3/mtk-mdp3-core.c | 379 +++++++
.../platform/mediatek/mdp3/mtk-mdp3-core.h | 95 ++
.../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 772 ++++++++++++++
.../platform/mediatek/mdp3/mtk-mdp3-m2m.h | 48 +
.../platform/mediatek/mdp3/mtk-mdp3-regs.c | 736 +++++++++++++
.../platform/mediatek/mdp3/mtk-mdp3-regs.h | 370 +++++++
.../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 312 ++++++
.../platform/mediatek/mdp3/mtk-mdp3-vpu.h | 78 ++
28 files changed, 5466 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
create mode 100644 drivers/media/platform/mediatek/mdp3/Kconfig
create mode 100644 drivers/media/platform/mediatek/mdp3/Makefile
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_ccorr.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_wdma.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c
create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h
--
2.18.0
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v15 1/3] dt-binding: mediatek: add bindings for MediaTek MDP3 components
2022-05-12 9:23 [PATCH v15 0/3] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
@ 2022-05-12 9:23 ` Moudy Ho
2022-05-17 17:53 ` Rob Herring
2022-05-18 10:09 ` Hans Verkuil
2022-05-12 9:23 ` [PATCH v15 2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes Moudy Ho
[not found] ` <20220512092306.6895-4-moudy.ho@mediatek.com>
2 siblings, 2 replies; 9+ messages in thread
From: Moudy Ho @ 2022-05-12 9:23 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Krzysztof Kozlowski, Hans Verkuil
Cc: Chun-Kuang Hu, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
Benjamin Gaignard, AngeloGioacchino Del Regno, daoyuan huang,
Ping-Hsun Wu, allen-kh.cheng, xiandong.wang, randy.wu, moudy.ho,
jason-jh.lin, roy-cw.yeh, river.cheng,
Project_Global_Chrome_Upstream_Group, cellopoint.kai
This patch adds DT binding documents for Media Data Path 3 (MDP3)
a unit in multimedia system combined with several components and
used for scaling and color format convert.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
.../bindings/media/mediatek,mdp3-rdma.yaml | 85 +++++++++++++++++++
.../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++++++++++
.../bindings/media/mediatek,mdp3-wrot.yaml | 70 +++++++++++++++
.../bindings/soc/mediatek/mediatek,ccorr.yaml | 58 +++++++++++++
.../bindings/soc/mediatek/mediatek,wdma.yaml | 71 ++++++++++++++++
5 files changed, 349 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
new file mode 100644
index 000000000000..4fe704e476dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Read Direct Memory Access
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+
+description: |
+ Mediatek Read Direct Memory Access(RDMA) component used to do read DMA.
+ It contains one line buffer to store the sufficient pixel data, and
+ must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+ for details.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8183-mdp3-rdma
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property. Each GCE subsys id is mapping to
+ a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: RDMA clock
+ - description: RSZ clock
+
+ iommus:
+ maxItems: 1
+
+ mboxes:
+ items:
+ - description: used for 1st data pipe from RDMA
+ - description: used for 2nd data pipe from RDMA
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - power-domains
+ - clocks
+ - iommus
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_rdma0: mdp3-rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp3-rdma";
+ reg = <0x14001000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>;
+ iommus = <&iommu>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
new file mode 100644
index 000000000000..7b566fbec3c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Resizer
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to do frame resizing.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-rsz
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property. Each GCE subsys id is mapping to
+ a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ mdp3_rsz0: mdp3-rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ reg = <0x14003000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp3_rsz1: mdp3-rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ reg = <0x14004000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
new file mode 100644
index 000000000000..5481d4e43315
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Write DMA with Rotation
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-wrot
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property. Each GCE subsys id is mapping to
+ a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_wrot0: mdp3-wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ reg = <0x14005000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu>;
+ };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
new file mode 100644
index 000000000000..20d02cb4ad0a
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek color correction
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+
+description: |
+ Mediatek color correction with 3X3 matrix.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-ccorr
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property. Each GCE subsys id is mapping to
+ a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ mdp3_ccorr: mdp3-ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp3-ccorr";
+ reg = <0x1401c000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
+ };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
new file mode 100644
index 000000000000..102d9e163139
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Write Direct Memory Access
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+
+description: |
+ Mediatek Write Direct Memory Access(WDMA) component used to write
+ the data into DMA.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-wdma
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ description: The register of client driver can be configured by gce with
+ 4 arguments defined in this property. Each GCE subsys id is mapping to
+ a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_wdma: mdp3-wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp3-wdma";
+ reg = <0x14006000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu>;
+ };
--
2.18.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v15 2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes
2022-05-12 9:23 [PATCH v15 0/3] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2022-05-12 9:23 ` [PATCH v15 1/3] dt-binding: mediatek: add bindings for MediaTek MDP3 components Moudy Ho
@ 2022-05-12 9:23 ` Moudy Ho
[not found] ` <20220512092306.6895-4-moudy.ho@mediatek.com>
2 siblings, 0 replies; 9+ messages in thread
From: Moudy Ho @ 2022-05-12 9:23 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Krzysztof Kozlowski, Hans Verkuil
Cc: Chun-Kuang Hu, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
Benjamin Gaignard, AngeloGioacchino Del Regno, daoyuan huang,
Ping-Hsun Wu, allen-kh.cheng, xiandong.wang, randy.wu, moudy.ho,
jason-jh.lin, roy-cw.yeh, river.cheng,
Project_Global_Chrome_Upstream_Group, cellopoint.kai
Add device nodes for Media Data Path 3 (MDP3) modules.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79 +++++++++++++++++++++++-
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index fc6ac2a46324..5b6c18f51787 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1389,6 +1389,50 @@
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
+ mdp3_rdma0: mdp3-rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp3-rdma";
+ reg = <0 0x14001000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
+ };
+
+ mdp3_rsz0: mdp3-rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp3_rsz1: mdp3-rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
+
+ mdp3_wrot0: mdp3-wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14005000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ };
+
+ mdp3_wdma: mdp3-wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp3-wdma";
+ reg = <0 0x14006000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+ };
+
ovl0: ovl@14008000 {
compatible = "mediatek,mt8183-disp-ovl";
reg = <0 0x14008000 0 0x1000>;
@@ -1513,7 +1557,33 @@
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
- <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
+ <CMDQ_EVENT_MUTEX_STREAM_DONE1>,
+ <CMDQ_EVENT_MDP_RDMA0_SOF>,
+ <CMDQ_EVENT_MDP_RDMA0_EOF>,
+ <CMDQ_EVENT_MDP_RSZ0_SOF>,
+ <CMDQ_EVENT_MDP_RSZ1_SOF>,
+ <CMDQ_EVENT_MDP_TDSHP_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_EOF>,
+ <CMDQ_EVENT_MDP_WDMA0_SOF>,
+ <CMDQ_EVENT_MDP_WDMA0_EOF>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+ <CMDQ_EVENT_WPE_A_DONE>,
+ <CMDQ_EVENT_SPE_B_DONE>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
};
@@ -1538,6 +1608,13 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
};
+ mdp3_ccorr: mdp3-ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp3-ccorr";
+ reg = <0 0x1401c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
+ };
+
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
--
2.18.0
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v15 3/3] media: platform: mtk-mdp3: add Mediatek MDP3 driver
[not found] ` <20220512092306.6895-4-moudy.ho@mediatek.com>
@ 2022-05-17 11:24 ` Rex-BC Chen
2022-05-19 3:07 ` moudy.ho
0 siblings, 1 reply; 9+ messages in thread
From: Rex-BC Chen @ 2022-05-17 11:24 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Krzysztof Kozlowski, Hans Verkuil
Cc: Chun-Kuang Hu, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
Benjamin Gaignard, AngeloGioacchino Del Regno, daoyuan huang,
Ping-Hsun Wu, allen-kh.cheng, xiandong.wang, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng,
Project_Global_Chrome_Upstream_Group, cellopoint.kai
On Thu, 2022-05-12 at 17:23 +0800, Moudy Ho wrote:
> This patch adds driver for Mediatek's Media Data Path ver.3 (MDP3).
> It provides the following functions:
> color transform, format conversion, resize, crop, rotate, flip
> and additional image quality enhancement.
>
> The MDP3 driver is mainly used for Google Chromebook products to
> import the new architecture to set the HW settings as shown below:
> User -> V4L2 framework
> -> MDP3 driver -> SCP (setting calculations)
> -> MDP3 driver -> CMDQ (GCE driver) -> HW
>
> Each modules' related operation control is sited in mtk-mdp3-comp.c
> Each modules' register table is defined in file with "mdp_reg_"
> prefix
> GCE related API, operation control sited in mtk-mdp3-cmdq.c
> V4L2 m2m device functions are implemented in mtk-mdp3-m2m.c
> Probe, power, suspend/resume, system level functions are defined in
> mtk-mdp3-core.c
>
> v4l2-compliance 1.22.1, 32 bits, 32-bit time_t
>
> Compliance test for mtk-mdp3 device /dev/video2:
>
> Driver Info:
> Driver name : mtk-mdp3
> Card type : 14001000.mdp3-rdma0
> Bus info : platform:mtk-mdp3
> Driver version : 5.18.0
> Capabilities : 0x84204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Device Capabilities
> Device Caps : 0x04204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
>
> Required ioctls:
> test VIDIOC_QUERYCAP: OK
> test invalid ioctls: OK
>
> Allow for multiple opens:
> test second /dev/video2 open: OK
> test VIDIOC_QUERYCAP: OK
> test VIDIOC_G/S_PRIORITY: OK
> test for unlimited opens: OK
>
> Debug ioctls:
> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> test VIDIOC_ENUMAUDIO: OK (Not Supported)
> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDIO: OK (Not Supported)
> Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> test VIDIOC_QUERYCTRL: OK
> test VIDIOC_G/S_CTRL: OK
> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> Standard Controls: 4 Private Controls: 0
>
> Format ioctls:
> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> test VIDIOC_G/S_PARM: OK (Not Supported)
> test VIDIOC_G_FBUF: OK (Not Supported)
> test VIDIOC_G_FMT: OK
> test VIDIOC_TRY_FMT: OK
> test VIDIOC_S_FMT: OK
> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> test Cropping: OK
> test Composing: OK
> test Scaling: OK
>
> Codec ioctls:
> test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
>
> Buffer ioctls:
> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> test VIDIOC_EXPBUF: OK
> test Requests: OK (Not Supported)
> test TIME32/64: OK
>
> Test input 0:
>
> Streaming ioctls:
> test read/write: OK (Not Supported)
> test blocking wait: OK
>
> Video Output Multiplanar: Frame #002
> Video Output Multiplanar: Frame #003
> Video Output Multiplanar: Frame #004
> Video Output Multiplanar: Frame #005
> Video Output Multiplanar: Frame #006
> Video Output Multiplanar: Frame #007
> Video Output Multiplanar: Frame #008
> Video Output Multiplanar: Frame #009
> Video Output Multiplanar: Frame #010
> Video Output Multiplanar: Frame #011
> Video Output Multiplanar: Frame #012
> Video Output Multiplanar: Frame #013
> Video Output Multiplanar: Frame #014
> Video Output Multiplanar: Frame #015
> Video Output Multiplanar: Frame #016
> Video Output Multiplanar: Frame #017
> Video Output Multiplanar: Frame #018
> Video Output Multiplanar: Frame #019
> Video Output Multiplanar: Frame #020
> Video Output Multiplanar: Frame #021
> Video Output Multiplanar: Frame #022
> Video Output Multiplanar: Frame #023
> Video Output Multiplanar: Frame #024
> Video Output Multiplanar: Frame #025
> Video Output Multiplanar: Frame #026
> Video Output Multiplanar: Frame #027
> Video Output Multiplanar: Frame #028
> Video Output Multiplanar: Frame #029
> Video Output Multiplanar: Frame #030
> Video Output Multiplanar: Frame #031
> Video Output Multiplanar: Frame #032
> Video Output Multiplanar: Frame #033
> Video Output Multiplanar: Frame #034
> Video Output Multiplanar: Frame #035
> Video Output Multiplanar: Frame #036
> Video Output Multiplanar: Frame #037
> Video Output Multiplanar: Frame #038
> Video Output Multiplanar: Frame #039
> Video Output Multiplanar: Frame #040
> Video Output Multiplanar: Frame #041
> Video Output Multiplanar: Frame #042
> Video Output Multiplanar: Frame #043
> Video Output Multiplanar: Frame #044
> Video Output Multiplanar: Frame #045
> Video Output Multiplanar: Frame #046
> Video Output Multiplanar: Frame #047
> Video Output Multiplanar: Frame #048
> Video Output Multiplanar: Frame #049
> Video Output Multiplanar: Frame #050
> Video Output Multiplanar: Frame #051
> Video Output Multiplanar: Frame #052
> Video Output Multiplanar: Frame #053
> Video Output Multiplanar: Frame #054
> Video Output Multiplanar: Frame #055
> Video Output Multiplanar: Frame #056
> Video Output Multiplanar: Frame #057
> Video Output Multiplanar: Frame #058
> Video Output Multiplanar: Frame #059
>
> Video Capture Multiplanar: Captured 58 buffers
> test MMAP (no poll): OK
>
> Video Output Multiplanar: Frame #002 (select)
> Video Output Multiplanar: Frame #003 (select)
> Video Output Multiplanar: Frame #004 (select)
> Video Output Multiplanar: Frame #005 (select)
> Video Output Multiplanar: Frame #006 (select)
> Video Output Multiplanar: Frame #007 (select)
> Video Output Multiplanar: Frame #008 (select)
> Video Output Multiplanar: Frame #009 (select)
> Video Output Multiplanar: Frame #010 (select)
> Video Output Multiplanar: Frame #011 (select)
> Video Output Multiplanar: Frame #012 (select)
> Video Output Multiplanar: Frame #013 (select)
> Video Output Multiplanar: Frame #014 (select)
> Video Output Multiplanar: Frame #015 (select)
> Video Output Multiplanar: Frame #016 (select)
> Video Output Multiplanar: Frame #017 (select)
> Video Output Multiplanar: Frame #018 (select)
> Video Output Multiplanar: Frame #019 (select)
> Video Output Multiplanar: Frame #020 (select)
> Video Output Multiplanar: Frame #021 (select)
> Video Output Multiplanar: Frame #022 (select)
> Video Output Multiplanar: Frame #023 (select)
> Video Output Multiplanar: Frame #024 (select)
> Video Output Multiplanar: Frame #025 (select)
> Video Output Multiplanar: Frame #026 (select)
> Video Output Multiplanar: Frame #027 (select)
> Video Output Multiplanar: Frame #028 (select)
> Video Output Multiplanar: Frame #029 (select)
> Video Output Multiplanar: Frame #030 (select)
> Video Output Multiplanar: Frame #031 (select)
> Video Output Multiplanar: Frame #032 (select)
> Video Output Multiplanar: Frame #033 (select)
> Video Output Multiplanar: Frame #034 (select)
> Video Output Multiplanar: Frame #035 (select)
> Video Output Multiplanar: Frame #036 (select)
> Video Output Multiplanar: Frame #037 (select)
> Video Output Multiplanar: Frame #038 (select)
> Video Output Multiplanar: Frame #039 (select)
> Video Output Multiplanar: Frame #040 (select)
> Video Output Multiplanar: Frame #041 (select)
> Video Output Multiplanar: Frame #042 (select)
> Video Output Multiplanar: Frame #043 (select)
> Video Output Multiplanar: Frame #044 (select)
> Video Output Multiplanar: Frame #045 (select)
> Video Output Multiplanar: Frame #046 (select)
> Video Output Multiplanar: Frame #047 (select)
> Video Output Multiplanar: Frame #048 (select)
> Video Output Multiplanar: Frame #049 (select)
> Video Output Multiplanar: Frame #050 (select)
> Video Output Multiplanar: Frame #051 (select)
> Video Output Multiplanar: Frame #052 (select)
> Video Output Multiplanar: Frame #053 (select)
> Video Output Multiplanar: Frame #054 (select)
> Video Output Multiplanar: Frame #055 (select)
> Video Output Multiplanar: Frame #056 (select)
> Video Output Multiplanar: Frame #057 (select)
> Video Output Multiplanar: Frame #058 (select)
> Video Output Multiplanar: Frame #059 (select)
>
> Video Capture Multiplanar: Captured 58 buffers
> test MMAP (select): OK
>
> Video Output Multiplanar: Frame #002 (epoll)
> Video Output Multiplanar: Frame #003 (epoll)
> Video Output Multiplanar: Frame #004 (epoll)
> Video Output Multiplanar: Frame #005 (epoll)
> Video Output Multiplanar: Frame #006 (epoll)
> Video Output Multiplanar: Frame #007 (epoll)
> Video Output Multiplanar: Frame #008 (epoll)
> Video Output Multiplanar: Frame #009 (epoll)
> Video Output Multiplanar: Frame #010 (epoll)
> Video Output Multiplanar: Frame #011 (epoll)
> Video Output Multiplanar: Frame #012 (epoll)
> Video Output Multiplanar: Frame #013 (epoll)
> Video Output Multiplanar: Frame #014 (epoll)
> Video Output Multiplanar: Frame #015 (epoll)
> Video Output Multiplanar: Frame #016 (epoll)
> Video Output Multiplanar: Frame #017 (epoll)
> Video Output Multiplanar: Frame #018 (epoll)
> Video Output Multiplanar: Frame #019 (epoll)
> Video Output Multiplanar: Frame #020 (epoll)
> Video Output Multiplanar: Frame #021 (epoll)
> Video Output Multiplanar: Frame #022 (epoll)
> Video Output Multiplanar: Frame #023 (epoll)
> Video Output Multiplanar: Frame #024 (epoll)
> Video Output Multiplanar: Frame #025 (epoll)
> Video Output Multiplanar: Frame #026 (epoll)
> Video Output Multiplanar: Frame #027 (epoll)
> Video Output Multiplanar: Frame #028 (epoll)
> Video Output Multiplanar: Frame #029 (epoll)
> Video Output Multiplanar: Frame #030 (epoll)
> Video Output Multiplanar: Frame #031 (epoll)
> Video Output Multiplanar: Frame #032 (epoll)
> Video Output Multiplanar: Frame #033 (epoll)
> Video Output Multiplanar: Frame #034 (epoll)
> Video Output Multiplanar: Frame #035 (epoll)
> Video Output Multiplanar: Frame #036 (epoll)
> Video Output Multiplanar: Frame #037 (epoll)
> Video Output Multiplanar: Frame #038 (epoll)
> Video Output Multiplanar: Frame #039 (epoll)
> Video Output Multiplanar: Frame #040 (epoll)
> Video Output Multiplanar: Frame #041 (epoll)
> Video Output Multiplanar: Frame #042 (epoll)
> Video Output Multiplanar: Frame #043 (epoll)
> Video Output Multiplanar: Frame #044 (epoll)
> Video Output Multiplanar: Frame #045 (epoll)
> Video Output Multiplanar: Frame #046 (epoll)
> Video Output Multiplanar: Frame #047 (epoll)
> Video Output Multiplanar: Frame #048 (epoll)
> Video Output Multiplanar: Frame #049 (epoll)
> Video Output Multiplanar: Frame #050 (epoll)
> Video Output Multiplanar: Frame #051 (epoll)
> Video Output Multiplanar: Frame #052 (epoll)
> Video Output Multiplanar: Frame #053 (epoll)
> Video Output Multiplanar: Frame #054 (epoll)
> Video Output Multiplanar: Frame #055 (epoll)
> Video Output Multiplanar: Frame #056 (epoll)
> Video Output Multiplanar: Frame #057 (epoll)
> Video Output Multiplanar: Frame #058 (epoll)
> Video Output Multiplanar: Frame #059 (epoll)
>
> Video Capture Multiplanar: Captured 58 buffers
> test MMAP (epoll): OK
> test USERPTR (no poll): OK (Not Supported)
> test USERPTR (select): OK (Not Supported)
> test DMABUF: Cannot test, specify --expbuf-device
>
> Total for mtk-mdp3 device /dev/video2: 53, Succeeded: 53, Failed: 0,
> Warnings: 0
>
> Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> drivers/media/platform/mediatek/Kconfig | 1 +
> drivers/media/platform/mediatek/Makefile | 1 +
> drivers/media/platform/mediatek/mdp3/Kconfig | 20 +
> drivers/media/platform/mediatek/mdp3/Makefile | 6 +
> .../platform/mediatek/mdp3/mdp_reg_ccorr.h | 19 +
> .../platform/mediatek/mdp3/mdp_reg_rdma.h | 65 ++
> .../platform/mediatek/mdp3/mdp_reg_rsz.h | 39 +
> .../platform/mediatek/mdp3/mdp_reg_wdma.h | 47 +
> .../platform/mediatek/mdp3/mdp_reg_wrot.h | 55 +
> .../platform/mediatek/mdp3/mtk-img-ipi.h | 290 +++++
> .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 486 +++++++++
> .../platform/mediatek/mdp3/mtk-mdp3-cmdq.h | 48 +
> .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 987
> ++++++++++++++++++
> .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 185 ++++
> .../platform/mediatek/mdp3/mtk-mdp3-core.c | 379 +++++++
> .../platform/mediatek/mdp3/mtk-mdp3-core.h | 95 ++
> .../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 772 ++++++++++++++
> .../platform/mediatek/mdp3/mtk-mdp3-m2m.h | 48 +
> .../platform/mediatek/mdp3/mtk-mdp3-regs.c | 736 +++++++++++++
> .../platform/mediatek/mdp3/mtk-mdp3-regs.h | 370 +++++++
> .../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 312 ++++++
> .../platform/mediatek/mdp3/mtk-mdp3-vpu.h | 78 ++
> 22 files changed, 5039 insertions(+)
> create mode 100644 drivers/media/platform/mediatek/mdp3/Kconfig
> create mode 100644 drivers/media/platform/mediatek/mdp3/Makefile
> create mode 100644
> drivers/media/platform/mediatek/mdp3/mdp_reg_ccorr.h
> create mode 100644
> drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h
> create mode 100644
> drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h
> create mode 100644
> drivers/media/platform/mediatek/mdp3/mdp_reg_wdma.h
> create mode 100644
> drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-img-
> ipi.h
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> cmdq.c
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> cmdq.h
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> comp.c
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> comp.h
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> core.c
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> core.h
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> m2m.c
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> m2m.h
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> regs.c
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> regs.h
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> vpu.c
> create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> vpu.h
>
> diff --git a/drivers/media/platform/mediatek/Kconfig
> b/drivers/media/platform/mediatek/Kconfig
> index af47d9888552..84104e2cd024 100644
> --- a/drivers/media/platform/mediatek/Kconfig
> +++ b/drivers/media/platform/mediatek/Kconfig
> @@ -6,3 +6,4 @@ source "drivers/media/platform/mediatek/jpeg/Kconfig"
> source "drivers/media/platform/mediatek/mdp/Kconfig"
> source "drivers/media/platform/mediatek/vcodec/Kconfig"
> source "drivers/media/platform/mediatek/vpu/Kconfig"
> +source "drivers/media/platform/mediatek/mdp3/Kconfig"
> diff --git a/drivers/media/platform/mediatek/Makefile
> b/drivers/media/platform/mediatek/Makefile
> index d3850a13f128..38e6ba917fe5 100644
> --- a/drivers/media/platform/mediatek/Makefile
> +++ b/drivers/media/platform/mediatek/Makefile
> @@ -3,3 +3,4 @@ obj-y += jpeg/
> obj-y += mdp/
> obj-y += vcodec/
> obj-y += vpu/
> +obj-y += mdp3/
> diff --git a/drivers/media/platform/mediatek/mdp3/Kconfig
> b/drivers/media/platform/mediatek/mdp3/Kconfig
> new file mode 100644
> index 000000000000..6640763c7c5e
> --- /dev/null
> +++ b/drivers/media/platform/mediatek/mdp3/Kconfig
> @@ -0,0 +1,20 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +config VIDEO_MEDIATEK_MDP3
> + tristate "Mediatek MDP v3 driver"
> + depends on MTK_IOMMU || COMPLIE_TEST
> + depends on VIDEO_DEV
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on MTK_MMSYS
> + depends on HAS_DMA
> + select VIDEOBUF2_DMA_CONTIG
> + select V4L2_MEM2MEM_DEV
> + select VIDEO_MEDIATEK_VPU
> + select MTK_CMDQ
> + select MTK_SCP
> + default n
> + help
> + It is a v4l2 driver and present in Mediatek MT8183 SoC.
> + The driver supports for scaling and color space conversion.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called mtk-mdp3.
> diff --git a/drivers/media/platform/mediatek/mdp3/Makefile
> b/drivers/media/platform/mediatek/mdp3/Makefile
> new file mode 100644
> index 000000000000..8772f5ac2867
> --- /dev/null
> +++ b/drivers/media/platform/mediatek/mdp3/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +mtk-mdp3-y += mtk-mdp3-core.o mtk-mdp3-vpu.o mtk-mdp3-regs.o
> +mtk-mdp3-y += mtk-mdp3-m2m.o
> +mtk-mdp3-y += mtk-mdp3-comp.o mtk-mdp3-cmdq.o
> +
> +obj-$(CONFIG_VIDEO_MEDIATEK_MDP3) += mtk-mdp3.o
> \ No newline at end of file
Hello Moudy,
I think you should fix "\ No newline at end of file".
BRs,
Rex
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v15 1/3] dt-binding: mediatek: add bindings for MediaTek MDP3 components
2022-05-12 9:23 ` [PATCH v15 1/3] dt-binding: mediatek: add bindings for MediaTek MDP3 components Moudy Ho
@ 2022-05-17 17:53 ` Rob Herring
2022-05-18 10:09 ` Hans Verkuil
1 sibling, 0 replies; 9+ messages in thread
From: Rob Herring @ 2022-05-17 17:53 UTC (permalink / raw)
To: Moudy Ho
Cc: drinkcat, AngeloGioacchino Del Regno, cellopoint.kai,
Hans Verkuil, Rob Landley, Laurent Pinchart, randy.wu,
xiandong.wang, linux-media, linux-mediatek,
Project_Global_Chrome_Upstream_Group, linux-arm-kernel,
Ping-Hsun Wu, Mauro Carvalho Chehab, Matthias Brugger,
Krzysztof Kozlowski, linux-kernel, Alexandre Courbot,
Rob Herring, allen-kh.cheng, daoyuan huang, pihsun, hsinyi,
jason-jh.lin, Benjamin Gaignard, river.cheng, roy-cw.yeh, tfiga,
devicetree, Chun-Kuang Hu
On Thu, 12 May 2022 17:23:04 +0800, Moudy Ho wrote:
> This patch adds DT binding documents for Media Data Path 3 (MDP3)
> a unit in multimedia system combined with several components and
> used for scaling and color format convert.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> .../bindings/media/mediatek,mdp3-rdma.yaml | 85 +++++++++++++++++++
> .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++++++++++
> .../bindings/media/mediatek,mdp3-wrot.yaml | 70 +++++++++++++++
> .../bindings/soc/mediatek/mediatek,ccorr.yaml | 58 +++++++++++++
> .../bindings/soc/mediatek/mediatek,wdma.yaml | 71 ++++++++++++++++
> 5 files changed, 349 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
> create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v15 1/3] dt-binding: mediatek: add bindings for MediaTek MDP3 components
2022-05-12 9:23 ` [PATCH v15 1/3] dt-binding: mediatek: add bindings for MediaTek MDP3 components Moudy Ho
2022-05-17 17:53 ` Rob Herring
@ 2022-05-18 10:09 ` Hans Verkuil
2022-05-19 2:46 ` moudy.ho
2022-05-19 5:34 ` Rex-BC Chen
1 sibling, 2 replies; 9+ messages in thread
From: Hans Verkuil @ 2022-05-18 10:09 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Krzysztof Kozlowski
Cc: Chun-Kuang Hu, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
Benjamin Gaignard, AngeloGioacchino Del Regno, daoyuan huang,
Ping-Hsun Wu, allen-kh.cheng, xiandong.wang, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng,
Project_Global_Chrome_Upstream_Group, cellopoint.kai
Hi Moudy,
On 5/12/22 11:23, Moudy Ho wrote:
> This patch adds DT binding documents for Media Data Path 3 (MDP3)
> a unit in multimedia system combined with several components and
> used for scaling and color format convert.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> .../bindings/media/mediatek,mdp3-rdma.yaml | 85 +++++++++++++++++++
> .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++++++++++
> .../bindings/media/mediatek,mdp3-wrot.yaml | 70 +++++++++++++++
> .../bindings/soc/mediatek/mediatek,ccorr.yaml | 58 +++++++++++++
> .../bindings/soc/mediatek/mediatek,wdma.yaml | 71 ++++++++++++++++
This changes bindings in two subsystems in a single patch. I would recommend splitting
this up. Besides, the subject specifically says "MDP3 components", so having other
components in this patch is confusing.
The soc bindings can either go through the soc subsystem or through the media
subsystem, but then I need Acked-by from the maintainer.
> 5 files changed, 349 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
Why is this part of soc/mediatek instead of media? CSC is typically a media operation.
I'm not saying it is wrong, but it's a bit odd. Apologies if this was asked before.
Regards,
Hans
> create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> new file mode 100644
> index 000000000000..4fe704e476dc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Read Direct Memory Access
> +
> +maintainers:
> + - Matthias Brugger <matthias.bgg@gmail.com>
> + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> +
> +description: |
> + Mediatek Read Direct Memory Access(RDMA) component used to do read DMA.
> + It contains one line buffer to store the sufficient pixel data, and
> + must be siblings to the central MMSYS_CONFIG node.
> + For a description of the MMSYS_CONFIG binding, see
> + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> + for details.
> +
> +properties:
> + compatible:
> + items:
> + - const: mediatek,mt8183-mdp3-rdma
> +
> + reg:
> + maxItems: 1
> +
> + mediatek,gce-client-reg:
> + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> + items:
> + items:
> + - description: phandle of GCE
> + - description: GCE subsys id
> + - description: register offset
> + - description: register size
> + description: The register of client driver can be configured by gce with
> + 4 arguments defined in this property. Each GCE subsys id is mapping to
> + a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: RDMA clock
> + - description: RSZ clock
> +
> + iommus:
> + maxItems: 1
> +
> + mboxes:
> + items:
> + - description: used for 1st data pipe from RDMA
> + - description: used for 2nd data pipe from RDMA
> +
> +required:
> + - compatible
> + - reg
> + - mediatek,gce-client-reg
> + - power-domains
> + - clocks
> + - iommus
> + - mboxes
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/gce/mt8183-gce.h>
> + #include <dt-bindings/power/mt8183-power.h>
> + #include <dt-bindings/memory/mt8183-larb-port.h>
> +
> + mdp3_rdma0: mdp3-rdma0@14001000 {
> + compatible = "mediatek,mt8183-mdp3-rdma";
> + reg = <0x14001000 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> + <&mmsys CLK_MM_MDP_RSZ1>;
> + iommus = <&iommu>;
> + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
> + <&gce 21 CMDQ_THR_PRIO_LOWEST>;
> + };
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> new file mode 100644
> index 000000000000..7b566fbec3c0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Resizer
> +
> +maintainers:
> + - Matthias Brugger <matthias.bgg@gmail.com>
> + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> +
> +description: |
> + One of Media Data Path 3 (MDP3) components used to do frame resizing.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8183-mdp3-rsz
> +
> + reg:
> + maxItems: 1
> +
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: phandle of GCE
> + - description: GCE subsys id
> + - description: register offset
> + - description: register size
> + description: The register of client driver can be configured by gce with
> + 4 arguments defined in this property. Each GCE subsys id is mapping to
> + a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +
> + clocks:
> + minItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - mediatek,gce-client-reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/gce/mt8183-gce.h>
> +
> + mdp3_rsz0: mdp3-rsz0@14003000 {
> + compatible = "mediatek,mt8183-mdp3-rsz";
> + reg = <0x14003000 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> + };
> +
> + mdp3_rsz1: mdp3-rsz1@14004000 {
> + compatible = "mediatek,mt8183-mdp3-rsz";
> + reg = <0x14004000 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> + };
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> new file mode 100644
> index 000000000000..5481d4e43315
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Write DMA with Rotation
> +
> +maintainers:
> + - Matthias Brugger <matthias.bgg@gmail.com>
> + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> +
> +description: |
> + One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8183-mdp3-wrot
> +
> + reg:
> + maxItems: 1
> +
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: phandle of GCE
> + - description: GCE subsys id
> + - description: register offset
> + - description: register size
> + description: The register of client driver can be configured by gce with
> + 4 arguments defined in this property. Each GCE subsys id is mapping to
> + a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> +
> + iommus:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - mediatek,gce-client-reg
> + - power-domains
> + - clocks
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/gce/mt8183-gce.h>
> + #include <dt-bindings/power/mt8183-power.h>
> + #include <dt-bindings/memory/mt8183-larb-port.h>
> +
> + mdp3_wrot0: mdp3-wrot0@14005000 {
> + compatible = "mediatek,mt8183-mdp3-wrot";
> + reg = <0x14005000 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_WROT0>;
> + iommus = <&iommu>;
> + };
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
> new file mode 100644
> index 000000000000..20d02cb4ad0a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek color correction
> +
> +maintainers:
> + - Matthias Brugger <matthias.bgg@gmail.com>
> + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> +
> +description: |
> + Mediatek color correction with 3X3 matrix.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8183-mdp3-ccorr
> +
> + reg:
> + maxItems: 1
> +
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: phandle of GCE
> + - description: GCE subsys id
> + - description: register offset
> + - description: register size
> + description: The register of client driver can be configured by gce with
> + 4 arguments defined in this property. Each GCE subsys id is mapping to
> + a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +
> + clocks:
> + minItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - mediatek,gce-client-reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/gce/mt8183-gce.h>
> +
> + mdp3_ccorr: mdp3-ccorr@1401c000 {
> + compatible = "mediatek,mt8183-mdp3-ccorr";
> + reg = <0x1401c000 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_CCORR>;
> + };
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> new file mode 100644
> index 000000000000..102d9e163139
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Write Direct Memory Access
> +
> +maintainers:
> + - Matthias Brugger <matthias.bgg@gmail.com>
> + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> +
> +description: |
> + Mediatek Write Direct Memory Access(WDMA) component used to write
> + the data into DMA.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8183-mdp3-wdma
> +
> + reg:
> + maxItems: 1
> +
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: phandle of GCE
> + - description: GCE subsys id
> + - description: register offset
> + - description: register size
> + description: The register of client driver can be configured by gce with
> + 4 arguments defined in this property. Each GCE subsys id is mapping to
> + a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> +
> + iommus:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - mediatek,gce-client-reg
> + - power-domains
> + - clocks
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/gce/mt8183-gce.h>
> + #include <dt-bindings/power/mt8183-power.h>
> + #include <dt-bindings/memory/mt8183-larb-port.h>
> +
> + mdp3_wdma: mdp3-wdma@14006000 {
> + compatible = "mediatek,mt8183-mdp3-wdma";
> + reg = <0x14006000 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_WDMA0>;
> + iommus = <&iommu>;
> + };
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v15 1/3] dt-binding: mediatek: add bindings for MediaTek MDP3 components
2022-05-18 10:09 ` Hans Verkuil
@ 2022-05-19 2:46 ` moudy.ho
2022-05-19 5:34 ` Rex-BC Chen
1 sibling, 0 replies; 9+ messages in thread
From: moudy.ho @ 2022-05-19 2:46 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Krzysztof Kozlowski
Cc: Chun-Kuang Hu, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
Benjamin Gaignard, AngeloGioacchino Del Regno, daoyuan huang,
Ping-Hsun Wu, allen-kh.cheng, xiandong.wang, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng,
Project_Global_Chrome_Upstream_Group, cellopoint.kai
On Wed, 2022-05-18 at 12:09 +0200, Hans Verkuil wrote:
> Hi Moudy,
>
> On 5/12/22 11:23, Moudy Ho wrote:
> > This patch adds DT binding documents for Media Data Path 3 (MDP3)
> > a unit in multimedia system combined with several components and
> > used for scaling and color format convert.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> > .../bindings/media/mediatek,mdp3-rdma.yaml | 85
> > +++++++++++++++++++
> > .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++++++++++
> > .../bindings/media/mediatek,mdp3-wrot.yaml | 70 +++++++++++++++
> > .../bindings/soc/mediatek/mediatek,ccorr.yaml | 58 +++++++++++++
> > .../bindings/soc/mediatek/mediatek,wdma.yaml | 71
> > ++++++++++++++++
>
> This changes bindings in two subsystems in a single patch. I would
> recommend splitting
> this up. Besides, the subject specifically says "MDP3 components", so
> having other
> components in this patch is confusing.
>
> The soc bindings can either go through the soc subsystem or through
> the media
> subsystem, but then I need Acked-by from the maintainer.
>
Hi Hans,
Thanks for the reminder, I'll split the bindings under ./soc/mediatek
into a separate patch in the next version.
> > 5 files changed, 349 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
>
> Why is this part of soc/mediatek instead of media? CSC is typically a
> media operation.
>
> I'm not saying it is wrong, but it's a bit odd. Apologies if this was
> asked before.
>
> Regards,
>
> Hans
>
The purpose of this path change is to allow Mediatek's MDP and DRM to
share the same binding, and the same concept as the previous patch
listed below:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220315061031.21642-4-moudy.ho@mediatek.com/
The current path is preliminary and subject to review. Please let me
know if there is a proper one.
Thanks,
Moudy
> > create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml
> > new file mode 100644
> > index 000000000000..4fe704e476dc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml
> > @@ -0,0 +1,85 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!2BMJrq6FnnN19TK9p-l5iZFkxsm9ENZEZONTCXHutrDvy_S9WWQG-NOlC0DQWgLt$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2BMJrq6FnnN19TK9p-l5iZFkxsm9ENZEZONTCXHutrDvy_S9WWQG-NOlC3RmmUh_$
> >
> > +
> > +title: Mediatek Read Direct Memory Access
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@gmail.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > +
> > +description: |
> > + Mediatek Read Direct Memory Access(RDMA) component used to do
> > read DMA.
> > + It contains one line buffer to store the sufficient pixel data,
> > and
> > + must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.ya
> > ml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: mediatek,mt8183-mdp3-rdma
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: RDMA clock
> > + - description: RSZ clock
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > + mboxes:
> > + items:
> > + - description: used for 1st data pipe from RDMA
> > + - description: used for 2nd data pipe from RDMA
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - power-domains
> > + - clocks
> > + - iommus
> > + - mboxes
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > + #include <dt-bindings/power/mt8183-power.h>
> > + #include <dt-bindings/memory/mt8183-larb-port.h>
> > +
> > + mdp3_rdma0: mdp3-rdma0@14001000 {
> > + compatible = "mediatek,mt8183-mdp3-rdma";
> > + reg = <0x14001000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000
> > 0x1000>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> > + <&mmsys CLK_MM_MDP_RSZ1>;
> > + iommus = <&iommu>;
> > + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
> > + <&gce 21 CMDQ_THR_PRIO_LOWEST>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rsz.yaml
> > new file mode 100644
> > index 000000000000..7b566fbec3c0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rsz.yaml
> > @@ -0,0 +1,65 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml*__;Iw!!CTRNKA9wMg0ARbw!2BMJrq6FnnN19TK9p-l5iZFkxsm9ENZEZONTCXHutrDvy_S9WWQG-NOlC1zmmmsy$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2BMJrq6FnnN19TK9p-l5iZFkxsm9ENZEZONTCXHutrDvy_S9WWQG-NOlC3RmmUh_$
> >
> > +
> > +title: Mediatek Resizer
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@gmail.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > +
> > +description: |
> > + One of Media Data Path 3 (MDP3) components used to do frame
> > resizing.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-rsz
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + clocks:
> > + minItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > +
> > + mdp3_rsz0: mdp3-rsz0@14003000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
> > + reg = <0x14003000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000
> > 0x1000>;
> > + clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> > + };
> > +
> > + mdp3_rsz1: mdp3-rsz1@14004000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
> > + reg = <0x14004000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000
> > 0x1000>;
> > + clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > wrot.yaml
> > new file mode 100644
> > index 000000000000..5481d4e43315
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > wrot.yaml
> > @@ -0,0 +1,70 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml*__;Iw!!CTRNKA9wMg0ARbw!2BMJrq6FnnN19TK9p-l5iZFkxsm9ENZEZONTCXHutrDvy_S9WWQG-NOlC7pZCdAq$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2BMJrq6FnnN19TK9p-l5iZFkxsm9ENZEZONTCXHutrDvy_S9WWQG-NOlC3RmmUh_$
> >
> > +
> > +title: Mediatek Write DMA with Rotation
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@gmail.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > +
> > +description: |
> > + One of Media Data Path 3 (MDP3) components used to write DMA
> > with frame rotation.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-wrot
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 1
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - power-domains
> > + - clocks
> > + - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > + #include <dt-bindings/power/mt8183-power.h>
> > + #include <dt-bindings/memory/mt8183-larb-port.h>
> > +
> > + mdp3_wrot0: mdp3-wrot0@14005000 {
> > + compatible = "mediatek,mt8183-mdp3-wrot";
> > + reg = <0x14005000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000
> > 0x1000>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_MDP_WROT0>;
> > + iommus = <&iommu>;
> > + };
> > diff --git
> > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam
> > l
> > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam
> > l
> > new file mode 100644
> > index 000000000000..20d02cb4ad0a
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam
> > l
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!2BMJrq6FnnN19TK9p-l5iZFkxsm9ENZEZONTCXHutrDvy_S9WWQG-NOlCzC45GYo$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2BMJrq6FnnN19TK9p-l5iZFkxsm9ENZEZONTCXHutrDvy_S9WWQG-NOlC3RmmUh_$
> >
> > +
> > +title: Mediatek color correction
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@gmail.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > +
> > +description: |
> > + Mediatek color correction with 3X3 matrix.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-ccorr
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + clocks:
> > + minItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > +
> > + mdp3_ccorr: mdp3-ccorr@1401c000 {
> > + compatible = "mediatek,mt8183-mdp3-ccorr";
> > + reg = <0x1401c000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000
> > 0x1000>;
> > + clocks = <&mmsys CLK_MM_MDP_CCORR>;
> > + };
> > diff --git
> > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> > new file mode 100644
> > index 000000000000..102d9e163139
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> > @@ -0,0 +1,71 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!2BMJrq6FnnN19TK9p-l5iZFkxsm9ENZEZONTCXHutrDvy_S9WWQG-NOlCxcXjGAJ$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2BMJrq6FnnN19TK9p-l5iZFkxsm9ENZEZONTCXHutrDvy_S9WWQG-NOlC3RmmUh_$
> >
> > +
> > +title: Mediatek Write Direct Memory Access
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@gmail.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > +
> > +description: |
> > + Mediatek Write Direct Memory Access(WDMA) component used to
> > write
> > + the data into DMA.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-wdma
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 1
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - power-domains
> > + - clocks
> > + - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > + #include <dt-bindings/power/mt8183-power.h>
> > + #include <dt-bindings/memory/mt8183-larb-port.h>
> > +
> > + mdp3_wdma: mdp3-wdma@14006000 {
> > + compatible = "mediatek,mt8183-mdp3-wdma";
> > + reg = <0x14006000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000
> > 0x1000>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_MDP_WDMA0>;
> > + iommus = <&iommu>;
> > + };
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v15 3/3] media: platform: mtk-mdp3: add Mediatek MDP3 driver
2022-05-17 11:24 ` [PATCH v15 3/3] media: platform: mtk-mdp3: add Mediatek MDP3 driver Rex-BC Chen
@ 2022-05-19 3:07 ` moudy.ho
0 siblings, 0 replies; 9+ messages in thread
From: moudy.ho @ 2022-05-19 3:07 UTC (permalink / raw)
To: Rex-BC Chen, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Krzysztof Kozlowski, Hans Verkuil
Cc: Chun-Kuang Hu, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
Benjamin Gaignard, AngeloGioacchino Del Regno, daoyuan huang,
Ping-Hsun Wu, allen-kh.cheng, xiandong.wang, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng,
Project_Global_Chrome_Upstream_Group, cellopoint.kai
On Tue, 2022-05-17 at 19:24 +0800, Rex-BC Chen wrote:
> On Thu, 2022-05-12 at 17:23 +0800, Moudy Ho wrote:
> > This patch adds driver for Mediatek's Media Data Path ver.3 (MDP3).
> > It provides the following functions:
> > color transform, format conversion, resize, crop, rotate, flip
> > and additional image quality enhancement.
> >
> > The MDP3 driver is mainly used for Google Chromebook products to
> > import the new architecture to set the HW settings as shown below:
> > User -> V4L2 framework
> > -> MDP3 driver -> SCP (setting calculations)
> > -> MDP3 driver -> CMDQ (GCE driver) -> HW
> >
> > Each modules' related operation control is sited in mtk-mdp3-comp.c
> > Each modules' register table is defined in file with "mdp_reg_"
> > prefix
> > GCE related API, operation control sited in mtk-mdp3-cmdq.c
> > V4L2 m2m device functions are implemented in mtk-mdp3-m2m.c
> > Probe, power, suspend/resume, system level functions are defined in
> > mtk-mdp3-core.c
> >
> > v4l2-compliance 1.22.1, 32 bits, 32-bit time_t
> >
> > Compliance test for mtk-mdp3 device /dev/video2:
> >
> > Driver Info:
> > Driver name : mtk-mdp3
> > Card type : 14001000.mdp3-rdma0
> > Bus info : platform:mtk-mdp3
> > Driver version : 5.18.0
> > Capabilities : 0x84204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
> > Device Capabilities
> > Device Caps : 0x04204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
> >
> > Required ioctls:
> > test VIDIOC_QUERYCAP: OK
> > test invalid ioctls: OK
> >
> > Allow for multiple opens:
> > test second /dev/video2 open: OK
> > test VIDIOC_QUERYCAP: OK
> > test VIDIOC_G/S_PRIORITY: OK
> > test for unlimited opens: OK
> >
> > Debug ioctls:
> > test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> > test VIDIOC_LOG_STATUS: OK (Not Supported)
> >
> > Input ioctls:
> > test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> > test VIDIOC_ENUMAUDIO: OK (Not Supported)
> > test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDIO: OK (Not Supported)
> > Inputs: 0 Audio Inputs: 0 Tuners: 0
> >
> > Output ioctls:
> > test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> > test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> > Outputs: 0 Audio Outputs: 0 Modulators: 0
> >
> > Input/Output configuration ioctls:
> > test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> > test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> > test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> > test VIDIOC_G/S_EDID: OK (Not Supported)
> >
> > Control ioctls:
> > test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> > test VIDIOC_QUERYCTRL: OK
> > test VIDIOC_G/S_CTRL: OK
> > test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> > test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> > test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> > Standard Controls: 4 Private Controls: 0
> >
> > Format ioctls:
> > test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> > test VIDIOC_G/S_PARM: OK (Not Supported)
> > test VIDIOC_G_FBUF: OK (Not Supported)
> > test VIDIOC_G_FMT: OK
> > test VIDIOC_TRY_FMT: OK
> > test VIDIOC_S_FMT: OK
> > test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> > test Cropping: OK
> > test Composing: OK
> > test Scaling: OK
> >
> > Codec ioctls:
> > test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> > test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> > test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
> >
> > Buffer ioctls:
> > test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> > test VIDIOC_EXPBUF: OK
> > test Requests: OK (Not Supported)
> > test TIME32/64: OK
> >
> > Test input 0:
> >
> > Streaming ioctls:
> > test read/write: OK (Not Supported)
> > test blocking wait: OK
> >
> > Video Output Multiplanar: Frame #002
> > Video Output Multiplanar: Frame #003
> > Video Output Multiplanar: Frame #004
> > Video Output Multiplanar: Frame #005
> > Video Output Multiplanar: Frame #006
> > Video Output Multiplanar: Frame #007
> > Video Output Multiplanar: Frame #008
> > Video Output Multiplanar: Frame #009
> > Video Output Multiplanar: Frame #010
> > Video Output Multiplanar: Frame #011
> > Video Output Multiplanar: Frame #012
> > Video Output Multiplanar: Frame #013
> > Video Output Multiplanar: Frame #014
> > Video Output Multiplanar: Frame #015
> > Video Output Multiplanar: Frame #016
> > Video Output Multiplanar: Frame #017
> > Video Output Multiplanar: Frame #018
> > Video Output Multiplanar: Frame #019
> > Video Output Multiplanar: Frame #020
> > Video Output Multiplanar: Frame #021
> > Video Output Multiplanar: Frame #022
> > Video Output Multiplanar: Frame #023
> > Video Output Multiplanar: Frame #024
> > Video Output Multiplanar: Frame #025
> > Video Output Multiplanar: Frame #026
> > Video Output Multiplanar: Frame #027
> > Video Output Multiplanar: Frame #028
> > Video Output Multiplanar: Frame #029
> > Video Output Multiplanar: Frame #030
> > Video Output Multiplanar: Frame #031
> > Video Output Multiplanar: Frame #032
> > Video Output Multiplanar: Frame #033
> > Video Output Multiplanar: Frame #034
> > Video Output Multiplanar: Frame #035
> > Video Output Multiplanar: Frame #036
> > Video Output Multiplanar: Frame #037
> > Video Output Multiplanar: Frame #038
> > Video Output Multiplanar: Frame #039
> > Video Output Multiplanar: Frame #040
> > Video Output Multiplanar: Frame #041
> > Video Output Multiplanar: Frame #042
> > Video Output Multiplanar: Frame #043
> > Video Output Multiplanar: Frame #044
> > Video Output Multiplanar: Frame #045
> > Video Output Multiplanar: Frame #046
> > Video Output Multiplanar: Frame #047
> > Video Output Multiplanar: Frame #048
> > Video Output Multiplanar: Frame #049
> > Video Output Multiplanar: Frame #050
> > Video Output Multiplanar: Frame #051
> > Video Output Multiplanar: Frame #052
> > Video Output Multiplanar: Frame #053
> > Video Output Multiplanar: Frame #054
> > Video Output Multiplanar: Frame #055
> > Video Output Multiplanar: Frame #056
> > Video Output Multiplanar: Frame #057
> > Video Output Multiplanar: Frame #058
> > Video Output Multiplanar: Frame #059
> >
> > Video Capture Multiplanar: Captured 58 buffers
> > test MMAP (no poll): OK
> >
> > Video Output Multiplanar: Frame #002 (select)
> > Video Output Multiplanar: Frame #003 (select)
> > Video Output Multiplanar: Frame #004 (select)
> > Video Output Multiplanar: Frame #005 (select)
> > Video Output Multiplanar: Frame #006 (select)
> > Video Output Multiplanar: Frame #007 (select)
> > Video Output Multiplanar: Frame #008 (select)
> > Video Output Multiplanar: Frame #009 (select)
> > Video Output Multiplanar: Frame #010 (select)
> > Video Output Multiplanar: Frame #011 (select)
> > Video Output Multiplanar: Frame #012 (select)
> > Video Output Multiplanar: Frame #013 (select)
> > Video Output Multiplanar: Frame #014 (select)
> > Video Output Multiplanar: Frame #015 (select)
> > Video Output Multiplanar: Frame #016 (select)
> > Video Output Multiplanar: Frame #017 (select)
> > Video Output Multiplanar: Frame #018 (select)
> > Video Output Multiplanar: Frame #019 (select)
> > Video Output Multiplanar: Frame #020 (select)
> > Video Output Multiplanar: Frame #021 (select)
> > Video Output Multiplanar: Frame #022 (select)
> > Video Output Multiplanar: Frame #023 (select)
> > Video Output Multiplanar: Frame #024 (select)
> > Video Output Multiplanar: Frame #025 (select)
> > Video Output Multiplanar: Frame #026 (select)
> > Video Output Multiplanar: Frame #027 (select)
> > Video Output Multiplanar: Frame #028 (select)
> > Video Output Multiplanar: Frame #029 (select)
> > Video Output Multiplanar: Frame #030 (select)
> > Video Output Multiplanar: Frame #031 (select)
> > Video Output Multiplanar: Frame #032 (select)
> > Video Output Multiplanar: Frame #033 (select)
> > Video Output Multiplanar: Frame #034 (select)
> > Video Output Multiplanar: Frame #035 (select)
> > Video Output Multiplanar: Frame #036 (select)
> > Video Output Multiplanar: Frame #037 (select)
> > Video Output Multiplanar: Frame #038 (select)
> > Video Output Multiplanar: Frame #039 (select)
> > Video Output Multiplanar: Frame #040 (select)
> > Video Output Multiplanar: Frame #041 (select)
> > Video Output Multiplanar: Frame #042 (select)
> > Video Output Multiplanar: Frame #043 (select)
> > Video Output Multiplanar: Frame #044 (select)
> > Video Output Multiplanar: Frame #045 (select)
> > Video Output Multiplanar: Frame #046 (select)
> > Video Output Multiplanar: Frame #047 (select)
> > Video Output Multiplanar: Frame #048 (select)
> > Video Output Multiplanar: Frame #049 (select)
> > Video Output Multiplanar: Frame #050 (select)
> > Video Output Multiplanar: Frame #051 (select)
> > Video Output Multiplanar: Frame #052 (select)
> > Video Output Multiplanar: Frame #053 (select)
> > Video Output Multiplanar: Frame #054 (select)
> > Video Output Multiplanar: Frame #055 (select)
> > Video Output Multiplanar: Frame #056 (select)
> > Video Output Multiplanar: Frame #057 (select)
> > Video Output Multiplanar: Frame #058 (select)
> > Video Output Multiplanar: Frame #059 (select)
> >
> > Video Capture Multiplanar: Captured 58 buffers
> > test MMAP (select): OK
> >
> > Video Output Multiplanar: Frame #002 (epoll)
> > Video Output Multiplanar: Frame #003 (epoll)
> > Video Output Multiplanar: Frame #004 (epoll)
> > Video Output Multiplanar: Frame #005 (epoll)
> > Video Output Multiplanar: Frame #006 (epoll)
> > Video Output Multiplanar: Frame #007 (epoll)
> > Video Output Multiplanar: Frame #008 (epoll)
> > Video Output Multiplanar: Frame #009 (epoll)
> > Video Output Multiplanar: Frame #010 (epoll)
> > Video Output Multiplanar: Frame #011 (epoll)
> > Video Output Multiplanar: Frame #012 (epoll)
> > Video Output Multiplanar: Frame #013 (epoll)
> > Video Output Multiplanar: Frame #014 (epoll)
> > Video Output Multiplanar: Frame #015 (epoll)
> > Video Output Multiplanar: Frame #016 (epoll)
> > Video Output Multiplanar: Frame #017 (epoll)
> > Video Output Multiplanar: Frame #018 (epoll)
> > Video Output Multiplanar: Frame #019 (epoll)
> > Video Output Multiplanar: Frame #020 (epoll)
> > Video Output Multiplanar: Frame #021 (epoll)
> > Video Output Multiplanar: Frame #022 (epoll)
> > Video Output Multiplanar: Frame #023 (epoll)
> > Video Output Multiplanar: Frame #024 (epoll)
> > Video Output Multiplanar: Frame #025 (epoll)
> > Video Output Multiplanar: Frame #026 (epoll)
> > Video Output Multiplanar: Frame #027 (epoll)
> > Video Output Multiplanar: Frame #028 (epoll)
> > Video Output Multiplanar: Frame #029 (epoll)
> > Video Output Multiplanar: Frame #030 (epoll)
> > Video Output Multiplanar: Frame #031 (epoll)
> > Video Output Multiplanar: Frame #032 (epoll)
> > Video Output Multiplanar: Frame #033 (epoll)
> > Video Output Multiplanar: Frame #034 (epoll)
> > Video Output Multiplanar: Frame #035 (epoll)
> > Video Output Multiplanar: Frame #036 (epoll)
> > Video Output Multiplanar: Frame #037 (epoll)
> > Video Output Multiplanar: Frame #038 (epoll)
> > Video Output Multiplanar: Frame #039 (epoll)
> > Video Output Multiplanar: Frame #040 (epoll)
> > Video Output Multiplanar: Frame #041 (epoll)
> > Video Output Multiplanar: Frame #042 (epoll)
> > Video Output Multiplanar: Frame #043 (epoll)
> > Video Output Multiplanar: Frame #044 (epoll)
> > Video Output Multiplanar: Frame #045 (epoll)
> > Video Output Multiplanar: Frame #046 (epoll)
> > Video Output Multiplanar: Frame #047 (epoll)
> > Video Output Multiplanar: Frame #048 (epoll)
> > Video Output Multiplanar: Frame #049 (epoll)
> > Video Output Multiplanar: Frame #050 (epoll)
> > Video Output Multiplanar: Frame #051 (epoll)
> > Video Output Multiplanar: Frame #052 (epoll)
> > Video Output Multiplanar: Frame #053 (epoll)
> > Video Output Multiplanar: Frame #054 (epoll)
> > Video Output Multiplanar: Frame #055 (epoll)
> > Video Output Multiplanar: Frame #056 (epoll)
> > Video Output Multiplanar: Frame #057 (epoll)
> > Video Output Multiplanar: Frame #058 (epoll)
> > Video Output Multiplanar: Frame #059 (epoll)
> >
> > Video Capture Multiplanar: Captured 58 buffers
> > test MMAP (epoll): OK
> > test USERPTR (no poll): OK (Not Supported)
> > test USERPTR (select): OK (Not Supported)
> > test DMABUF: Cannot test, specify --expbuf-device
> >
> > Total for mtk-mdp3 device /dev/video2: 53, Succeeded: 53, Failed:
> > 0,
> > Warnings: 0
> >
> > Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> > drivers/media/platform/mediatek/Kconfig | 1 +
> > drivers/media/platform/mediatek/Makefile | 1 +
> > drivers/media/platform/mediatek/mdp3/Kconfig | 20 +
> > drivers/media/platform/mediatek/mdp3/Makefile | 6 +
> > .../platform/mediatek/mdp3/mdp_reg_ccorr.h | 19 +
> > .../platform/mediatek/mdp3/mdp_reg_rdma.h | 65 ++
> > .../platform/mediatek/mdp3/mdp_reg_rsz.h | 39 +
> > .../platform/mediatek/mdp3/mdp_reg_wdma.h | 47 +
> > .../platform/mediatek/mdp3/mdp_reg_wrot.h | 55 +
> > .../platform/mediatek/mdp3/mtk-img-ipi.h | 290 +++++
> > .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 486 +++++++++
> > .../platform/mediatek/mdp3/mtk-mdp3-cmdq.h | 48 +
> > .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 987
> > ++++++++++++++++++
> > .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 185 ++++
> > .../platform/mediatek/mdp3/mtk-mdp3-core.c | 379 +++++++
> > .../platform/mediatek/mdp3/mtk-mdp3-core.h | 95 ++
> > .../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 772 ++++++++++++++
> > .../platform/mediatek/mdp3/mtk-mdp3-m2m.h | 48 +
> > .../platform/mediatek/mdp3/mtk-mdp3-regs.c | 736 +++++++++++++
> > .../platform/mediatek/mdp3/mtk-mdp3-regs.h | 370 +++++++
> > .../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 312 ++++++
> > .../platform/mediatek/mdp3/mtk-mdp3-vpu.h | 78 ++
> > 22 files changed, 5039 insertions(+)
> > create mode 100644 drivers/media/platform/mediatek/mdp3/Kconfig
> > create mode 100644 drivers/media/platform/mediatek/mdp3/Makefile
> > create mode 100644
> > drivers/media/platform/mediatek/mdp3/mdp_reg_ccorr.h
> > create mode 100644
> > drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h
> > create mode 100644
> > drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h
> > create mode 100644
> > drivers/media/platform/mediatek/mdp3/mdp_reg_wdma.h
> > create mode 100644
> > drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-img-
> > ipi.h
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > cmdq.c
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > cmdq.h
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > comp.c
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > comp.h
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > core.c
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > core.h
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > m2m.c
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > m2m.h
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > regs.c
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > regs.h
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > vpu.c
> > create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-
> > vpu.h
> >
> > diff --git a/drivers/media/platform/mediatek/Kconfig
> > b/drivers/media/platform/mediatek/Kconfig
> > index af47d9888552..84104e2cd024 100644
> > --- a/drivers/media/platform/mediatek/Kconfig
> > +++ b/drivers/media/platform/mediatek/Kconfig
> > @@ -6,3 +6,4 @@ source
> > "drivers/media/platform/mediatek/jpeg/Kconfig"
> > source "drivers/media/platform/mediatek/mdp/Kconfig"
> > source "drivers/media/platform/mediatek/vcodec/Kconfig"
> > source "drivers/media/platform/mediatek/vpu/Kconfig"
> > +source "drivers/media/platform/mediatek/mdp3/Kconfig"
> > diff --git a/drivers/media/platform/mediatek/Makefile
> > b/drivers/media/platform/mediatek/Makefile
> > index d3850a13f128..38e6ba917fe5 100644
> > --- a/drivers/media/platform/mediatek/Makefile
> > +++ b/drivers/media/platform/mediatek/Makefile
> > @@ -3,3 +3,4 @@ obj-y += jpeg/
> > obj-y += mdp/
> > obj-y += vcodec/
> > obj-y += vpu/
> > +obj-y += mdp3/
> > diff --git a/drivers/media/platform/mediatek/mdp3/Kconfig
> > b/drivers/media/platform/mediatek/mdp3/Kconfig
> > new file mode 100644
> > index 000000000000..6640763c7c5e
> > --- /dev/null
> > +++ b/drivers/media/platform/mediatek/mdp3/Kconfig
> > @@ -0,0 +1,20 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +config VIDEO_MEDIATEK_MDP3
> > + tristate "Mediatek MDP v3 driver"
> > + depends on MTK_IOMMU || COMPLIE_TEST
> > + depends on VIDEO_DEV
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
> > + depends on MTK_MMSYS
> > + depends on HAS_DMA
> > + select VIDEOBUF2_DMA_CONTIG
> > + select V4L2_MEM2MEM_DEV
> > + select VIDEO_MEDIATEK_VPU
> > + select MTK_CMDQ
> > + select MTK_SCP
> > + default n
> > + help
> > + It is a v4l2 driver and present in Mediatek MT8183 SoC.
> > + The driver supports for scaling and color space conversion.
> > +
> > + To compile this driver as a module, choose M here: the
> > + module will be called mtk-mdp3.
> > diff --git a/drivers/media/platform/mediatek/mdp3/Makefile
> > b/drivers/media/platform/mediatek/mdp3/Makefile
> > new file mode 100644
> > index 000000000000..8772f5ac2867
> > --- /dev/null
> > +++ b/drivers/media/platform/mediatek/mdp3/Makefile
> > @@ -0,0 +1,6 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +mtk-mdp3-y += mtk-mdp3-core.o mtk-mdp3-vpu.o mtk-mdp3-regs.o
> > +mtk-mdp3-y += mtk-mdp3-m2m.o
> > +mtk-mdp3-y += mtk-mdp3-comp.o mtk-mdp3-cmdq.o
> > +
> > +obj-$(CONFIG_VIDEO_MEDIATEK_MDP3) += mtk-mdp3.o
> > \ No newline at end of file
>
> Hello Moudy,
>
> I think you should fix "\ No newline at end of file".
>
> BRs,
> Rex
>
Hi Rex,
Thanks for the reminder, I'll fix it in the next version.
Regards,
Moudy
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v15 1/3] dt-binding: mediatek: add bindings for MediaTek MDP3 components
2022-05-18 10:09 ` Hans Verkuil
2022-05-19 2:46 ` moudy.ho
@ 2022-05-19 5:34 ` Rex-BC Chen
1 sibling, 0 replies; 9+ messages in thread
From: Rex-BC Chen @ 2022-05-19 5:34 UTC (permalink / raw)
To: Hans Verkuil, Moudy Ho, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Krzysztof Kozlowski
Cc: Chun-Kuang Hu, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
Benjamin Gaignard, AngeloGioacchino Del Regno, daoyuan huang,
Ping-Hsun Wu, allen-kh.cheng, xiandong.wang, randy.wu,
jason-jh.lin, roy-cw.yeh, river.cheng,
Project_Global_Chrome_Upstream_Group, cellopoint.kai
On Wed, 2022-05-18 at 12:09 +0200, Hans Verkuil wrote:
> Hi Moudy,
>
> On 5/12/22 11:23, Moudy Ho wrote:
> > This patch adds DT binding documents for Media Data Path 3 (MDP3)
> > a unit in multimedia system combined with several components and
> > used for scaling and color format convert.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> > .../bindings/media/mediatek,mdp3-rdma.yaml | 85
> > +++++++++++++++++++
> > .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++++++++++
> > .../bindings/media/mediatek,mdp3-wrot.yaml | 70 +++++++++++++++
> > .../bindings/soc/mediatek/mediatek,ccorr.yaml | 58 +++++++++++++
> > .../bindings/soc/mediatek/mediatek,wdma.yaml | 71
> > ++++++++++++++++
>
> This changes bindings in two subsystems in a single patch. I would
> recommend splitting
> this up. Besides, the subject specifically says "MDP3 components", so
> having other
> components in this patch is confusing.
>
> The soc bindings can either go through the soc subsystem or through
> the media
> subsystem, but then I need Acked-by from the maintainer.
>
Hello Hans,
There is something wrong for Moudy's mediatek mail server, so I help
him to reply this mail to prevent the mismatch of discussion between
Moudy and you.
Moudy will split the bindings under ./soc/mediatek
into a separate patch in the next version.
> > 5 files changed, 349 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
>
> Why is this part of soc/mediatek instead of media? CSC is typically a
> media operation.
>
> I'm not saying it is wrong, but it's a bit odd. Apologies if this was
> asked before.
>
> Regards,
>
> Hans
>
The purpose of this path change is to allow Mediatek's MDP and DRM to
share the same binding, and the same concept as the previous patch
listed below:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220315061031.21642-4-moudy.ho@mediatek.com/
The current path is preliminary and subject to review. Please let me
know if there is a proper one.
BRs,
Rex
> > create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml
> > new file mode 100644
> > index 000000000000..4fe704e476dc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml
> > @@ -0,0 +1,85 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uZLfyeWNg$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYTQJNp6g$
> >
> > +
> > +title: Mediatek Read Direct Memory Access
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@gmail.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > +
> > +description: |
> > + Mediatek Read Direct Memory Access(RDMA) component used to do
> > read DMA.
> > + It contains one line buffer to store the sufficient pixel data,
> > and
> > + must be siblings to the central MMSYS_CONFIG node.
> > + For a description of the MMSYS_CONFIG binding, see
> > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.ya
> > ml
> > + for details.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: mediatek,mt8183-mdp3-rdma
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: RDMA clock
> > + - description: RSZ clock
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > + mboxes:
> > + items:
> > + - description: used for 1st data pipe from RDMA
> > + - description: used for 2nd data pipe from RDMA
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - power-domains
> > + - clocks
> > + - iommus
> > + - mboxes
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > + #include <dt-bindings/power/mt8183-power.h>
> > + #include <dt-bindings/memory/mt8183-larb-port.h>
> > +
> > + mdp3_rdma0: mdp3-rdma0@14001000 {
> > + compatible = "mediatek,mt8183-mdp3-rdma";
> > + reg = <0x14001000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000
> > 0x1000>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> > + <&mmsys CLK_MM_MDP_RSZ1>;
> > + iommus = <&iommu>;
> > + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
> > + <&gce 21 CMDQ_THR_PRIO_LOWEST>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rsz.yaml
> > new file mode 100644
> > index 000000000000..7b566fbec3c0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rsz.yaml
> > @@ -0,0 +1,65 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYLnzDDrw$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYTQJNp6g$
> >
> > +
> > +title: Mediatek Resizer
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@gmail.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > +
> > +description: |
> > + One of Media Data Path 3 (MDP3) components used to do frame
> > resizing.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-rsz
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + clocks:
> > + minItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > +
> > + mdp3_rsz0: mdp3-rsz0@14003000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
> > + reg = <0x14003000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000
> > 0x1000>;
> > + clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> > + };
> > +
> > + mdp3_rsz1: mdp3-rsz1@14004000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
> > + reg = <0x14004000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000
> > 0x1000>;
> > + clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > wrot.yaml
> > new file mode 100644
> > index 000000000000..5481d4e43315
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > wrot.yaml
> > @@ -0,0 +1,70 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uY3xwuR8Q$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYTQJNp6g$
> >
> > +
> > +title: Mediatek Write DMA with Rotation
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@gmail.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > +
> > +description: |
> > + One of Media Data Path 3 (MDP3) components used to write DMA
> > with frame rotation.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-wrot
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 1
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - power-domains
> > + - clocks
> > + - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > + #include <dt-bindings/power/mt8183-power.h>
> > + #include <dt-bindings/memory/mt8183-larb-port.h>
> > +
> > + mdp3_wrot0: mdp3-wrot0@14005000 {
> > + compatible = "mediatek,mt8183-mdp3-wrot";
> > + reg = <0x14005000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000
> > 0x1000>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_MDP_WROT0>;
> > + iommus = <&iommu>;
> > + };
> > diff --git
> > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam
> > l
> > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam
> > l
> > new file mode 100644
> > index 000000000000..20d02cb4ad0a
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam
> > l
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1ua8l4S1Sg$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYTQJNp6g$
> >
> > +
> > +title: Mediatek color correction
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@gmail.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > +
> > +description: |
> > + Mediatek color correction with 3X3 matrix.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-ccorr
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + clocks:
> > + minItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > +
> > + mdp3_ccorr: mdp3-ccorr@1401c000 {
> > + compatible = "mediatek,mt8183-mdp3-ccorr";
> > + reg = <0x1401c000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000
> > 0x1000>;
> > + clocks = <&mmsys CLK_MM_MDP_CCORR>;
> > + };
> > diff --git
> > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> > new file mode 100644
> > index 000000000000..102d9e163139
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> > @@ -0,0 +1,71 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uZKK4h1GQ$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYTQJNp6g$
> >
> > +
> > +title: Mediatek Write Direct Memory Access
> > +
> > +maintainers:
> > + - Matthias Brugger <matthias.bgg@gmail.com>
> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> > +
> > +description: |
> > + Mediatek Write Direct Memory Access(WDMA) component used to
> > write
> > + the data into DMA.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-wdma
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + items:
> > + - description: phandle of GCE
> > + - description: GCE subsys id
> > + - description: register offset
> > + - description: register size
> > + description: The register of client driver can be configured
> > by gce with
> > + 4 arguments defined in this property. Each GCE subsys id is
> > mapping to
> > + a client defined in the header include/dt-
> > bindings/gce/<chip>-gce.h.
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 1
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - mediatek,gce-client-reg
> > + - power-domains
> > + - clocks
> > + - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > + #include <dt-bindings/power/mt8183-power.h>
> > + #include <dt-bindings/memory/mt8183-larb-port.h>
> > +
> > + mdp3_wdma: mdp3-wdma@14006000 {
> > + compatible = "mediatek,mt8183-mdp3-wdma";
> > + reg = <0x14006000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000
> > 0x1000>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_MDP_WDMA0>;
> > + iommus = <&iommu>;
> > + };
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Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-12 9:23 [PATCH v15 0/3] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2022-05-12 9:23 ` [PATCH v15 1/3] dt-binding: mediatek: add bindings for MediaTek MDP3 components Moudy Ho
2022-05-17 17:53 ` Rob Herring
2022-05-18 10:09 ` Hans Verkuil
2022-05-19 2:46 ` moudy.ho
2022-05-19 5:34 ` Rex-BC Chen
2022-05-12 9:23 ` [PATCH v15 2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes Moudy Ho
[not found] ` <20220512092306.6895-4-moudy.ho@mediatek.com>
2022-05-17 11:24 ` [PATCH v15 3/3] media: platform: mtk-mdp3: add Mediatek MDP3 driver Rex-BC Chen
2022-05-19 3:07 ` moudy.ho
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