* [V4,0/8] Support multi-hardware jpeg decoder for MT8195
@ 2022-06-27 2:55 Irui Wang
2022-06-27 2:55 ` [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible Irui Wang
` (7 more replies)
0 siblings, 8 replies; 15+ messages in thread
From: Irui Wang @ 2022-06-27 2:55 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Tzung-Bi Shih, angelogioacchino.delregno,
nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
From: kyrie wu <kyrie.wu@mediatek.com>
This series adds support for multi hardware jpeg decoding,
by first adding use of_platform_populate to manage each hardware
information: interrupt, clock, register bases and power.
Secondly add decoding work queue to deal with the decoding requests
of multi-hardware at the same time. Lastly, add output picture
reorder function interface to eliminate the out of order images.
This series has been tested with both MT8195.
Decoding worked for this chip.
Patch 1 Adds jpeg decoder dt-bindings for mt8195
Patches 2 jpeg decoder builds three module for using Multi-HW,
export some functions to make them visible by other modules.
Patch 3 use of_platform_populate to manage multi-hardware.
Patch 4 add jpeg decoding timeout function to judge hardware timeout.
Patch 5 add decoding work queue to deal with multi-hardware decoding
at the same time.
Patch 6 add output picture reorder function to order images.
Patch 7 refactor jpegdec func interface for HW working.
Patch 8 add stop cmd function to deal with EOS operation.
---
This series patches dependent on:
media_stage tree:
[1]
https://git.linuxtv.org/media_stage.git/commit/?id=b3627647f9ea7473d10fb08a95fd7c4133a17ca4
patch1 new jpegdec dt-bindings included files
[2] MM IOMMU binding:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220217113453.13658-2-yong.wu@mediatek.com/
[3] MT8195 power domain:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=580579
Changes compared with v3:
- some modifications for patch v3's review comments.
Changes compared with v2:
- add stop cmd function.
- some modifications for patch v1's review comments.
Changes compared with v1:
- new yaml file for mt8195 jpeg decoder.
- some modifications for patch v1's review comments.
kyrie wu (8):
dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible
media: mtk-jpegdec: export jpeg decoder functions
media: mtk-jpegdec: manage jpegdec multi-hardware
media: mtk-jpegdec: add jpegdec timeout func interface
media: mtk-jpegdec: add jpeg decode worker interface
media: mtk-jpegdec: add output pic reorder interface
media: mtk-jpegdec: refactor jpegdec func interface
mtk-jpegdec: add stop cmd interface for jpgdec
.../media/mediatek,mt8195-jpegdec.yaml | 176 ++++++++++
drivers/media/platform/mediatek/jpeg/Makefile | 5 +-
.../platform/mediatek/jpeg/mtk_jpeg_core.c | 246 +++++++++++++-
.../platform/mediatek/jpeg/mtk_jpeg_core.h | 47 +++
.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 310 ++++++++++++++++--
.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.h | 3 +-
.../platform/mediatek/jpeg/mtk_jpeg_dec_reg.h | 1 +
7 files changed, 754 insertions(+), 34 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible
2022-06-27 2:55 [V4,0/8] Support multi-hardware jpeg decoder for MT8195 Irui Wang
@ 2022-06-27 2:55 ` Irui Wang
2022-07-01 15:29 ` Rob Herring
2022-07-05 13:00 ` AngeloGioacchino Del Regno
2022-06-27 2:55 ` [V4,2/8] media: mtk-jpegdec: export jpeg decoder functions Irui Wang
` (6 subsequent siblings)
7 siblings, 2 replies; 15+ messages in thread
From: Irui Wang @ 2022-06-27 2:55 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Tzung-Bi Shih, angelogioacchino.delregno,
nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
From: kyrie wu <kyrie.wu@mediatek.com>
Add mediatek,mt8195-jpgdec compatible to binding document.
Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
---
.../media/mediatek,mt8195-jpegdec.yaml | 176 ++++++++++++++++++
1 file changed, 176 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
new file mode 100644
index 000000000000..8a255e8e2e09
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek JPEG Encoder Device Tree Bindings
+
+maintainers:
+ - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
+
+description: |-
+ MediaTek JPEG Decoder is the JPEG decode hardware present in MediaTek SoCs
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-jpgdec
+
+ mediatek,jpegdec-multi-core:
+ type: boolean
+ description: |
+ Indicates whether the jpeg encoder has multiple cores or not.
+
+ power-domains:
+ maxItems: 1
+
+ iommus:
+ maxItems: 6
+ description: |
+ Points to the respective IOMMU block with master port as argument, see
+ Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+ Ports are according to the HW.
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+# Required child node:
+patternProperties:
+ "^jpgdec@[0-9a-f]+$":
+ type: object
+ description: |
+ The jpeg decoder hardware device node which should be added as subnodes to
+ the main jpeg node.
+
+ properties:
+ compatible:
+ const: mediatek,mt8195-jpgdec-hw
+
+ reg:
+ maxItems: 1
+
+ hw_id:
+ description: |
+ MT8195 decoding hardware id value. MT8195 has three decoding hardwares,
+ which is represented by this parameter.
+
+ iommus:
+ minItems: 1
+ maxItems: 32
+ description: |
+ List of the hardware port in respective IOMMU block for current Socs.
+ Refer to bindings/iommu/mediatek,iommu.yaml.
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: jpgdec
+
+ power-domains:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - hw_id
+ - iommus
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - power-domains
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/memory/mt8195-memory-port.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/power/mt8195-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ jpgdec_master {
+ compatible = "mediatek,mt8195-jpgdec";
+ mediatek,jpegdec-multi-core;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+ iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
+ <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
+ <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
+ <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
+ <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+ <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ jpgdec@1a040000 {
+ compatible = "mediatek,mt8195-jpgdec-hw";
+ reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
+ hw_id = <0>;
+ iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
+ <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
+ <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
+ <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
+ <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+ <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+ interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vencsys CLK_VENC_JPGDEC>;
+ clock-names = "jpgdec";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+ };
+
+ jpgdec@1a050000 {
+ compatible = "mediatek,mt8195-jpgdec-hw";
+ reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
+ hw_id = <1>;
+ iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
+ <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
+ <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
+ <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
+ <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+ <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+ interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
+ clock-names = "jpgdec";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+ };
+
+ jpgdec@1b040000 {
+ compatible = "mediatek,mt8195-jpgdec-hw";
+ reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
+ hw_id = <2>;
+ iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
+ <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
+ <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
+ <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
+ <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
+ <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
+ interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
+ clock-names = "jpgdec";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
+ };
+ };
+ };
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [V4,2/8] media: mtk-jpegdec: export jpeg decoder functions
2022-06-27 2:55 [V4,0/8] Support multi-hardware jpeg decoder for MT8195 Irui Wang
2022-06-27 2:55 ` [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible Irui Wang
@ 2022-06-27 2:55 ` Irui Wang
2022-06-27 2:55 ` [PV4,3/8] media: mtk-jpegdec: manage jpegdec multi-hardware Irui Wang
` (5 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Irui Wang @ 2022-06-27 2:55 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Tzung-Bi Shih, angelogioacchino.delregno,
nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
From: kyrie wu <kyrie.wu@mediatek.com>
mtk jpeg decoder is built as a module, export some functions to make them
visible by other modules.
Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
---
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index 1e3852295f2f..d2f25f43e852 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -189,6 +189,7 @@ int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param)
return 0;
}
+EXPORT_SYMBOL_GPL(mtk_jpeg_dec_fill_param);
u32 mtk_jpeg_dec_get_int_status(void __iomem *base)
{
@@ -200,6 +201,7 @@ u32 mtk_jpeg_dec_get_int_status(void __iomem *base)
return ret;
}
+EXPORT_SYMBOL_GPL(mtk_jpeg_dec_get_int_status);
u32 mtk_jpeg_dec_enum_result(u32 irq_result)
{
@@ -216,11 +218,13 @@ u32 mtk_jpeg_dec_enum_result(u32 irq_result)
return MTK_JPEG_DEC_RESULT_ERROR_UNKNOWN;
}
+EXPORT_SYMBOL_GPL(mtk_jpeg_dec_enum_result);
void mtk_jpeg_dec_start(void __iomem *base)
{
writel(0, base + JPGDEC_REG_TRIG);
}
+EXPORT_SYMBOL_GPL(mtk_jpeg_dec_start);
static void mtk_jpeg_dec_soft_reset(void __iomem *base)
{
@@ -240,6 +244,7 @@ void mtk_jpeg_dec_reset(void __iomem *base)
mtk_jpeg_dec_soft_reset(base);
mtk_jpeg_dec_hard_reset(base);
}
+EXPORT_SYMBOL_GPL(mtk_jpeg_dec_reset);
static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w,
u8 yscale_h, u8 uvscale_w, u8 uvscale_h)
@@ -408,3 +413,4 @@ void mtk_jpeg_dec_set_config(void __iomem *base,
config->dma_last_mcu);
mtk_jpeg_dec_set_pause_mcu_idx(base, config->total_mcu);
}
+EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_config);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PV4,3/8] media: mtk-jpegdec: manage jpegdec multi-hardware
2022-06-27 2:55 [V4,0/8] Support multi-hardware jpeg decoder for MT8195 Irui Wang
2022-06-27 2:55 ` [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible Irui Wang
2022-06-27 2:55 ` [V4,2/8] media: mtk-jpegdec: export jpeg decoder functions Irui Wang
@ 2022-06-27 2:55 ` Irui Wang
2022-07-05 13:36 ` AngeloGioacchino Del Regno
2022-06-27 2:55 ` [V4,4/8] media: mtk-jpegdec: add jpegdec timeout func interface Irui Wang
` (4 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Irui Wang @ 2022-06-27 2:55 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Tzung-Bi Shih, angelogioacchino.delregno,
nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
From: kyrie wu <kyrie.wu@mediatek.com>
manage each hardware information, including irq/clk/power.
the hardware includes HW0/HW1/HW2.
Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
---
drivers/media/platform/mediatek/jpeg/Makefile | 5 +-
.../platform/mediatek/jpeg/mtk_jpeg_core.c | 25 ++-
.../platform/mediatek/jpeg/mtk_jpeg_core.h | 38 ++++
.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 168 ++++++++++++++++++
4 files changed, 232 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/mediatek/jpeg/Makefile b/drivers/media/platform/mediatek/jpeg/Makefile
index 69703db4b0a5..26e84852523e 100644
--- a/drivers/media/platform/mediatek/jpeg/Makefile
+++ b/drivers/media/platform/mediatek/jpeg/Makefile
@@ -1,9 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o \
- mtk-jpeg-enc-hw.o
+ mtk-jpeg-enc-hw.o \
+ mtk-jpeg-dec-hw.o
mtk_jpeg-y := mtk_jpeg_core.o \
- mtk_jpeg_dec_hw.o \
mtk_jpeg_dec_parse.o
mtk-jpeg-enc-hw-y := mtk_jpeg_enc_hw.o
+mtk-jpeg-dec-hw-y := mtk_jpeg_dec_hw.o
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 2696651b457b..5683df94ac6a 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1467,8 +1467,14 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
jpeg->variant = of_device_get_match_data(jpeg->dev);
if (of_property_read_bool(pdev->dev.of_node,
- "mediatek,jpegenc-multi-core")) {
+ "mediatek,jpegenc-multi-core"))
jpeg->is_jpgenc_multihw = true;
+
+ if (of_property_read_bool(pdev->dev.of_node,
+ "mediatek,jpegdec-multi-core"))
+ jpeg->is_jpgdec_multihw = true;
+
+ if (jpeg->is_jpgenc_multihw || jpeg->is_jpgdec_multihw) {
ret = devm_of_platform_populate(&pdev->dev);
if (ret) {
v4l2_err(&jpeg->v4l2_dev, "Master of platform populate failed.");
@@ -1476,7 +1482,7 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
}
}
- if (!jpeg->is_jpgenc_multihw) {
+ if (!jpeg->is_jpgenc_multihw || jpeg->is_jpgdec_multihw) {
INIT_DELAYED_WORK(&jpeg->job_timeout_work,
mtk_jpeg_job_timeout_work);
@@ -1693,6 +1699,17 @@ static const struct mtk_jpeg_variant mtk8195_jpegenc_drvdata = {
.cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
};
+static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = {
+ .formats = mtk_jpeg_dec_formats,
+ .num_formats = MTK_JPEG_DEC_NUM_FORMATS,
+ .qops = &mtk_jpeg_dec_qops,
+ .m2m_ops = &mtk_jpeg_dec_m2m_ops,
+ .dev_name = "mtk-jpeg-dec",
+ .ioctl_ops = &mtk_jpeg_dec_ioctl_ops,
+ .out_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+ .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
+};
+
#if defined(CONFIG_OF)
static const struct of_device_id mtk_jpeg_match[] = {
{
@@ -1711,6 +1728,10 @@ static const struct of_device_id mtk_jpeg_match[] = {
.compatible = "mediatek,mt8195-jpgenc",
.data = &mtk8195_jpegenc_drvdata,
},
+ {
+ .compatible = "mediatek,mt8195-jpgdec",
+ .data = &mtk8195_jpegdec_drvdata,
+ },
{},
};
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index f8415b6b1618..29cd71fd713e 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -102,6 +102,13 @@ enum mtk_jpegenc_hw_id {
MTK_JPEGENC_HW_MAX,
};
+enum mtk_jpegdec_hw_id {
+ MTK_JPEGDEC_HW0,
+ MTK_JPEGDEC_HW1,
+ MTK_JPEGDEC_HW2,
+ MTK_JPEGDEC_HW_MAX,
+};
+
/**
* struct mtk_vcodec_clk - Structure used to store vcodec clock information
*/
@@ -110,6 +117,14 @@ struct mtk_jpegenc_clk {
int clk_num;
};
+/**
+ * struct mtk_vcodec_clk - Structure used to store vcodec clock information
+ */
+struct mtk_jpegdec_clk {
+ struct clk_bulk_data *clks;
+ int clk_num;
+};
+
/**
* struct mtk_jpegenc_comp_dev - JPEG COREX abstraction
* @dev: JPEG device
@@ -139,6 +154,25 @@ struct mtk_jpegenc_comp_dev {
spinlock_t hw_lock;
};
+/**
+ * struct mtk_jpegdec_comp_dev - JPEG COREX abstraction
+ * @dev: JPEG device
+ * @plat_dev: platform device data
+ * @reg_base: JPEG registers mapping
+ * @master_dev: mtk_jpeg_dev device
+ * @jdec_clk: mtk_jpegdec_clk
+ * @jpegdec_irq: jpeg decode irq num
+ */
+struct mtk_jpegdec_comp_dev {
+ struct device *dev;
+ struct platform_device *plat_dev;
+ void __iomem *reg_base;
+ struct mtk_jpeg_dev *master_dev;
+ struct mtk_jpegdec_clk jdec_clk;
+ int jpegdec_irq;
+ int hw_id;
+};
+
/**
* struct mtk_jpeg_dev - JPEG IP abstraction
* @lock: the mutex protecting this structure
@@ -171,6 +205,10 @@ struct mtk_jpeg_dev {
bool is_jpgenc_multihw;
wait_queue_head_t enc_hw_wq;
atomic_t enchw_rdy;
+
+ void __iomem *reg_decbase[MTK_JPEGDEC_HW_MAX];
+ struct mtk_jpegdec_comp_dev *dec_hw_dev[MTK_JPEGDEC_HW_MAX];
+ bool is_jpgdec_multihw;
};
/**
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index d2f25f43e852..fc98fe122874 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -5,9 +5,24 @@
* Rick Chang <rick.chang@mediatek.com>
*/
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <media/media-device.h>
#include <media/videobuf2-core.h>
+#include <media/videobuf2-v4l2.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-fh.h>
+#include <media/v4l2-event.h>
#include "mtk_jpeg_core.h"
#include "mtk_jpeg_dec_hw.h"
@@ -24,6 +39,16 @@ enum mtk_jpeg_color {
MTK_JPEG_COLOR_400 = 0x00110000
};
+#if defined(CONFIG_OF)
+static const struct of_device_id mtk_jpegdec_hw_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-jpgdec-hw",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids);
+#endif
+
static inline int mtk_jpeg_verify_align(u32 val, int align, u32 reg)
{
if (val & (align - 1)) {
@@ -414,3 +439,146 @@ void mtk_jpeg_dec_set_config(void __iomem *base,
mtk_jpeg_dec_set_pause_mcu_idx(base, config->total_mcu);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_config);
+
+static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
+{
+ struct vb2_v4l2_buffer *src_buf, *dst_buf;
+ struct mtk_jpeg_src_buf *jpeg_src_buf;
+ enum vb2_buffer_state buf_state;
+ struct mtk_jpeg_ctx *ctx;
+ u32 dec_irq_ret;
+ u32 irq_status;
+ int i;
+
+ struct mtk_jpegdec_comp_dev *jpeg = priv;
+ struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev;
+
+ irq_status = mtk_jpeg_dec_get_int_status(jpeg->reg_base);
+ dec_irq_ret = mtk_jpeg_dec_enum_result(irq_status);
+ if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
+ mtk_jpeg_dec_reset(jpeg->reg_base);
+ if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE)
+ return IRQ_NONE;
+
+ ctx = v4l2_m2m_get_curr_priv(master_jpeg->m2m_dev);
+ if (!ctx) {
+ dev_err(jpeg->dev, "Context is NULL\n");
+ return IRQ_HANDLED;
+ }
+
+ src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+ dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+ v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
+ jpeg_src_buf =
+ container_of(src_buf, struct mtk_jpeg_src_buf, b);
+
+ for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
+ vb2_set_plane_payload(&dst_buf->vb2_buf, i,
+ jpeg_src_buf->dec_param.comp_size[i]);
+
+ buf_state = VB2_BUF_STATE_DONE;
+
+ v4l2_m2m_buf_done(src_buf, buf_state);
+ v4l2_m2m_buf_done(dst_buf, buf_state);
+ v4l2_m2m_job_finish(master_jpeg->m2m_dev, ctx->fh.m2m_ctx);
+ pm_runtime_put(ctx->jpeg->dev);
+
+ return IRQ_HANDLED;
+}
+
+static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev *dev)
+{
+ struct platform_device *pdev = dev->plat_dev;
+ int ret;
+
+ dev->jpegdec_irq = platform_get_irq(pdev, 0);
+ if (dev->jpegdec_irq < 0) {
+ dev_err(&pdev->dev, "Failed to get irq resource");
+ return dev->jpegdec_irq;
+ }
+
+ ret = devm_request_irq(&pdev->dev,
+ dev->jpegdec_irq,
+ mtk_jpegdec_hw_irq_handler,
+ 0,
+ pdev->name, dev);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to devm_request_irq %d (%d)",
+ dev->jpegdec_irq, ret);
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
+{
+ struct mtk_jpegdec_clk *jpegdec_clk;
+ struct mtk_jpeg_dev *master_dev;
+ struct mtk_jpegdec_comp_dev *dev;
+ int ret;
+
+ struct device *decs = &pdev->dev;
+
+ if (!decs->parent)
+ return -EPROBE_DEFER;
+
+ master_dev = dev_get_drvdata(decs->parent);
+ if (!master_dev)
+ return -EPROBE_DEFER;
+
+ dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return -ENOMEM;
+
+ dev->plat_dev = pdev;
+ dev->dev = &pdev->dev;
+ jpegdec_clk = &dev->jdec_clk;
+
+ jpegdec_clk->clk_num = devm_clk_bulk_get_all(&pdev->dev,
+ &jpegdec_clk->clks);
+ if (jpegdec_clk->clk_num < 0)
+ return dev_err_probe(&pdev->dev,
+ jpegdec_clk->clk_num,
+ "Failed to get jpegdec clock count.\n");
+
+ dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(dev->reg_base))
+ return PTR_ERR(dev->reg_base);
+
+ ret = mtk_jpegdec_hw_init_irq(dev);
+ if (ret)
+ return dev_err_probe(&pdev->dev,
+ ret,
+ "Failed to register JPEGDEC irq handler.\n");
+
+ of_property_read_u32(decs->of_node, "hw_id",
+ &dev->hw_id);
+
+ if (dev->hw_id >= 0 || dev->hw_id < MTK_JPEGDEC_HW_MAX) {
+ master_dev->dec_hw_dev[dev->hw_id] = dev;
+ master_dev->reg_decbase[dev->hw_id] = dev->reg_base;
+ dev->master_dev = master_dev;
+ } else {
+ return dev_err_probe(&pdev->dev, dev->hw_id,
+ "Invalid hw id\n");
+ }
+
+ platform_set_drvdata(pdev, dev);
+ pm_runtime_enable(&pdev->dev);
+
+ return 0;
+}
+
+struct platform_driver mtk_jpegdec_hw_driver = {
+ .probe = mtk_jpegdec_hw_probe,
+ .driver = {
+ .name = "mtk-jpegdec-hw",
+ .of_match_table = of_match_ptr(mtk_jpegdec_hw_ids),
+ },
+};
+
+module_platform_driver(mtk_jpegdec_hw_driver);
+
+MODULE_DESCRIPTION("MediaTek JPEG decode HW driver");
+MODULE_LICENSE("GPL");
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [V4,4/8] media: mtk-jpegdec: add jpegdec timeout func interface
2022-06-27 2:55 [V4,0/8] Support multi-hardware jpeg decoder for MT8195 Irui Wang
` (2 preceding siblings ...)
2022-06-27 2:55 ` [PV4,3/8] media: mtk-jpegdec: manage jpegdec multi-hardware Irui Wang
@ 2022-06-27 2:55 ` Irui Wang
2022-06-27 2:55 ` [V4,5/8] media: mtk-jpegdec: add jpeg decode worker interface Irui Wang
` (3 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Irui Wang @ 2022-06-27 2:55 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Tzung-Bi Shih, angelogioacchino.delregno,
nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
From: kyrie wu <kyrie.wu@mediatek.com>
Generalizes jpegdec timeout func interfaces to handle HW timeout.
Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
---
.../platform/mediatek/jpeg/mtk_jpeg_core.h | 2 ++
.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 25 +++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index 29cd71fd713e..353ce40f6ca2 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -171,6 +171,8 @@ struct mtk_jpegdec_comp_dev {
struct mtk_jpegdec_clk jdec_clk;
int jpegdec_irq;
int hw_id;
+ struct delayed_work job_timeout_work;
+ struct mtk_jpeg_hw_param hw_param;
};
/**
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index fc98fe122874..e9e99fea656e 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -440,6 +440,25 @@ void mtk_jpeg_dec_set_config(void __iomem *base,
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_config);
+static void mtk_jpegdec_timeout_work(struct work_struct *work)
+{
+ enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
+ struct mtk_jpegdec_comp_dev *cjpeg =
+ container_of(work, struct mtk_jpegdec_comp_dev,
+ job_timeout_work.work);
+ struct vb2_v4l2_buffer *src_buf, *dst_buf;
+
+ src_buf = cjpeg->hw_param.src_buffer;
+ dst_buf = cjpeg->hw_param.dst_buffer;
+ v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
+
+ mtk_jpeg_dec_reset(cjpeg->reg_base);
+ clk_disable_unprepare(cjpeg->jdec_clk.clks->clk);
+ pm_runtime_put(cjpeg->dev);
+ v4l2_m2m_buf_done(src_buf, buf_state);
+ v4l2_m2m_buf_done(dst_buf, buf_state);
+}
+
static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
{
struct vb2_v4l2_buffer *src_buf, *dst_buf;
@@ -453,6 +472,8 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
struct mtk_jpegdec_comp_dev *jpeg = priv;
struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev;
+ cancel_delayed_work(&jpeg->job_timeout_work);
+
irq_status = mtk_jpeg_dec_get_int_status(jpeg->reg_base);
dec_irq_ret = mtk_jpeg_dec_enum_result(irq_status);
if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
@@ -533,6 +554,10 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
dev->plat_dev = pdev;
dev->dev = &pdev->dev;
+
+ INIT_DELAYED_WORK(&dev->job_timeout_work,
+ mtk_jpegdec_timeout_work);
+
jpegdec_clk = &dev->jdec_clk;
jpegdec_clk->clk_num = devm_clk_bulk_get_all(&pdev->dev,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [V4,5/8] media: mtk-jpegdec: add jpeg decode worker interface
2022-06-27 2:55 [V4,0/8] Support multi-hardware jpeg decoder for MT8195 Irui Wang
` (3 preceding siblings ...)
2022-06-27 2:55 ` [V4,4/8] media: mtk-jpegdec: add jpegdec timeout func interface Irui Wang
@ 2022-06-27 2:55 ` Irui Wang
2022-06-27 2:55 ` [V4,6/8] media: mtk-jpegdec: add output pic reorder interface Irui Wang
` (2 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Irui Wang @ 2022-06-27 2:55 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Tzung-Bi Shih, angelogioacchino.delregno,
nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
From: kyrie wu <kyrie.wu@mediatek.com>
Add jpeg decoding worker to ensure that three HWs
run in parallel in MT8195.
Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
---
.../platform/mediatek/jpeg/mtk_jpeg_core.c | 184 ++++++++++++++++++
.../platform/mediatek/jpeg/mtk_jpeg_core.h | 6 +
.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 33 ++--
3 files changed, 212 insertions(+), 11 deletions(-)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 5683df94ac6a..d4eca0b22ace 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1096,6 +1096,171 @@ static void mtk_jpeg_enc_device_run(void *priv)
}
}
+static int mtk_jpegdec_select_hw(struct mtk_jpeg_ctx *ctx)
+{
+ struct mtk_jpegdec_comp_dev *comp_jpeg;
+ struct mtk_jpeg_dev *jpeg = ctx->jpeg;
+ unsigned long flags;
+ int hw_id = -1;
+ int i;
+
+ spin_lock_irqsave(&jpeg->hw_lock, flags);
+ for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) {
+ comp_jpeg = jpeg->dec_hw_dev[i];
+ if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) {
+ hw_id = i;
+ comp_jpeg->hw_state = MTK_JPEG_HW_BUSY;
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&jpeg->hw_lock, flags);
+
+ return hw_id;
+}
+
+static int mtk_jpegdec_deselect_hw(struct mtk_jpeg_dev *jpeg, int hw_id)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&jpeg->hw_lock, flags);
+ jpeg->dec_hw_dev[hw_id]->hw_state =
+ MTK_JPEG_HW_IDLE;
+ spin_unlock_irqrestore(&jpeg->hw_lock, flags);
+
+ return 0;
+}
+
+static int mtk_jpegdec_set_hw_param(struct mtk_jpeg_ctx *ctx,
+ int hw_id,
+ struct vb2_v4l2_buffer *src_buf,
+ struct vb2_v4l2_buffer *dst_buf)
+{
+ struct mtk_jpegdec_comp_dev *jpeg =
+ ctx->jpeg->dec_hw_dev[hw_id];
+
+ jpeg->hw_param.curr_ctx = ctx;
+ jpeg->hw_param.src_buffer = src_buf;
+ jpeg->hw_param.dst_buffer = dst_buf;
+
+ return 0;
+}
+
+static void mtk_jpegdec_worker(struct work_struct *work)
+{
+ struct mtk_jpeg_ctx *ctx = container_of(work, struct mtk_jpeg_ctx,
+ jpeg_work);
+ struct mtk_jpegdec_comp_dev *comp_jpeg[MTK_JPEGDEC_HW_MAX];
+ enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
+ struct mtk_jpeg_src_buf *jpeg_src_buf, *jpeg_dst_buf;
+ struct vb2_v4l2_buffer *src_buf, *dst_buf;
+ struct mtk_jpeg_dev *jpeg = ctx->jpeg;
+ int ret, i, hw_id = 0;
+ struct mtk_jpeg_bs bs;
+ struct mtk_jpeg_fb fb;
+ unsigned long flags;
+
+ for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++)
+ comp_jpeg[i] = jpeg->dec_hw_dev[i];
+
+retry_select:
+ hw_id = mtk_jpegdec_select_hw(ctx);
+ if (hw_id < 0) {
+ ret = wait_event_interruptible_timeout(jpeg->dec_hw_wq,
+ atomic_read(&jpeg->dechw_rdy) > 0,
+ MTK_JPEG_HW_TIMEOUT_MSEC);
+ if (ret != 0) {
+ dev_err(jpeg->dev, "%s : %d, all HW are busy\n",
+ __func__, __LINE__);
+ v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
+ return;
+ }
+
+ goto retry_select;
+ }
+
+ atomic_dec(&jpeg->dechw_rdy);
+ src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
+ if (!src_buf)
+ goto getbuf_fail;
+
+ dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
+ if (!dst_buf)
+ goto getbuf_fail;
+
+ v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+ v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+
+ v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
+ jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(&src_buf->vb2_buf);
+ jpeg_dst_buf = mtk_jpeg_vb2_to_srcbuf(&dst_buf->vb2_buf);
+
+ if (mtk_jpeg_check_resolution_change(ctx,
+ &jpeg_src_buf->dec_param)) {
+ mtk_jpeg_queue_src_chg_event(ctx);
+ ctx->state = MTK_JPEG_SOURCE_CHANGE;
+ goto dec_end;
+ }
+
+ jpeg_src_buf->curr_ctx = ctx;
+ jpeg_src_buf->frame_num = ctx->total_frame_num;
+ jpeg_dst_buf->curr_ctx = ctx;
+ jpeg_dst_buf->frame_num = ctx->total_frame_num;
+ ctx->total_frame_num++;
+
+ mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf);
+ ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev);
+ if (ret < 0) {
+ dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n",
+ __func__, __LINE__);
+ goto dec_end;
+ }
+
+ ret = clk_prepare_enable(comp_jpeg[hw_id]->jdec_clk.clks->clk);
+ if (ret) {
+ dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n",
+ __func__, __LINE__);
+ goto clk_end;
+ }
+
+ schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work,
+ msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));
+
+ mtk_jpeg_set_dec_src(ctx, &src_buf->vb2_buf, &bs);
+ if (mtk_jpeg_set_dec_dst(ctx,
+ &jpeg_src_buf->dec_param,
+ &dst_buf->vb2_buf, &fb)) {
+ dev_err(jpeg->dev, "%s : %d, mtk_jpeg_set_dec_dst fail\n",
+ __func__, __LINE__);
+ goto setdst_end;
+ }
+
+ spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags);
+ mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base);
+ mtk_jpeg_dec_set_config(jpeg->reg_base,
+ &jpeg_src_buf->dec_param,
+ &bs,
+ &fb);
+ mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base);
+ v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
+ spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
+
+ return;
+
+setdst_end:
+ clk_disable_unprepare(comp_jpeg[hw_id]->jdec_clk.clks->clk);
+clk_end:
+ pm_runtime_put(comp_jpeg[hw_id]->dev);
+dec_end:
+ v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+ v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+ v4l2_m2m_buf_done(src_buf, buf_state);
+ v4l2_m2m_buf_done(dst_buf, buf_state);
+getbuf_fail:
+ atomic_inc(&jpeg->dechw_rdy);
+ mtk_jpegdec_deselect_hw(jpeg, hw_id);
+ v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
+}
+
static void mtk_jpeg_dec_device_run(void *priv)
{
struct mtk_jpeg_ctx *ctx = priv;
@@ -1108,6 +1273,7 @@ static void mtk_jpeg_dec_device_run(void *priv)
struct mtk_jpeg_fb fb;
int ret;
+if (!jpeg->is_jpgdec_multihw) {
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(&src_buf->vb2_buf);
@@ -1145,6 +1311,9 @@ static void mtk_jpeg_dec_device_run(void *priv)
v4l2_m2m_buf_done(src_buf, buf_state);
v4l2_m2m_buf_done(dst_buf, buf_state);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
+} else {
+ queue_work(jpeg->workqueue, &ctx->jpeg_work);
+}
}
static int mtk_jpeg_dec_job_ready(void *priv)
@@ -1361,6 +1530,9 @@ static int mtk_jpeg_open(struct file *file)
if (jpeg->is_jpgenc_multihw)
INIT_WORK(&ctx->jpeg_work, mtk_jpegenc_worker);
+ if (jpeg->is_jpgdec_multihw)
+ INIT_WORK(&ctx->jpeg_work, mtk_jpegdec_worker);
+
INIT_LIST_HEAD(&ctx->dst_done_queue);
spin_lock_init(&ctx->done_queue_lock);
v4l2_fh_init(&ctx->fh, vfd);
@@ -1526,6 +1698,18 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
goto err_alloc_workqueue;
}
}
+
+ if (of_property_read_bool(pdev->dev.of_node,
+ "mediatek,jpegdec-multi-core")) {
+ init_waitqueue_head(&jpeg->dec_hw_wq);
+ jpeg->workqueue = alloc_ordered_workqueue(MTK_JPEG_NAME,
+ WQ_MEM_RECLAIM
+ | WQ_FREEZABLE);
+ if (!jpeg->workqueue) {
+ ret = -EINVAL;
+ goto err_alloc_workqueue;
+ }
+ }
}
ret = v4l2_device_register(&pdev->dev, &jpeg->v4l2_dev);
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index 353ce40f6ca2..a158017c7767 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -173,6 +173,9 @@ struct mtk_jpegdec_comp_dev {
int hw_id;
struct delayed_work job_timeout_work;
struct mtk_jpeg_hw_param hw_param;
+ enum mtk_jpeg_hw_state hw_state;
+ //spinlock protecting the hw device resource
+ spinlock_t hw_lock;
};
/**
@@ -211,6 +214,9 @@ struct mtk_jpeg_dev {
void __iomem *reg_decbase[MTK_JPEGDEC_HW_MAX];
struct mtk_jpegdec_comp_dev *dec_hw_dev[MTK_JPEGDEC_HW_MAX];
bool is_jpgdec_multihw;
+ wait_queue_head_t dec_hw_wq;
+ struct workqueue_struct *dec_workqueue;
+ atomic_t dechw_rdy;
};
/**
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index e9e99fea656e..a8d63242ea8f 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -446,6 +446,7 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
struct mtk_jpegdec_comp_dev *cjpeg =
container_of(work, struct mtk_jpegdec_comp_dev,
job_timeout_work.work);
+ struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
src_buf = cjpeg->hw_param.src_buffer;
@@ -455,6 +456,9 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
mtk_jpeg_dec_reset(cjpeg->reg_base);
clk_disable_unprepare(cjpeg->jdec_clk.clks->clk);
pm_runtime_put(cjpeg->dev);
+ cjpeg->hw_state = MTK_JPEG_HW_IDLE;
+ atomic_inc(&master_jpeg->dechw_rdy);
+ wake_up(&master_jpeg->dec_hw_wq);
v4l2_m2m_buf_done(src_buf, buf_state);
v4l2_m2m_buf_done(dst_buf, buf_state);
}
@@ -474,22 +478,21 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
cancel_delayed_work(&jpeg->job_timeout_work);
+ ctx = jpeg->hw_param.curr_ctx;
+ src_buf = jpeg->hw_param.src_buffer;
+ dst_buf = jpeg->hw_param.dst_buffer;
+ v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
+
irq_status = mtk_jpeg_dec_get_int_status(jpeg->reg_base);
dec_irq_ret = mtk_jpeg_dec_enum_result(irq_status);
if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
mtk_jpeg_dec_reset(jpeg->reg_base);
- if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE)
- return IRQ_NONE;
- ctx = v4l2_m2m_get_curr_priv(master_jpeg->m2m_dev);
- if (!ctx) {
- dev_err(jpeg->dev, "Context is NULL\n");
- return IRQ_HANDLED;
+ if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE) {
+ dev_err(jpeg->dev, " Not MTK_JPEG_DEC_RESULT_EOF_DONE\n");
+ goto irq_handled;
}
- src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
- dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
- v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
jpeg_src_buf =
container_of(src_buf, struct mtk_jpeg_src_buf, b);
@@ -497,12 +500,16 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
vb2_set_plane_payload(&dst_buf->vb2_buf, i,
jpeg_src_buf->dec_param.comp_size[i]);
+irq_handled:
buf_state = VB2_BUF_STATE_DONE;
-
v4l2_m2m_buf_done(src_buf, buf_state);
v4l2_m2m_buf_done(dst_buf, buf_state);
- v4l2_m2m_job_finish(master_jpeg->m2m_dev, ctx->fh.m2m_ctx);
pm_runtime_put(ctx->jpeg->dev);
+ clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
+
+ jpeg->hw_state = MTK_JPEG_HW_IDLE;
+ wake_up(&master_jpeg->dec_hw_wq);
+ atomic_inc(&master_jpeg->dechw_rdy);
return IRQ_HANDLED;
}
@@ -555,6 +562,10 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
dev->plat_dev = pdev;
dev->dev = &pdev->dev;
+ atomic_set(&master_dev->dechw_rdy, MTK_JPEGDEC_HW_MAX);
+ spin_lock_init(&dev->hw_lock);
+ dev->hw_state = MTK_JPEG_HW_IDLE;
+
INIT_DELAYED_WORK(&dev->job_timeout_work,
mtk_jpegdec_timeout_work);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [V4,6/8] media: mtk-jpegdec: add output pic reorder interface
2022-06-27 2:55 [V4,0/8] Support multi-hardware jpeg decoder for MT8195 Irui Wang
` (4 preceding siblings ...)
2022-06-27 2:55 ` [V4,5/8] media: mtk-jpegdec: add jpeg decode worker interface Irui Wang
@ 2022-06-27 2:55 ` Irui Wang
2022-06-27 2:55 ` [V4,7/8] media: mtk-jpegdec: refactor jpegdec func interface Irui Wang
2022-06-27 2:55 ` [V4,8/8] mtk-jpegdec: add stop cmd interface for jpgdec Irui Wang
7 siblings, 0 replies; 15+ messages in thread
From: Irui Wang @ 2022-06-27 2:55 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Tzung-Bi Shih, angelogioacchino.delregno,
nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
From: kyrie wu <kyrie.wu@mediatek.com>
add output reorder func to reorder the output images
to ensure the output pic is consistent with the input images.
Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
---
.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 49 ++++++++++++++++++-
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index a8d63242ea8f..ea2dca88aae7 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -440,6 +440,51 @@ void mtk_jpeg_dec_set_config(void __iomem *base,
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_config);
+static void mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev *jpeg)
+{
+ struct mtk_jpeg_src_buf *dst_done_buf, *tmp_dst_done_buf;
+ struct vb2_v4l2_buffer *dst_buffer;
+ struct list_head *temp_entry;
+ struct list_head *pos = NULL;
+ struct mtk_jpeg_ctx *ctx;
+ unsigned long flags;
+
+ ctx = jpeg->hw_param.curr_ctx;
+ if (unlikely(!ctx)) {
+ dev_err(jpeg->dev, "comp_jpeg ctx fail !!!\n");
+ return;
+ }
+
+ dst_buffer = jpeg->hw_param.dst_buffer;
+ if (!dst_buffer) {
+ dev_err(jpeg->dev, "comp_jpeg dst_buffer fail !!!\n");
+ return;
+ }
+
+ dst_done_buf = container_of(dst_buffer, struct mtk_jpeg_src_buf, b);
+
+ spin_lock_irqsave(&ctx->done_queue_lock, flags);
+ list_add_tail(&dst_done_buf->list, &ctx->dst_done_queue);
+ while (!list_empty(&ctx->dst_done_queue) &&
+ (pos != &ctx->dst_done_queue)) {
+ list_for_each_prev_safe(pos,
+ temp_entry,
+ (&ctx->dst_done_queue)) {
+ tmp_dst_done_buf = list_entry(pos,
+ struct mtk_jpeg_src_buf,
+ list);
+ if (tmp_dst_done_buf->frame_num ==
+ ctx->last_done_frame_num) {
+ list_del(&tmp_dst_done_buf->list);
+ v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
+ VB2_BUF_STATE_DONE);
+ ctx->last_done_frame_num++;
+ }
+ }
+ }
+ spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
+}
+
static void mtk_jpegdec_timeout_work(struct work_struct *work)
{
enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
@@ -460,7 +505,7 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work)
atomic_inc(&master_jpeg->dechw_rdy);
wake_up(&master_jpeg->dec_hw_wq);
v4l2_m2m_buf_done(src_buf, buf_state);
- v4l2_m2m_buf_done(dst_buf, buf_state);
+ mtk_jpegdec_put_buf(cjpeg);
}
static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
@@ -503,7 +548,7 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
irq_handled:
buf_state = VB2_BUF_STATE_DONE;
v4l2_m2m_buf_done(src_buf, buf_state);
- v4l2_m2m_buf_done(dst_buf, buf_state);
+ mtk_jpegdec_put_buf(jpeg);
pm_runtime_put(ctx->jpeg->dev);
clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [V4,7/8] media: mtk-jpegdec: refactor jpegdec func interface
2022-06-27 2:55 [V4,0/8] Support multi-hardware jpeg decoder for MT8195 Irui Wang
` (5 preceding siblings ...)
2022-06-27 2:55 ` [V4,6/8] media: mtk-jpegdec: add output pic reorder interface Irui Wang
@ 2022-06-27 2:55 ` Irui Wang
2022-06-27 2:55 ` [V4,8/8] mtk-jpegdec: add stop cmd interface for jpgdec Irui Wang
7 siblings, 0 replies; 15+ messages in thread
From: Irui Wang @ 2022-06-27 2:55 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Tzung-Bi Shih, angelogioacchino.delregno,
nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
From: kyrie wu <kyrie.wu@mediatek.com>
refactor the func interface of mtk_jpeg_dec_set_config
for decode
Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
---
.../platform/mediatek/jpeg/mtk_jpeg_core.c | 38 +++++++++++--
.../platform/mediatek/jpeg/mtk_jpeg_core.h | 1 +
.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 55 ++++++++++---------
.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.h | 3 +-
.../platform/mediatek/jpeg/mtk_jpeg_dec_reg.h | 1 +
5 files changed, 66 insertions(+), 32 deletions(-)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index d4eca0b22ace..916c27fcfe9b 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -587,6 +587,31 @@ static int mtk_jpeg_enc_s_selection(struct file *file, void *priv,
return 0;
}
+static int mtk_jpeg_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
+{
+ struct v4l2_fh *fh = file->private_data;
+ struct mtk_jpeg_ctx *ctx = mtk_jpeg_fh_to_ctx(priv);
+ struct vb2_queue *vq;
+ struct vb2_buffer *vb;
+ struct mtk_jpeg_src_buf *jpeg_src_buf;
+
+ if (buf->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+ goto end;
+
+ vq = v4l2_m2m_get_vq(fh->m2m_ctx, buf->type);
+ if (buf->index >= vq->num_buffers) {
+ dev_err(ctx->jpeg->dev, "buffer index out of range\n");
+ return -EINVAL;
+ }
+
+ vb = vq->bufs[buf->index];
+ jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(vb);
+ jpeg_src_buf->bs_size = buf->m.planes[0].bytesused;
+
+end:
+ return v4l2_m2m_qbuf(file, fh->m2m_ctx, buf);
+}
+
static const struct v4l2_ioctl_ops mtk_jpeg_enc_ioctl_ops = {
.vidioc_querycap = mtk_jpeg_querycap,
.vidioc_enum_fmt_vid_cap = mtk_jpeg_enum_fmt_vid_cap,
@@ -627,7 +652,7 @@ static const struct v4l2_ioctl_ops mtk_jpeg_dec_ioctl_ops = {
.vidioc_g_fmt_vid_out_mplane = mtk_jpeg_g_fmt_vid_mplane,
.vidioc_s_fmt_vid_cap_mplane = mtk_jpeg_s_fmt_vid_cap_mplane,
.vidioc_s_fmt_vid_out_mplane = mtk_jpeg_s_fmt_vid_out_mplane,
- .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
+ .vidioc_qbuf = mtk_jpeg_qbuf,
.vidioc_subscribe_event = mtk_jpeg_subscribe_event,
.vidioc_g_selection = mtk_jpeg_dec_g_selection,
@@ -1205,7 +1230,6 @@ static void mtk_jpegdec_worker(struct work_struct *work)
jpeg_src_buf->frame_num = ctx->total_frame_num;
jpeg_dst_buf->curr_ctx = ctx;
jpeg_dst_buf->frame_num = ctx->total_frame_num;
- ctx->total_frame_num++;
mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf);
ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev);
@@ -1235,9 +1259,11 @@ static void mtk_jpegdec_worker(struct work_struct *work)
}
spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags);
+ ctx->total_frame_num++;
mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base);
- mtk_jpeg_dec_set_config(jpeg->reg_base,
+ mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base,
&jpeg_src_buf->dec_param,
+ jpeg_src_buf->bs_size,
&bs,
&fb);
mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base);
@@ -1299,8 +1325,10 @@ if (!jpeg->is_jpgdec_multihw) {
spin_lock_irqsave(&jpeg->hw_lock, flags);
mtk_jpeg_dec_reset(jpeg->reg_base);
mtk_jpeg_dec_set_config(jpeg->reg_base,
- &jpeg_src_buf->dec_param, &bs, &fb);
-
+ &jpeg_src_buf->dec_param,
+ jpeg_src_buf->bs_size,
+ &bs,
+ &fb);
mtk_jpeg_dec_start(jpeg->reg_base);
spin_unlock_irqrestore(&jpeg->hw_lock, flags);
return;
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index a158017c7767..b00b12125863 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -80,6 +80,7 @@ struct mtk_jpeg_src_buf {
u32 frame_num;
struct vb2_v4l2_buffer b;
struct list_head list;
+ u32 bs_size;
struct mtk_jpeg_dec_param dec_param;
struct mtk_jpeg_ctx *curr_ctx;
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index ea2dca88aae7..350e13af1192 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -330,12 +330,14 @@ static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, u32 ptr)
writel(ptr, base + JPGDEC_REG_FILE_BRP);
}
-static void mtk_jpeg_dec_set_bs_info(void __iomem *base, u32 addr, u32 size)
+static void mtk_jpeg_dec_set_bs_info(void __iomem *base, u32 addr, u32 size,
+ u32 bitstream_size)
{
mtk_jpeg_verify_align(addr, 16, JPGDEC_REG_FILE_ADDR);
mtk_jpeg_verify_align(size, 128, JPGDEC_REG_FILE_TOTAL_SIZE);
writel(addr, base + JPGDEC_REG_FILE_ADDR);
writel(size, base + JPGDEC_REG_FILE_TOTAL_SIZE);
+ writel(bitstream_size, base + JPGDEC_REG_BIT_STREAM_SIZE);
}
static void mtk_jpeg_dec_set_comp_id(void __iomem *base, u32 id_y, u32 id_u,
@@ -404,39 +406,40 @@ static void mtk_jpeg_dec_set_sampling_factor(void __iomem *base, u32 comp_num,
}
void mtk_jpeg_dec_set_config(void __iomem *base,
- struct mtk_jpeg_dec_param *config,
+ struct mtk_jpeg_dec_param *cfg,
+ u32 bitstream_size,
struct mtk_jpeg_bs *bs,
struct mtk_jpeg_fb *fb)
{
- mtk_jpeg_dec_set_brz_factor(base, 0, 0, config->uv_brz_w, 0);
+ mtk_jpeg_dec_set_brz_factor(base, 0, 0, cfg->uv_brz_w, 0);
mtk_jpeg_dec_set_dec_mode(base, 0);
- mtk_jpeg_dec_set_comp0_du(base, config->unit_num);
- mtk_jpeg_dec_set_total_mcu(base, config->total_mcu);
- mtk_jpeg_dec_set_bs_info(base, bs->str_addr, bs->size);
+ mtk_jpeg_dec_set_comp0_du(base, cfg->unit_num);
+ mtk_jpeg_dec_set_total_mcu(base, cfg->total_mcu);
+ mtk_jpeg_dec_set_bs_info(base, bs->str_addr, bs->size, bitstream_size);
mtk_jpeg_dec_set_bs_write_ptr(base, bs->end_addr);
- mtk_jpeg_dec_set_du_membership(base, config->membership, 1,
- (config->comp_num == 1) ? 1 : 0);
- mtk_jpeg_dec_set_comp_id(base, config->comp_id[0], config->comp_id[1],
- config->comp_id[2]);
- mtk_jpeg_dec_set_q_table(base, config->qtbl_num[0],
- config->qtbl_num[1], config->qtbl_num[2]);
- mtk_jpeg_dec_set_sampling_factor(base, config->comp_num,
- config->sampling_w[0],
- config->sampling_h[0],
- config->sampling_w[1],
- config->sampling_h[1],
- config->sampling_w[2],
- config->sampling_h[2]);
- mtk_jpeg_dec_set_mem_stride(base, config->mem_stride[0],
- config->mem_stride[1]);
- mtk_jpeg_dec_set_img_stride(base, config->img_stride[0],
- config->img_stride[1]);
+ mtk_jpeg_dec_set_du_membership(base, cfg->membership, 1,
+ (cfg->comp_num == 1) ? 1 : 0);
+ mtk_jpeg_dec_set_comp_id(base, cfg->comp_id[0], cfg->comp_id[1],
+ cfg->comp_id[2]);
+ mtk_jpeg_dec_set_q_table(base, cfg->qtbl_num[0],
+ cfg->qtbl_num[1], cfg->qtbl_num[2]);
+ mtk_jpeg_dec_set_sampling_factor(base, cfg->comp_num,
+ cfg->sampling_w[0],
+ cfg->sampling_h[0],
+ cfg->sampling_w[1],
+ cfg->sampling_h[1],
+ cfg->sampling_w[2],
+ cfg->sampling_h[2]);
+ mtk_jpeg_dec_set_mem_stride(base, cfg->mem_stride[0],
+ cfg->mem_stride[1]);
+ mtk_jpeg_dec_set_img_stride(base, cfg->img_stride[0],
+ cfg->img_stride[1]);
mtk_jpeg_dec_set_dst_bank0(base, fb->plane_addr[0],
fb->plane_addr[1], fb->plane_addr[2]);
mtk_jpeg_dec_set_dst_bank1(base, 0, 0, 0);
- mtk_jpeg_dec_set_dma_group(base, config->dma_mcu, config->dma_group,
- config->dma_last_mcu);
- mtk_jpeg_dec_set_pause_mcu_idx(base, config->total_mcu);
+ mtk_jpeg_dec_set_dma_group(base, cfg->dma_mcu, cfg->dma_group,
+ cfg->dma_last_mcu);
+ mtk_jpeg_dec_set_pause_mcu_idx(base, cfg->total_mcu);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_config);
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
index 87aaa5c9082b..8c31c6b12417 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
@@ -71,7 +71,8 @@ int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param);
u32 mtk_jpeg_dec_get_int_status(void __iomem *dec_reg_base);
u32 mtk_jpeg_dec_enum_result(u32 irq_result);
void mtk_jpeg_dec_set_config(void __iomem *base,
- struct mtk_jpeg_dec_param *config,
+ struct mtk_jpeg_dec_param *cfg,
+ u32 bitstream_size,
struct mtk_jpeg_bs *bs,
struct mtk_jpeg_fb *fb);
void mtk_jpeg_dec_reset(void __iomem *dec_reg_base);
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
index 21ec8f96797f..27b7711ca341 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
@@ -45,5 +45,6 @@
#define JPGDEC_REG_QT_ID 0x0270
#define JPGDEC_REG_INTERRUPT_STATUS 0x0274
#define JPGDEC_REG_STATUS 0x0278
+#define JPGDEC_REG_BIT_STREAM_SIZE 0x0344
#endif /* _MTK_JPEG_REG_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [V4,8/8] mtk-jpegdec: add stop cmd interface for jpgdec
2022-06-27 2:55 [V4,0/8] Support multi-hardware jpeg decoder for MT8195 Irui Wang
` (6 preceding siblings ...)
2022-06-27 2:55 ` [V4,7/8] media: mtk-jpegdec: refactor jpegdec func interface Irui Wang
@ 2022-06-27 2:55 ` Irui Wang
7 siblings, 0 replies; 15+ messages in thread
From: Irui Wang @ 2022-06-27 2:55 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Tzung-Bi Shih, angelogioacchino.delregno,
nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
From: kyrie wu <kyrie.wu@mediatek.com>
Add stop cmd interface for jpgdec to stop stream
Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
---
drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 916c27fcfe9b..23d6b685dd7d 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -666,6 +666,9 @@ static const struct v4l2_ioctl_ops mtk_jpeg_dec_ioctl_ops = {
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+
+ .vidioc_decoder_cmd = v4l2_m2m_ioctl_decoder_cmd,
+ .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd,
};
static int mtk_jpeg_queue_setup(struct vb2_queue *q,
--
2.18.0
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^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible
2022-06-27 2:55 ` [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible Irui Wang
@ 2022-07-01 15:29 ` Rob Herring
2022-07-14 8:42 ` kyrie.wu
2022-07-05 13:00 ` AngeloGioacchino Del Regno
1 sibling, 1 reply; 15+ messages in thread
From: Rob Herring @ 2022-07-01 15:29 UTC (permalink / raw)
To: Irui Wang
Cc: Hans Verkuil, Mauro Carvalho Chehab, Matthias Brugger,
Tzung-Bi Shih, angelogioacchino.delregno, nicolas.dufresne,
wenst, Project_Global_Chrome_Upstream_Group, linux-media,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Tomasz Figa, xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
On Mon, Jun 27, 2022 at 10:55:33AM +0800, Irui Wang wrote:
> From: kyrie wu <kyrie.wu@mediatek.com>
>
> Add mediatek,mt8195-jpgdec compatible to binding document.
>
> Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
> ---
> .../media/mediatek,mt8195-jpegdec.yaml | 176 ++++++++++++++++++
> 1 file changed, 176 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
> new file mode 100644
> index 000000000000..8a255e8e2e09
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
> @@ -0,0 +1,176 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek JPEG Encoder Device Tree Bindings
s/Device Tree Bindings//
> +
> +maintainers:
> + - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
> +
> +description: |-
Don't need '|-'
> + MediaTek JPEG Decoder is the JPEG decode hardware present in MediaTek SoCs
> +
> +properties:
> + compatible:
> + items:
> + - const: mediatek,mt8195-jpgdec
> +
> + mediatek,jpegdec-multi-core:
> + type: boolean
> + description: |
Don't need '|'
> + Indicates whether the jpeg encoder has multiple cores or not.
Can't this be implied from the child nodes?
> +
> + power-domains:
> + maxItems: 1
> +
> + iommus:
> + maxItems: 6
> + description: |
> + Points to the respective IOMMU block with master port as argument, see
> + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> + Ports are according to the HW.
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + ranges: true
> +
> +# Required child node:
> +patternProperties:
> + "^jpgdec@[0-9a-f]+$":
> + type: object
> + description: |
> + The jpeg decoder hardware device node which should be added as subnodes to
> + the main jpeg node.
> +
> + properties:
> + compatible:
> + const: mediatek,mt8195-jpgdec-hw
> +
> + reg:
> + maxItems: 1
> +
> + hw_id:
So a similar, but different property from the video codec? Either way,
this property should go. We don't do indexes in DT.
Why do you need this?
> + description: |
> + MT8195 decoding hardware id value. MT8195 has three decoding hardwares,
> + which is represented by this parameter.
> +
> + iommus:
> + minItems: 1
> + maxItems: 32
> + description: |
> + List of the hardware port in respective IOMMU block for current Socs.
> + Refer to bindings/iommu/mediatek,iommu.yaml.
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: jpgdec
> +
> + power-domains:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> + - hw_id
> + - iommus
> + - interrupts
> + - clocks
> + - clock-names
> + - power-domains
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - power-domains
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/memory/mt8195-memory-port.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/mt8195-clk.h>
> + #include <dt-bindings/power/mt8195-power.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + jpgdec_master {
> + compatible = "mediatek,mt8195-jpgdec";
> + mediatek,jpegdec-multi-core;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
> + iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + jpgdec@1a040000 {
> + compatible = "mediatek,mt8195-jpgdec-hw";
> + reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
> + hw_id = <0>;
> + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vencsys CLK_VENC_JPGDEC>;
> + clock-names = "jpgdec";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
> + };
> +
> + jpgdec@1a050000 {
> + compatible = "mediatek,mt8195-jpgdec-hw";
> + reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
> + hw_id = <1>;
> + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
> + clock-names = "jpgdec";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
> + };
> +
> + jpgdec@1b040000 {
> + compatible = "mediatek,mt8195-jpgdec-hw";
> + reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
> + hw_id = <2>;
> + iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
> + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
> + clock-names = "jpgdec";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
> + };
> + };
> + };
> --
> 2.18.0
>
>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible
2022-06-27 2:55 ` [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible Irui Wang
2022-07-01 15:29 ` Rob Herring
@ 2022-07-05 13:00 ` AngeloGioacchino Del Regno
2022-07-14 8:56 ` kyrie.wu
1 sibling, 1 reply; 15+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-07-05 13:00 UTC (permalink / raw)
To: Irui Wang, Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Tzung-Bi Shih, nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
Il 27/06/22 04:55, Irui Wang ha scritto:
> From: kyrie wu <kyrie.wu@mediatek.com>
>
> Add mediatek,mt8195-jpgdec compatible to binding document.
>
> Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
> ---
> .../media/mediatek,mt8195-jpegdec.yaml | 176 ++++++++++++++++++
> 1 file changed, 176 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
> new file mode 100644
> index 000000000000..8a255e8e2e09
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
> @@ -0,0 +1,176 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
...snip...
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/memory/mt8195-memory-port.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/mt8195-clk.h>
> + #include <dt-bindings/power/mt8195-power.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + jpgdec_master {
Additionally to Rob's review, which I of course fully agree on, this example
devicetree does *not* work on MT8195.
[ 13.015716] mtk-jpegdec-hw 1a040000.jpgdec: Adding to iommu group 1
[ 13.025383] mtk-jpegdec-hw 1a050000.jpgdec: Adding to iommu group 1
[ 13.034814] mtk-jpegdec-hw 1b040000.jpgdec: Adding to iommu group 1
[ 13.041672] mtk-jpeg soc:jpgdec_master: invalid resource
[ 13.049758] mtk-jpeg: probe of soc:jpgdec_master failed with error -22
Regards,
Angelo
> + compatible = "mediatek,mt8195-jpgdec";
> + mediatek,jpegdec-multi-core;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
> + iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + jpgdec@1a040000 {
> + compatible = "mediatek,mt8195-jpgdec-hw";
> + reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
> + hw_id = <0>;
> + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vencsys CLK_VENC_JPGDEC>;
> + clock-names = "jpgdec";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
> + };
> +
> + jpgdec@1a050000 {
> + compatible = "mediatek,mt8195-jpgdec-hw";
> + reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
> + hw_id = <1>;
> + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
> + clock-names = "jpgdec";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
> + };
> +
> + jpgdec@1b040000 {
> + compatible = "mediatek,mt8195-jpgdec-hw";
> + reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
> + hw_id = <2>;
> + iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
> + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
> + clock-names = "jpgdec";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
> + };
> + };
> + };
_______________________________________________
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PV4,3/8] media: mtk-jpegdec: manage jpegdec multi-hardware
2022-06-27 2:55 ` [PV4,3/8] media: mtk-jpegdec: manage jpegdec multi-hardware Irui Wang
@ 2022-07-05 13:36 ` AngeloGioacchino Del Regno
2022-07-14 8:55 ` kyrie.wu
0 siblings, 1 reply; 15+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-07-05 13:36 UTC (permalink / raw)
To: Irui Wang, Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Tzung-Bi Shih, nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, kyrie wu, srv_heupstream
Il 27/06/22 04:55, Irui Wang ha scritto:
> From: kyrie wu <kyrie.wu@mediatek.com>
>
> manage each hardware information, including irq/clk/power.
> the hardware includes HW0/HW1/HW2.
>
> Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
> ---
> drivers/media/platform/mediatek/jpeg/Makefile | 5 +-
> .../platform/mediatek/jpeg/mtk_jpeg_core.c | 25 ++-
> .../platform/mediatek/jpeg/mtk_jpeg_core.h | 38 ++++
> .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 168 ++++++++++++++++++
> 4 files changed, 232 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/media/platform/mediatek/jpeg/Makefile b/drivers/media/platform/mediatek/jpeg/Makefile
> index 69703db4b0a5..26e84852523e 100644
> --- a/drivers/media/platform/mediatek/jpeg/Makefile
> +++ b/drivers/media/platform/mediatek/jpeg/Makefile
> @@ -1,9 +1,10 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o \
> - mtk-jpeg-enc-hw.o
> + mtk-jpeg-enc-hw.o \
> + mtk-jpeg-dec-hw.o
>
> mtk_jpeg-y := mtk_jpeg_core.o \
> - mtk_jpeg_dec_hw.o \
> mtk_jpeg_dec_parse.o
>
> mtk-jpeg-enc-hw-y := mtk_jpeg_enc_hw.o
> +mtk-jpeg-dec-hw-y := mtk_jpeg_dec_hw.o
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> index 2696651b457b..5683df94ac6a 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> @@ -1467,8 +1467,14 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
> jpeg->variant = of_device_get_match_data(jpeg->dev);
>
> if (of_property_read_bool(pdev->dev.of_node,
> - "mediatek,jpegenc-multi-core")) {
> + "mediatek,jpegenc-multi-core"))
> jpeg->is_jpgenc_multihw = true;
> +
> + if (of_property_read_bool(pdev->dev.of_node,
> + "mediatek,jpegdec-multi-core"))
> + jpeg->is_jpgdec_multihw = true;
> +
> + if (jpeg->is_jpgenc_multihw || jpeg->is_jpgdec_multihw) {
> ret = devm_of_platform_populate(&pdev->dev);
> if (ret) {
> v4l2_err(&jpeg->v4l2_dev, "Master of platform populate failed.");
> @@ -1476,7 +1482,7 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
> }
> }
>
> - if (!jpeg->is_jpgenc_multihw) {
> + if (!jpeg->is_jpgenc_multihw || jpeg->is_jpgdec_multihw) {
That's never going to work. I'm sure that you were meaning:
if (!jpeg->is_jpgenc_multihw && !jpeg->is_jpgdec_multihw) {
> INIT_DELAYED_WORK(&jpeg->job_timeout_work,
> mtk_jpeg_job_timeout_work);
>
> @@ -1693,6 +1699,17 @@ static const struct mtk_jpeg_variant mtk8195_jpegenc_drvdata = {
> .cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
> };
>
> +static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = {
> + .formats = mtk_jpeg_dec_formats,
> + .num_formats = MTK_JPEG_DEC_NUM_FORMATS,
> + .qops = &mtk_jpeg_dec_qops,
> + .m2m_ops = &mtk_jpeg_dec_m2m_ops,
> + .dev_name = "mtk-jpeg-dec",
> + .ioctl_ops = &mtk_jpeg_dec_ioctl_ops,
> + .out_q_default_fourcc = V4L2_PIX_FMT_JPEG,
> + .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
> +};
> +
> #if defined(CONFIG_OF)
> static const struct of_device_id mtk_jpeg_match[] = {
> {
> @@ -1711,6 +1728,10 @@ static const struct of_device_id mtk_jpeg_match[] = {
> .compatible = "mediatek,mt8195-jpgenc",
> .data = &mtk8195_jpegenc_drvdata,
> },
> + {
> + .compatible = "mediatek,mt8195-jpgdec",
> + .data = &mtk8195_jpegdec_drvdata,
> + },
> {},
> };
>
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> index f8415b6b1618..29cd71fd713e 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> @@ -102,6 +102,13 @@ enum mtk_jpegenc_hw_id {
> MTK_JPEGENC_HW_MAX,
> };
>
> +enum mtk_jpegdec_hw_id {
> + MTK_JPEGDEC_HW0,
> + MTK_JPEGDEC_HW1,
> + MTK_JPEGDEC_HW2,
> + MTK_JPEGDEC_HW_MAX,
> +};
> +
> /**
> * struct mtk_vcodec_clk - Structure used to store vcodec clock information
> */
> @@ -110,6 +117,14 @@ struct mtk_jpegenc_clk {
> int clk_num;
> };
>
> +/**
> + * struct mtk_vcodec_clk - Structure used to store vcodec clock information
This is not struct mtk_vcodec_clk, but mtk_jpegdec_clk. Please fix.
> + */
> +struct mtk_jpegdec_clk {
> + struct clk_bulk_data *clks;
> + int clk_num;
> +};
> +
> /**
> * struct mtk_jpegenc_comp_dev - JPEG COREX abstraction
> * @dev: JPEG device
> @@ -139,6 +154,25 @@ struct mtk_jpegenc_comp_dev {
> spinlock_t hw_lock;
> };
>
> +/**
> + * struct mtk_jpegdec_comp_dev - JPEG COREX abstraction
> + * @dev: JPEG device
> + * @plat_dev: platform device data
> + * @reg_base: JPEG registers mapping
> + * @master_dev: mtk_jpeg_dev device
> + * @jdec_clk: mtk_jpegdec_clk
Please fix indentation.
> + * @jpegdec_irq: jpeg decode irq num
> + */
> +struct mtk_jpegdec_comp_dev {
> + struct device *dev;
> + struct platform_device *plat_dev;
> + void __iomem *reg_base;
> + struct mtk_jpeg_dev *master_dev;
> + struct mtk_jpegdec_clk jdec_clk;
> + int jpegdec_irq;
> + int hw_id;
> +};
> +
> /**
> * struct mtk_jpeg_dev - JPEG IP abstraction
> * @lock: the mutex protecting this structure
> @@ -171,6 +205,10 @@ struct mtk_jpeg_dev {
> bool is_jpgenc_multihw;
> wait_queue_head_t enc_hw_wq;
> atomic_t enchw_rdy;
> +
> + void __iomem *reg_decbase[MTK_JPEGDEC_HW_MAX];
> + struct mtk_jpegdec_comp_dev *dec_hw_dev[MTK_JPEGDEC_HW_MAX];
> + bool is_jpgdec_multihw;
> };
>
> /**
> diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> index d2f25f43e852..fc98fe122874 100644
> --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> @@ -5,9 +5,24 @@
> * Rick Chang <rick.chang@mediatek.com>
> */
>
> +#include <linux/clk.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> #include <linux/io.h>
> #include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/slab.h>
> +#include <media/media-device.h>
> #include <media/videobuf2-core.h>
> +#include <media/videobuf2-v4l2.h>
> +#include <media/v4l2-mem2mem.h>
> +#include <media/v4l2-dev.h>
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-fh.h>
> +#include <media/v4l2-event.h>
>
> #include "mtk_jpeg_core.h"
> #include "mtk_jpeg_dec_hw.h"
> @@ -24,6 +39,16 @@ enum mtk_jpeg_color {
> MTK_JPEG_COLOR_400 = 0x00110000
> };
>
> +#if defined(CONFIG_OF)
> +static const struct of_device_id mtk_jpegdec_hw_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-jpgdec-hw",
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids);
> +#endif
> +
> static inline int mtk_jpeg_verify_align(u32 val, int align, u32 reg)
> {
> if (val & (align - 1)) {
> @@ -414,3 +439,146 @@ void mtk_jpeg_dec_set_config(void __iomem *base,
> mtk_jpeg_dec_set_pause_mcu_idx(base, config->total_mcu);
> }
> EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_config);
> +
> +static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
> +{
> + struct vb2_v4l2_buffer *src_buf, *dst_buf;
> + struct mtk_jpeg_src_buf *jpeg_src_buf;
> + enum vb2_buffer_state buf_state;
> + struct mtk_jpeg_ctx *ctx;
> + u32 dec_irq_ret;
> + u32 irq_status;
> + int i;
> +
> + struct mtk_jpegdec_comp_dev *jpeg = priv;
> + struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev;
> +
> + irq_status = mtk_jpeg_dec_get_int_status(jpeg->reg_base);
> + dec_irq_ret = mtk_jpeg_dec_enum_result(irq_status);
> + if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
> + mtk_jpeg_dec_reset(jpeg->reg_base);
> + if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE)
> + return IRQ_NONE;
> +
> + ctx = v4l2_m2m_get_curr_priv(master_jpeg->m2m_dev);
> + if (!ctx) {
> + dev_err(jpeg->dev, "Context is NULL\n");
> + return IRQ_HANDLED;
> + }
> +
> + src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
> + dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
> + v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
> + jpeg_src_buf =
> + container_of(src_buf, struct mtk_jpeg_src_buf, b);
> +
> + for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
> + vb2_set_plane_payload(&dst_buf->vb2_buf, i,
> + jpeg_src_buf->dec_param.comp_size[i]);
> +
> + buf_state = VB2_BUF_STATE_DONE;
> +
> + v4l2_m2m_buf_done(src_buf, buf_state);
> + v4l2_m2m_buf_done(dst_buf, buf_state);
> + v4l2_m2m_job_finish(master_jpeg->m2m_dev, ctx->fh.m2m_ctx);
> + pm_runtime_put(ctx->jpeg->dev);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev *dev)
> +{
> + struct platform_device *pdev = dev->plat_dev;
> + int ret;
> +
> + dev->jpegdec_irq = platform_get_irq(pdev, 0);
> + if (dev->jpegdec_irq < 0) {
> + dev_err(&pdev->dev, "Failed to get irq resource");
> + return dev->jpegdec_irq;
> + }
> +
> + ret = devm_request_irq(&pdev->dev,
> + dev->jpegdec_irq,
> + mtk_jpegdec_hw_irq_handler,
> + 0,
> + pdev->name, dev);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to devm_request_irq %d (%d)",
> + dev->jpegdec_irq, ret);
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
> +{
> + struct mtk_jpegdec_clk *jpegdec_clk;
> + struct mtk_jpeg_dev *master_dev;
> + struct mtk_jpegdec_comp_dev *dev;
> + int ret;
> +
> + struct device *decs = &pdev->dev;
> +
> + if (!decs->parent)
> + return -EPROBE_DEFER;
> +
> + master_dev = dev_get_drvdata(decs->parent);
> + if (!master_dev)
> + return -EPROBE_DEFER;
> +
> + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
> + if (!dev)
> + return -ENOMEM;
> +
> + dev->plat_dev = pdev;
> + dev->dev = &pdev->dev;
> + jpegdec_clk = &dev->jdec_clk;
> +
> + jpegdec_clk->clk_num = devm_clk_bulk_get_all(&pdev->dev,
> + &jpegdec_clk->clks);
> + if (jpegdec_clk->clk_num < 0)
> + return dev_err_probe(&pdev->dev,
> + jpegdec_clk->clk_num,
> + "Failed to get jpegdec clock count.\n");
> +
> + dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(dev->reg_base))
> + return PTR_ERR(dev->reg_base);
> +
> + ret = mtk_jpegdec_hw_init_irq(dev);
> + if (ret)
> + return dev_err_probe(&pdev->dev,
> + ret,
> + "Failed to register JPEGDEC irq handler.\n");
> +
> + of_property_read_u32(decs->of_node, "hw_id",
> + &dev->hw_id);
ret = of_property_read_u32( ..... )
if (ret)
return ret;
P.S.: Is it really important to get the hw_id from devicetree?
is there any difference between HW0, HW1, HW2?
Can we start decoding the first frame on HW1 or on HW2 instead of HW0?
Does this hardware really need to work in HW0->1->2 specific sequence?
Regards,
Angelo
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible
2022-07-01 15:29 ` Rob Herring
@ 2022-07-14 8:42 ` kyrie.wu
0 siblings, 0 replies; 15+ messages in thread
From: kyrie.wu @ 2022-07-14 8:42 UTC (permalink / raw)
To: Rob Herring, Irui Wang
Cc: Hans Verkuil, Mauro Carvalho Chehab, Matthias Brugger,
Tzung-Bi Shih, angelogioacchino.delregno, nicolas.dufresne,
wenst, Project_Global_Chrome_Upstream_Group, linux-media,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Tomasz Figa, xia.jiang, maoguang.meng, srv_heupstream
On Fri, 2022-07-01 at 09:29 -0600, Rob Herring wrote:
> On Mon, Jun 27, 2022 at 10:55:33AM +0800, Irui Wang wrote:
> > From: kyrie wu <kyrie.wu@mediatek.com>
> >
> > Add mediatek,mt8195-jpgdec compatible to binding document.
> >
> > Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
> > ---
> > .../media/mediatek,mt8195-jpegdec.yaml | 176
> > ++++++++++++++++++
> > 1 file changed, 176 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> > b/Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> > new file mode 100644
> > index 000000000000..8a255e8e2e09
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> > @@ -0,0 +1,176 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek JPEG Encoder Device Tree Bindings
>
> s/Device Tree Bindings//
>
> > +
> > +maintainers:
> > + - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
> > +
> > +description: |-
>
> Don't need '|-'
>
> > + MediaTek JPEG Decoder is the JPEG decode hardware present in
> > MediaTek SoCs
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: mediatek,mt8195-jpgdec
> > +
> > + mediatek,jpegdec-multi-core:
> > + type: boolean
> > + description: |
>
> Don't need '|'
>
> > + Indicates whether the jpeg encoder has multiple cores or
> > not.
>
> Can't this be implied from the child nodes?
Dear Rob,
I will remove is in the next version to simplify device node.
Kyrie.
>
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + iommus:
> > + maxItems: 6
> > + description: |
> > + Points to the respective IOMMU block with master port as
> > argument, see
> > + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > for details.
> > + Ports are according to the HW.
> > +
> > + "#address-cells":
> > + const: 2
> > +
> > + "#size-cells":
> > + const: 2
> > +
> > + ranges: true
> > +
> > +# Required child node:
> > +patternProperties:
> > + "^jpgdec@[0-9a-f]+$":
> > + type: object
> > + description: |
> > + The jpeg decoder hardware device node which should be added
> > as subnodes to
> > + the main jpeg node.
> > +
> > + properties:
> > + compatible:
> > + const: mediatek,mt8195-jpgdec-hw
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + hw_id:
>
> So a similar, but different property from the video codec? Either
> way,
> this property should go. We don't do indexes in DT.
>
> Why do you need this?
It also will be removed in the next version.
>
> > + description: |
> > + MT8195 decoding hardware id value. MT8195 has three
> > decoding hardwares,
> > + which is represented by this parameter.
> > +
> > + iommus:
> > + minItems: 1
> > + maxItems: 32
> > + description: |
> > + List of the hardware port in respective IOMMU block for
> > current Socs.
> > + Refer to bindings/iommu/mediatek,iommu.yaml.
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + clock-names:
> > + items:
> > + - const: jpgdec
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > + - reg
> > + - hw_id
> > + - iommus
> > + - interrupts
> > + - clocks
> > + - clock-names
> > + - power-domains
> > +
> > + additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - power-domains
> > + - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/memory/mt8195-memory-port.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/clock/mt8195-clk.h>
> > + #include <dt-bindings/power/mt8195-power.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + jpgdec_master {
> > + compatible = "mediatek,mt8195-jpgdec";
> > + mediatek,jpegdec-multi-core;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
> > + iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
> > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
> > + <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
> > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
> > + <&iommu_vpp
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> > + <&iommu_vpp
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + jpgdec@1a040000 {
> > + compatible = "mediatek,mt8195-jpgdec-hw";
> > + reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
> > + hw_id = <0>;
> > + iommus = <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_WDMA0>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> > + <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> > + <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> > + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&vencsys CLK_VENC_JPGDEC>;
> > + clock-names = "jpgdec";
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VDEC0>;
> > + };
> > +
> > + jpgdec@1a050000 {
> > + compatible = "mediatek,mt8195-jpgdec-hw";
> > + reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
> > + hw_id = <1>;
> > + iommus = <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_WDMA0>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> > + <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> > + <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> > + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
> > + clock-names = "jpgdec";
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VDEC1>;
> > + };
> > +
> > + jpgdec@1b040000 {
> > + compatible = "mediatek,mt8195-jpgdec-hw";
> > + reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
> > + hw_id = <2>;
> > + iommus = <&iommu_vpp
> > M4U_PORT_L20_JPGDEC_WDMA0>,
> > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
> > + <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
> > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
> > + <&iommu_vpp
> > M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
> > + <&iommu_vpp
> > M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
> > + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&vencsys_core1
> > CLK_VENC_CORE1_JPGDEC>;
> > + clock-names = "jpgdec";
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VDEC2>;
> > + };
> > + };
> > + };
> > --
> > 2.18.0
> >
> >
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PV4,3/8] media: mtk-jpegdec: manage jpegdec multi-hardware
2022-07-05 13:36 ` AngeloGioacchino Del Regno
@ 2022-07-14 8:55 ` kyrie.wu
0 siblings, 0 replies; 15+ messages in thread
From: kyrie.wu @ 2022-07-14 8:55 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Irui Wang, Hans Verkuil,
Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Tzung-Bi Shih, nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, srv_heupstream
On Tue, 2022-07-05 at 15:36 +0200, AngeloGioacchino Del Regno wrote:
> Il 27/06/22 04:55, Irui Wang ha scritto:
> > From: kyrie wu <kyrie.wu@mediatek.com>
> >
> > manage each hardware information, including irq/clk/power.
> > the hardware includes HW0/HW1/HW2.
> >
> > Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
> > ---
> > drivers/media/platform/mediatek/jpeg/Makefile | 5 +-
> > .../platform/mediatek/jpeg/mtk_jpeg_core.c | 25 ++-
> > .../platform/mediatek/jpeg/mtk_jpeg_core.h | 38 ++++
> > .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 168
> > ++++++++++++++++++
> > 4 files changed, 232 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/media/platform/mediatek/jpeg/Makefile
> > b/drivers/media/platform/mediatek/jpeg/Makefile
> > index 69703db4b0a5..26e84852523e 100644
> > --- a/drivers/media/platform/mediatek/jpeg/Makefile
> > +++ b/drivers/media/platform/mediatek/jpeg/Makefile
> > @@ -1,9 +1,10 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> > obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o \
> > - mtk-jpeg-enc-hw.o
> > + mtk-jpeg-enc-hw.o \
> > + mtk-jpeg-dec-hw.o
> >
> > mtk_jpeg-y := mtk_jpeg_core.o \
> > - mtk_jpeg_dec_hw.o \
> > mtk_jpeg_dec_parse.o
> >
> > mtk-jpeg-enc-hw-y := mtk_jpeg_enc_hw.o
> > +mtk-jpeg-dec-hw-y := mtk_jpeg_dec_hw.o
> > diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> > b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> > index 2696651b457b..5683df94ac6a 100644
> > --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> > +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
> > @@ -1467,8 +1467,14 @@ static int mtk_jpeg_probe(struct
> > platform_device *pdev)
> > jpeg->variant = of_device_get_match_data(jpeg->dev);
> >
> > if (of_property_read_bool(pdev->dev.of_node,
> > - "mediatek,jpegenc-multi-core")) {
> > + "mediatek,jpegenc-multi-core"))
> > jpeg->is_jpgenc_multihw = true;
> > +
> > + if (of_property_read_bool(pdev->dev.of_node,
> > + "mediatek,jpegdec-multi-core"))
> > + jpeg->is_jpgdec_multihw = true;
> > +
> > + if (jpeg->is_jpgenc_multihw || jpeg->is_jpgdec_multihw) {
> > ret = devm_of_platform_populate(&pdev->dev);
> > if (ret) {
> > v4l2_err(&jpeg->v4l2_dev, "Master of platform
> > populate failed.");
> > @@ -1476,7 +1482,7 @@ static int mtk_jpeg_probe(struct
> > platform_device *pdev)
> > }
> > }
> >
> > - if (!jpeg->is_jpgenc_multihw) {
> > + if (!jpeg->is_jpgenc_multihw || jpeg->is_jpgdec_multihw) {
>
>
> That's never going to work. I'm sure that you were meaning:
>
> if (!jpeg->is_jpgenc_multihw && !jpeg->is_jpgdec_multihw) {
It is a wrong code. I will fix this check code.
Thanks.
>
>
>
> > INIT_DELAYED_WORK(&jpeg->job_timeout_work,
> > mtk_jpeg_job_timeout_work);
> >
> > @@ -1693,6 +1699,17 @@ static const struct mtk_jpeg_variant
> > mtk8195_jpegenc_drvdata = {
> > .cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
> > };
> >
> > +static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = {
> > + .formats = mtk_jpeg_dec_formats,
> > + .num_formats = MTK_JPEG_DEC_NUM_FORMATS,
> > + .qops = &mtk_jpeg_dec_qops,
> > + .m2m_ops = &mtk_jpeg_dec_m2m_ops,
> > + .dev_name = "mtk-jpeg-dec",
> > + .ioctl_ops = &mtk_jpeg_dec_ioctl_ops,
> > + .out_q_default_fourcc = V4L2_PIX_FMT_JPEG,
> > + .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
> > +};
> > +
> > #if defined(CONFIG_OF)
> > static const struct of_device_id mtk_jpeg_match[] = {
> > {
> > @@ -1711,6 +1728,10 @@ static const struct of_device_id
> > mtk_jpeg_match[] = {
> > .compatible = "mediatek,mt8195-jpgenc",
> > .data = &mtk8195_jpegenc_drvdata,
> > },
> > + {
> > + .compatible = "mediatek,mt8195-jpgdec",
> > + .data = &mtk8195_jpegdec_drvdata,
> > + },
> > {},
> > };
> >
> > diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> > b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> > index f8415b6b1618..29cd71fd713e 100644
> > --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> > +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
> > @@ -102,6 +102,13 @@ enum mtk_jpegenc_hw_id {
> > MTK_JPEGENC_HW_MAX,
> > };
> >
> > +enum mtk_jpegdec_hw_id {
> > + MTK_JPEGDEC_HW0,
> > + MTK_JPEGDEC_HW1,
> > + MTK_JPEGDEC_HW2,
> > + MTK_JPEGDEC_HW_MAX,
> > +};
> > +
> > /**
> > * struct mtk_vcodec_clk - Structure used to store vcodec clock
> > information
> > */
> > @@ -110,6 +117,14 @@ struct mtk_jpegenc_clk {
> > int clk_num;
> > };
> >
> > +/**
> > + * struct mtk_vcodec_clk - Structure used to store vcodec clock
> > information
>
> This is not struct mtk_vcodec_clk, but mtk_jpegdec_clk. Please fix.
OK, thanks.
>
> > + */
> > +struct mtk_jpegdec_clk {
> > + struct clk_bulk_data *clks;
> > + int clk_num;
> > +};
> > +
> > /**
> > * struct mtk_jpegenc_comp_dev - JPEG COREX abstraction
> > * @dev: JPEG device
> > @@ -139,6 +154,25 @@ struct mtk_jpegenc_comp_dev {
> > spinlock_t hw_lock;
> > };
> >
> > +/**
> > + * struct mtk_jpegdec_comp_dev - JPEG COREX abstraction
> > + * @dev: JPEG device
> > + * @plat_dev: platform device data
> > + * @reg_base: JPEG registers mapping
> > + * @master_dev: mtk_jpeg_dev device
> > + * @jdec_clk: mtk_jpegdec_clk
>
> Please fix indentation.
OK.
>
> > + * @jpegdec_irq: jpeg decode irq num
> > + */
> > +struct mtk_jpegdec_comp_dev {
> > + struct device *dev;
> > + struct platform_device *plat_dev;
> > + void __iomem *reg_base;
> > + struct mtk_jpeg_dev *master_dev;
> > + struct mtk_jpegdec_clk jdec_clk;
> > + int jpegdec_irq;
> > + int hw_id;
> > +};
> > +
> > /**
> > * struct mtk_jpeg_dev - JPEG IP abstraction
> > * @lock: the mutex protecting this structure
> > @@ -171,6 +205,10 @@ struct mtk_jpeg_dev {
> > bool is_jpgenc_multihw;
> > wait_queue_head_t enc_hw_wq;
> > atomic_t enchw_rdy;
> > +
> > + void __iomem *reg_decbase[MTK_JPEGDEC_HW_MAX];
> > + struct mtk_jpegdec_comp_dev *dec_hw_dev[MTK_JPEGDEC_HW_MAX];
> > + bool is_jpgdec_multihw;
> > };
> >
> > /**
> > diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> > b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> > index d2f25f43e852..fc98fe122874 100644
> > --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> > +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
> > @@ -5,9 +5,24 @@
> > * Rick Chang <rick.chang@mediatek.com>
> > */
> >
> > +#include <linux/clk.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/irq.h>
> > #include <linux/io.h>
> > #include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/slab.h>
> > +#include <media/media-device.h>
> > #include <media/videobuf2-core.h>
> > +#include <media/videobuf2-v4l2.h>
> > +#include <media/v4l2-mem2mem.h>
> > +#include <media/v4l2-dev.h>
> > +#include <media/v4l2-device.h>
> > +#include <media/v4l2-fh.h>
> > +#include <media/v4l2-event.h>
> >
> > #include "mtk_jpeg_core.h"
> > #include "mtk_jpeg_dec_hw.h"
> > @@ -24,6 +39,16 @@ enum mtk_jpeg_color {
> > MTK_JPEG_COLOR_400 = 0x00110000
> > };
> >
> > +#if defined(CONFIG_OF)
> > +static const struct of_device_id mtk_jpegdec_hw_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-jpgdec-hw",
> > + },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids);
> > +#endif
> > +
> > static inline int mtk_jpeg_verify_align(u32 val, int align, u32
> > reg)
> > {
> > if (val & (align - 1)) {
> > @@ -414,3 +439,146 @@ void mtk_jpeg_dec_set_config(void __iomem
> > *base,
> > mtk_jpeg_dec_set_pause_mcu_idx(base, config->total_mcu);
> > }
> > EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_config);
> > +
> > +static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
> > +{
> > + struct vb2_v4l2_buffer *src_buf, *dst_buf;
> > + struct mtk_jpeg_src_buf *jpeg_src_buf;
> > + enum vb2_buffer_state buf_state;
> > + struct mtk_jpeg_ctx *ctx;
> > + u32 dec_irq_ret;
> > + u32 irq_status;
> > + int i;
> > +
> > + struct mtk_jpegdec_comp_dev *jpeg = priv;
> > + struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev;
> > +
> > + irq_status = mtk_jpeg_dec_get_int_status(jpeg->reg_base);
> > + dec_irq_ret = mtk_jpeg_dec_enum_result(irq_status);
> > + if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
> > + mtk_jpeg_dec_reset(jpeg->reg_base);
> > + if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE)
> > + return IRQ_NONE;
> > +
> > + ctx = v4l2_m2m_get_curr_priv(master_jpeg->m2m_dev);
> > + if (!ctx) {
> > + dev_err(jpeg->dev, "Context is NULL\n");
> > + return IRQ_HANDLED;
> > + }
> > +
> > + src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
> > + dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
> > + v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
> > + jpeg_src_buf =
> > + container_of(src_buf, struct mtk_jpeg_src_buf, b);
> > +
> > + for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
> > + vb2_set_plane_payload(&dst_buf->vb2_buf, i,
> > + jpeg_src_buf-
> > >dec_param.comp_size[i]);
> > +
> > + buf_state = VB2_BUF_STATE_DONE;
> > +
> > + v4l2_m2m_buf_done(src_buf, buf_state);
> > + v4l2_m2m_buf_done(dst_buf, buf_state);
> > + v4l2_m2m_job_finish(master_jpeg->m2m_dev, ctx->fh.m2m_ctx);
> > + pm_runtime_put(ctx->jpeg->dev);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev
> > *dev)
> > +{
> > + struct platform_device *pdev = dev->plat_dev;
> > + int ret;
> > +
> > + dev->jpegdec_irq = platform_get_irq(pdev, 0);
> > + if (dev->jpegdec_irq < 0) {
> > + dev_err(&pdev->dev, "Failed to get irq resource");
> > + return dev->jpegdec_irq;
> > + }
> > +
> > + ret = devm_request_irq(&pdev->dev,
> > + dev->jpegdec_irq,
> > + mtk_jpegdec_hw_irq_handler,
> > + 0,
> > + pdev->name, dev);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Failed to devm_request_irq %d
> > (%d)",
> > + dev->jpegdec_irq, ret);
> > + return -ENOENT;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
> > +{
> > + struct mtk_jpegdec_clk *jpegdec_clk;
> > + struct mtk_jpeg_dev *master_dev;
> > + struct mtk_jpegdec_comp_dev *dev;
> > + int ret;
> > +
> > + struct device *decs = &pdev->dev;
> > +
> > + if (!decs->parent)
> > + return -EPROBE_DEFER;
> > +
> > + master_dev = dev_get_drvdata(decs->parent);
> > + if (!master_dev)
> > + return -EPROBE_DEFER;
> > +
> > + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
> > + if (!dev)
> > + return -ENOMEM;
> > +
> > + dev->plat_dev = pdev;
> > + dev->dev = &pdev->dev;
> > + jpegdec_clk = &dev->jdec_clk;
> > +
> > + jpegdec_clk->clk_num = devm_clk_bulk_get_all(&pdev->dev,
> > + &jpegdec_clk-
> > >clks);
> > + if (jpegdec_clk->clk_num < 0)
> > + return dev_err_probe(&pdev->dev,
> > + jpegdec_clk->clk_num,
> > + "Failed to get jpegdec clock
> > count.\n");
> > +
> > + dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(dev->reg_base))
> > + return PTR_ERR(dev->reg_base);
> > +
> > + ret = mtk_jpegdec_hw_init_irq(dev);
> > + if (ret)
> > + return dev_err_probe(&pdev->dev,
> > + ret,
> > + "Failed to register JPEGDEC irq
> > handler.\n");
> > +
> > + of_property_read_u32(decs->of_node, "hw_id",
> > + &dev->hw_id);
>
> ret = of_property_read_u32( ..... )
> if (ret)
> return ret;
>
> P.S.: Is it really important to get the hw_id from devicetree?
> is there any difference between HW0, HW1, HW2?
>
> Can we start decoding the first frame on HW1 or on HW2 instead of
> HW0?
> Does this hardware really need to work in HW0->1->2 specific
> sequence?
>
> Regards,
> Angelo
I will take Rob's suggestion to replace it by a new method.
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible
2022-07-05 13:00 ` AngeloGioacchino Del Regno
@ 2022-07-14 8:56 ` kyrie.wu
0 siblings, 0 replies; 15+ messages in thread
From: kyrie.wu @ 2022-07-14 8:56 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Irui Wang, Hans Verkuil,
Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Tzung-Bi Shih, nicolas.dufresne, wenst
Cc: Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng, srv_heupstream
On Tue, 2022-07-05 at 15:00 +0200, AngeloGioacchino Del Regno wrote:
> Il 27/06/22 04:55, Irui Wang ha scritto:
> > From: kyrie wu <kyrie.wu@mediatek.com>
> >
> > Add mediatek,mt8195-jpgdec compatible to binding document.
> >
> > Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
> > ---
> > .../media/mediatek,mt8195-jpegdec.yaml | 176
> > ++++++++++++++++++
> > 1 file changed, 176 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> > b/Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> > new file mode 100644
> > index 000000000000..8a255e8e2e09
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-
> > jpegdec.yaml
> > @@ -0,0 +1,176 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
>
> ...snip...
>
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/memory/mt8195-memory-port.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/clock/mt8195-clk.h>
> > + #include <dt-bindings/power/mt8195-power.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + jpgdec_master {
>
> Additionally to Rob's review, which I of course fully agree on, this
> example
> devicetree does *not* work on MT8195.
>
> [ 13.015716] mtk-jpegdec-hw 1a040000.jpgdec: Adding to iommu group
> 1
>
> [ 13.025383] mtk-jpegdec-hw 1a050000.jpgdec: Adding to iommu group
> 1
>
> [ 13.034814] mtk-jpegdec-hw 1b040000.jpgdec: Adding to iommu group
> 1
>
> [ 13.041672] mtk-jpeg soc:jpgdec_master: invalid resource
>
> [ 13.049758] mtk-jpeg: probe of soc:jpgdec_master failed with error
> -22
>
>
> Regards,
> Angelo
This error will be fixed.
Thanks.
>
> > + compatible = "mediatek,mt8195-jpgdec";
> > + mediatek,jpegdec-multi-core;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
> > + iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
> > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
> > + <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
> > + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
> > + <&iommu_vpp
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> > + <&iommu_vpp
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + jpgdec@1a040000 {
> > + compatible = "mediatek,mt8195-jpgdec-hw";
> > + reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
> > + hw_id = <0>;
> > + iommus = <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_WDMA0>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> > + <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> > + <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> > + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&vencsys CLK_VENC_JPGDEC>;
> > + clock-names = "jpgdec";
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VDEC0>;
> > + };
> > +
> > + jpgdec@1a050000 {
> > + compatible = "mediatek,mt8195-jpgdec-hw";
> > + reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
> > + hw_id = <1>;
> > + iommus = <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_WDMA0>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> > + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> > + <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> > + <&iommu_vdo
> > M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> > + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
> > + clock-names = "jpgdec";
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VDEC1>;
> > + };
> > +
> > + jpgdec@1b040000 {
> > + compatible = "mediatek,mt8195-jpgdec-hw";
> > + reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
> > + hw_id = <2>;
> > + iommus = <&iommu_vpp
> > M4U_PORT_L20_JPGDEC_WDMA0>,
> > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
> > + <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
> > + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
> > + <&iommu_vpp
> > M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
> > + <&iommu_vpp
> > M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
> > + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > + clocks = <&vencsys_core1
> > CLK_VENC_CORE1_JPGDEC>;
> > + clock-names = "jpgdec";
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VDEC2>;
> > + };
> > + };
> > + };
>
>
>
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^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2022-07-14 9:59 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-27 2:55 [V4,0/8] Support multi-hardware jpeg decoder for MT8195 Irui Wang
2022-06-27 2:55 ` [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec compatible Irui Wang
2022-07-01 15:29 ` Rob Herring
2022-07-14 8:42 ` kyrie.wu
2022-07-05 13:00 ` AngeloGioacchino Del Regno
2022-07-14 8:56 ` kyrie.wu
2022-06-27 2:55 ` [V4,2/8] media: mtk-jpegdec: export jpeg decoder functions Irui Wang
2022-06-27 2:55 ` [PV4,3/8] media: mtk-jpegdec: manage jpegdec multi-hardware Irui Wang
2022-07-05 13:36 ` AngeloGioacchino Del Regno
2022-07-14 8:55 ` kyrie.wu
2022-06-27 2:55 ` [V4,4/8] media: mtk-jpegdec: add jpegdec timeout func interface Irui Wang
2022-06-27 2:55 ` [V4,5/8] media: mtk-jpegdec: add jpeg decode worker interface Irui Wang
2022-06-27 2:55 ` [V4,6/8] media: mtk-jpegdec: add output pic reorder interface Irui Wang
2022-06-27 2:55 ` [V4,7/8] media: mtk-jpegdec: refactor jpegdec func interface Irui Wang
2022-06-27 2:55 ` [V4,8/8] mtk-jpegdec: add stop cmd interface for jpgdec Irui Wang
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