From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: robh+dt@kernel.org
Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org,
chaotian.jing@mediatek.com, ulf.hansson@linaro.org,
matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com,
hsinyi@chromium.org, nfraprado@collabora.com,
allen-kh.cheng@mediatek.com, fparent@baylibre.com,
sam.shih@mediatek.com, sean.wang@mediatek.com,
long.cheng@mediatek.com, wenbin.mei@mediatek.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org,
~postmarketos/upstreaming@lists.sr.ht
Subject: [PATCH 5/8] arm64: dts: mediatek: mt6795: Add support for APDMA and wire up UART DMAs
Date: Fri, 29 Jul 2022 12:44:37 +0200 [thread overview]
Message-ID: <20220729104441.39177-6-angelogioacchino.delregno@collabora.com> (raw)
In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com>
This SoC has a DMA controller with tx/rx channels for all of the
UART controller IPs: add the apdma node and wire up the DMAs on
all controllers.
When one of the UART controllers is used as a serial console,
the DMA will be automatically ignored.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 34 ++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 559fec1ee123..687e0ee63503 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -314,6 +314,8 @@ uart0: serial@11002000 {
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
clock-names = "baud", "bus";
+ dmas = <&apdma 0>, <&apdma 1>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -324,9 +326,37 @@ uart1: serial@11003000 {
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
clock-names = "baud", "bus";
+ dmas = <&apdma 2>, <&apdma 3>;
+ dma-names = "tx", "rx";
status = "disabled";
};
+ apdma: dma-controller@11000380 {
+ compatible = "mediatek,mt6795-uart-dma",
+ "mediatek,mt6577-uart-dma";
+ reg = <0 0x11000380 0 0x60>,
+ <0 0x11000400 0 0x60>,
+ <0 0x11000480 0 0x60>,
+ <0 0x11000500 0 0x60>,
+ <0 0x11000580 0 0x60>,
+ <0 0x11000600 0 0x60>,
+ <0 0x11000680 0 0x60>,
+ <0 0x11000700 0 0x60>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
+ dma-requests = <8>;
+ clocks = <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "apdma";
+ mediatek,dma-33bits;
+ #dma-cells = <1>;
+ };
+
uart2: serial@11004000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
@@ -334,6 +364,8 @@ uart2: serial@11004000 {
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
clock-names = "baud", "bus";
+ dmas = <&apdma 4>, <&apdma 5>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -344,6 +376,8 @@ uart3: serial@11005000 {
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
clock-names = "baud", "bus";
+ dmas = <&apdma 6>, <&apdma 7>;
+ dma-names = "tx", "rx";
status = "disabled";
};
};
--
2.35.1
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next prev parent reply other threads:[~2022-07-29 10:47 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-29 10:44 [PATCH 0/8] MT6795 Devicetrees and Sony Xperia M5 AngeloGioacchino Del Regno
2022-07-29 10:44 ` [PATCH 1/8] dt-bindings: dma: mediatek,uart-dma: Add binding for MT6795 SoC AngeloGioacchino Del Regno
2022-08-02 7:34 ` Krzysztof Kozlowski
2022-09-04 17:26 ` Vinod Koul
2022-07-29 10:44 ` [PATCH 2/8] dt-bindings: mmc: Add compatible for MT6795 Helio X10 SoC AngeloGioacchino Del Regno
2022-07-29 23:05 ` Rob Herring
2022-08-15 18:28 ` Ulf Hansson
2022-07-29 10:44 ` [PATCH 3/8] arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets AngeloGioacchino Del Regno
2022-07-29 10:44 ` [PATCH 4/8] arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg AngeloGioacchino Del Regno
2022-07-29 10:44 ` AngeloGioacchino Del Regno [this message]
2022-07-29 10:44 ` [PATCH 6/8] arm64: dts: mediatek: mt6795: Add support for eMMC/SD/SDIO controllers AngeloGioacchino Del Regno
2022-07-29 10:44 ` [PATCH 7/7] arm64: dts: mediatek: Add support for MT6795 Sony Xperia M5 smartphone AngeloGioacchino Del Regno
2022-07-29 12:00 ` Konrad Dybcio
2022-10-27 9:28 ` AngeloGioacchino Del Regno
2022-10-27 9:40 ` Konrad Dybcio
2022-10-27 10:01 ` AngeloGioacchino Del Regno
2022-07-29 10:44 ` [PATCH 7/8] dt-bindings: arm: mediatek: Add compatible for MT6795 Sony Xperia M5 AngeloGioacchino Del Regno
2022-07-29 23:05 ` Rob Herring
2022-07-29 10:44 ` [PATCH 8/8] arm64: dts: mediatek: Add support for MT6795 Sony Xperia M5 smartphone AngeloGioacchino Del Regno
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