* [PATCH v4 0/4] MT8188 SMI SUPPORT @ 2022-08-01 2:18 Chengci.Xu 2022-08-01 2:18 ` [PATCH v4 1/4] dt-bindings: memory: mediatek: Add mt8188 smi binding Chengci.Xu ` (3 more replies) 0 siblings, 4 replies; 9+ messages in thread From: Chengci.Xu @ 2022-08-01 2:18 UTC (permalink / raw) To: Yong Wu, Krzysztof Kozlowski, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, yi.kuo, anthony.huang, wendy-st.lin, Chengci.Xu This patchset adds MT8188 SMI support. MT8188, similar to mt8195, there are two SMI-common HW, one is for VDO(video output), the other is for VPP(video processing pipe). They connect with different SMI-larbs, then some setting(bus_sel) is different. The connection between SMI and MM IOMMU could be something like this: IOMMU(VDO) IOMMU(VPP) | | SMI_COMMON_VDO SMI_COMMON_VPP ---------------- ---------------- | | ... | | ... larb0 larb2 ... larb1 larb3 ... Another change is that the register about enable/disable iommu is in security world. We add some SMC command to set it. And we add a return value for configure port function because SMC call may fail. changes since v4: - base on tag: next-20220728. - new patch[2/4] to add return value for all config port function. - rename enum IOMMU_ATF_CMD to a lower case: iommu_atf_cmd. - rename MTK_SMI_FLAG_SEC_REG to MTK_SMI_FLAG_CFG_PORT_SEC_CTL. - rename IOMMU_ATF_CMD_COUNT to IOMMU_ATF_CMD_MAX. - add some comment for why still need write SMI_LARB_NONSEC_CON. - return an error(-EINVAL) when enable iommu failed by SMC call. - put enum iommu_atf_cmd inside the macro CONFIG_MTK_SMI. changes since v3: - base on tag: next-20220726. - No code change just remove the change-id in patch [2/3]. changes since v2: - base on tag: next-20220722. - Move some included header to the source file that use them. changes since v1: - base on tag: next-20220720. - adds MT8188 SMI support. Chengci.Xu (4): dt-bindings: memory: mediatek: Add mt8188 smi binding memory: mtk-smi: Add return value for configure port function memory: mtk-smi: Add enable IOMMU SMC command for MM master memory: mtk-smi: mt8188: Add SMI Support .../mediatek,smi-common.yaml | 4 +- .../memory-controllers/mediatek,smi-larb.yaml | 3 + drivers/memory/mtk-smi.c | 108 +++++++++++++++++- include/linux/soc/mediatek/mtk_sip_svc.h | 3 + include/soc/mediatek/smi.h | 5 + 5 files changed, 116 insertions(+), 7 deletions(-) -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 1/4] dt-bindings: memory: mediatek: Add mt8188 smi binding 2022-08-01 2:18 [PATCH v4 0/4] MT8188 SMI SUPPORT Chengci.Xu @ 2022-08-01 2:18 ` Chengci.Xu 2022-08-01 2:18 ` [PATCH v4 2/4] memory: mtk-smi: Add return value for configure port function Chengci.Xu ` (2 subsequent siblings) 3 siblings, 0 replies; 9+ messages in thread From: Chengci.Xu @ 2022-08-01 2:18 UTC (permalink / raw) To: Yong Wu, Krzysztof Kozlowski, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, yi.kuo, anthony.huang, wendy-st.lin, Chengci.Xu, AngeloGioacchino Del Regno Add mt8188 smi supporting in the bindings. In mt8188, there are two smi-common HW, one is for vdo(video output), the other is for vpp(video processing pipe). They connect with different smi-larbs, then some setting(bus_sel) is different. Differentiate them with the compatible string. Something like this: IOMMU(VDO) IOMMU(VPP) | | SMI_COMMON_VDO SMI_COMMON_VPP ---------------- ---------------- | | ... | | ... larb0 larb2 ... larb1 larb3 ... Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Yong Wu <yong.wu@mediatek.com> --- .../bindings/memory-controllers/mediatek,smi-common.yaml | 4 +++- .../bindings/memory-controllers/mediatek,smi-larb.yaml | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index 71bc5cefb49c..70bba66c7551 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -16,7 +16,7 @@ description: | MediaTek SMI have two generations of HW architecture, here is the list which generation the SoCs use: generation 1: mt2701 and mt7623. - generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8192 and mt8195. + generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195. There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. But @@ -37,6 +37,8 @@ properties: - mediatek,mt8173-smi-common - mediatek,mt8183-smi-common - mediatek,mt8186-smi-common + - mediatek,mt8188-smi-common-vdo + - mediatek,mt8188-smi-common-vpp - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 59dcd163668f..5f4ac3609887 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt8173-smi-larb - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb + - mediatek,mt8188-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb @@ -78,6 +79,7 @@ allOf: enum: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb + - mediatek,mt8188-smi-larb - mediatek,mt8195-smi-larb then: @@ -111,6 +113,7 @@ allOf: - mediatek,mt2712-smi-larb - mediatek,mt6779-smi-larb - mediatek,mt8186-smi-larb + - mediatek,mt8188-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 2/4] memory: mtk-smi: Add return value for configure port function 2022-08-01 2:18 [PATCH v4 0/4] MT8188 SMI SUPPORT Chengci.Xu 2022-08-01 2:18 ` [PATCH v4 1/4] dt-bindings: memory: mediatek: Add mt8188 smi binding Chengci.Xu @ 2022-08-01 2:18 ` Chengci.Xu 2022-08-09 5:58 ` Yong Wu 2022-08-01 2:18 ` [PATCH v4 3/4] memory: mtk-smi: Add enable IOMMU SMC command for MM master Chengci.Xu 2022-08-01 2:18 ` [PATCH v4 4/4] memory: mtk-smi: mt8188: Add SMI Support Chengci.Xu 3 siblings, 1 reply; 9+ messages in thread From: Chengci.Xu @ 2022-08-01 2:18 UTC (permalink / raw) To: Yong Wu, Krzysztof Kozlowski, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, yi.kuo, anthony.huang, wendy-st.lin, Chengci.Xu In MT8188, the register to enable/disable IOMMU can only be configured in secure world by SMC call. We should add a return value for configure port function for preparation because SMC call may return an error result. Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com> --- drivers/memory/mtk-smi.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index d7cb7ead2ac7..08c1668d47bf 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -127,7 +127,7 @@ struct mtk_smi_common_plat { struct mtk_smi_larb_gen { int port_in_larb[MTK_LARB_NR_MAX + 1]; - void (*config_port)(struct device *dev); + int (*config_port)(struct device *dev); unsigned int larb_direct_to_common_mask; unsigned int flags_general; const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; @@ -185,7 +185,7 @@ static const struct component_ops mtk_smi_larb_component_ops = { .unbind = mtk_smi_larb_unbind, }; -static void mtk_smi_larb_config_port_gen1(struct device *dev) +static int mtk_smi_larb_config_port_gen1(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; @@ -214,23 +214,26 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) common->smi_ao_base + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); } + return 0; } -static void mtk_smi_larb_config_port_mt8167(struct device *dev) +static int mtk_smi_larb_config_port_mt8167(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); + return 0; } -static void mtk_smi_larb_config_port_mt8173(struct device *dev) +static int mtk_smi_larb_config_port_mt8173(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); + return 0; } -static void mtk_smi_larb_config_port_gen2_general(struct device *dev) +static int mtk_smi_larb_config_port_gen2_general(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); u32 reg, flags_general = larb->larb_gen->flags_general; @@ -238,7 +241,7 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) int i; if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) - return; + return 0; if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); @@ -259,6 +262,7 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) reg |= BANK_SEL(larb->bank[i]); writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); } + return 0; } static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { @@ -511,7 +515,9 @@ static int __maybe_unused mtk_smi_larb_resume(struct device *dev) mtk_smi_larb_sleep_ctrl_disable(larb); /* Configure the basic setting for this larb */ - larb_gen->config_port(dev); + ret = larb_gen->config_port(dev); + if (ret) + return ret; return 0; } -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v4 2/4] memory: mtk-smi: Add return value for configure port function 2022-08-01 2:18 ` [PATCH v4 2/4] memory: mtk-smi: Add return value for configure port function Chengci.Xu @ 2022-08-09 5:58 ` Yong Wu 0 siblings, 0 replies; 9+ messages in thread From: Yong Wu @ 2022-08-09 5:58 UTC (permalink / raw) To: Chengci.Xu, Krzysztof Kozlowski, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, yi.kuo, anthony.huang, wendy-st.lin On Mon, 2022-08-01 at 10:18 +0800, Chengci.Xu wrote: > In MT8188, the register to enable/disable IOMMU can only be > configured > in secure world by SMC call. We should add a return value for > configure > port function for preparation because SMC call may return an error > result. > > Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com> > --- > drivers/memory/mtk-smi.c | 20 +++++++++++++------- > 1 file changed, 13 insertions(+), 7 deletions(-) > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > index d7cb7ead2ac7..08c1668d47bf 100644 > --- a/drivers/memory/mtk-smi.c > +++ b/drivers/memory/mtk-smi.c > @@ -127,7 +127,7 @@ struct mtk_smi_common_plat { > > struct mtk_smi_larb_gen { > int port_in_larb[MTK_LARB_NR_MAX + 1]; > - void (*config_port)(struct device *dev); > + int (*config_port)(struct device > *dev); > unsigned int larb_direct_to_common_mask; > unsigned int flags_general; > const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; > @@ -185,7 +185,7 @@ static const struct component_ops > mtk_smi_larb_component_ops = { > .unbind = mtk_smi_larb_unbind, > }; > > -static void mtk_smi_larb_config_port_gen1(struct device *dev) > +static int mtk_smi_larb_config_port_gen1(struct device *dev) > { > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; > @@ -214,23 +214,26 @@ static void > mtk_smi_larb_config_port_gen1(struct device *dev) > common->smi_ao_base > + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); > } > + return 0; > } > > -static void mtk_smi_larb_config_port_mt8167(struct device *dev) > +static int mtk_smi_larb_config_port_mt8167(struct device *dev) > { > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); > + return 0; > } > > -static void mtk_smi_larb_config_port_mt8173(struct device *dev) > +static int mtk_smi_larb_config_port_mt8173(struct device *dev) > { > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); > + return 0; > } > > -static void mtk_smi_larb_config_port_gen2_general(struct device > *dev) > +static int mtk_smi_larb_config_port_gen2_general(struct device *dev) > { > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > u32 reg, flags_general = larb->larb_gen->flags_general; > @@ -238,7 +241,7 @@ static void > mtk_smi_larb_config_port_gen2_general(struct device *dev) > int i; > > if (BIT(larb->larbid) & larb->larb_gen- > >larb_direct_to_common_mask) > - return; > + return 0; > > if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { > reg = readl_relaxed(larb->base + > SMI_LARB_CMD_THRT_CON); > @@ -259,6 +262,7 @@ static void > mtk_smi_larb_config_port_gen2_general(struct device *dev) > reg |= BANK_SEL(larb->bank[i]); > writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); > } > + return 0; > } > > static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { > @@ -511,7 +515,9 @@ static int __maybe_unused > mtk_smi_larb_resume(struct device *dev) > mtk_smi_larb_sleep_ctrl_disable(larb); > > /* Configure the basic setting for this larb */ > - larb_gen->config_port(dev); > + ret = larb_gen->config_port(dev); > + if (ret) > + return ret; return larb_gen->config_port(dev); After this, Reviewed-by: Yong Wu <yong.wu@mediatek.com> > > return 0; > } _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 3/4] memory: mtk-smi: Add enable IOMMU SMC command for MM master 2022-08-01 2:18 [PATCH v4 0/4] MT8188 SMI SUPPORT Chengci.Xu 2022-08-01 2:18 ` [PATCH v4 1/4] dt-bindings: memory: mediatek: Add mt8188 smi binding Chengci.Xu 2022-08-01 2:18 ` [PATCH v4 2/4] memory: mtk-smi: Add return value for configure port function Chengci.Xu @ 2022-08-01 2:18 ` Chengci.Xu 2022-08-09 5:58 ` Yong Wu 2022-08-01 2:18 ` [PATCH v4 4/4] memory: mtk-smi: mt8188: Add SMI Support Chengci.Xu 3 siblings, 1 reply; 9+ messages in thread From: Chengci.Xu @ 2022-08-01 2:18 UTC (permalink / raw) To: Yong Wu, Krzysztof Kozlowski, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, yi.kuo, anthony.huang, wendy-st.lin, Chengci.Xu For concerns about security, the register to enable/disable IOMMU of SMI LARB should only be configured in secure world. Thus, we add some SMC command for multimedia master to enable/disable MM IOMMU in ATF by setting the register of SMI LARB. This function is prepared for MT8188. Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com> --- drivers/memory/mtk-smi.c | 19 +++++++++++++++++++ include/linux/soc/mediatek/mtk_sip_svc.h | 3 +++ include/soc/mediatek/smi.h | 5 +++++ 3 files changed, 27 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index 08c1668d47bf..28e1123f9d76 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -3,6 +3,7 @@ * Copyright (c) 2015-2016 MediaTek Inc. * Author: Yong Wu <yong.wu@mediatek.com> */ +#include <linux/arm-smccc.h> #include <linux/clk.h> #include <linux/component.h> #include <linux/device.h> @@ -14,6 +15,7 @@ #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/soc/mediatek/mtk_sip_svc.h> #include <soc/mediatek/smi.h> #include <dt-bindings/memory/mt2701-larb-port.h> #include <dt-bindings/memory/mtk-memory-port.h> @@ -89,6 +91,7 @@ #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) #define MTK_SMI_FLAG_SW_FLAG BIT(1) #define MTK_SMI_FLAG_SLEEP_CTL BIT(2) +#define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3) #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) struct mtk_smi_reg_pair { @@ -238,6 +241,7 @@ static int mtk_smi_larb_config_port_gen2_general(struct device *dev) struct mtk_smi_larb *larb = dev_get_drvdata(dev); u32 reg, flags_general = larb->larb_gen->flags_general; const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL; + struct arm_smccc_res res; int i; if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) @@ -262,6 +266,21 @@ static int mtk_smi_larb_config_port_gen2_general(struct device *dev) reg |= BANK_SEL(larb->bank[i]); writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); } + + /* + * We still need to write above NONSEC_CON register for bank selection + * even if enabling IOMMU is failed by SMC call. Otherwise, all master + * will be configured to bank 0 with a state of IOMMU enable due to the + * HW default value of register. + */ + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_CFG_PORT_SEC_CTL)) { + arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, IOMMU_ATF_CMD_CONFIG_SMI_LARB, + larb->larbid, (u32)(*larb->mmu), 0, 0, 0, 0, &res); + if (res.a0 != 0) { + dev_err(dev, "Enable iommu fail, ret %ld\n", res.a0); + return -EINVAL; + } + } return 0; } diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h index 082398e0cfb1..0761128b4354 100644 --- a/include/linux/soc/mediatek/mtk_sip_svc.h +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -22,4 +22,7 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ ARM_SMCCC_OWNER_SIP, fn_id) +/* IOMMU related SMC call */ +#define MTK_SIP_KERNEL_IOMMU_CONTROL MTK_SIP_SMC_CMD(0x514) + #endif diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h index 11f7d6b59642..dfd8efca5e60 100644 --- a/include/soc/mediatek/smi.h +++ b/include/soc/mediatek/smi.h @@ -11,6 +11,11 @@ #if IS_ENABLED(CONFIG_MTK_SMI) +enum iommu_atf_cmd { + IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to en/disable iommu */ + IOMMU_ATF_CMD_MAX, +}; + #define MTK_SMI_MMU_EN(port) BIT(port) struct mtk_smi_larb_iommu { -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v4 3/4] memory: mtk-smi: Add enable IOMMU SMC command for MM master 2022-08-01 2:18 ` [PATCH v4 3/4] memory: mtk-smi: Add enable IOMMU SMC command for MM master Chengci.Xu @ 2022-08-09 5:58 ` Yong Wu 2022-08-17 12:43 ` Chengci.Xu 0 siblings, 1 reply; 9+ messages in thread From: Yong Wu @ 2022-08-09 5:58 UTC (permalink / raw) To: Chengci.Xu, Krzysztof Kozlowski, Matthias Brugger Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, yi.kuo, anthony.huang, wendy-st.lin, Rob Herring On Mon, 2022-08-01 at 10:18 +0800, Chengci.Xu wrote: > For concerns about security, the register to enable/disable IOMMU of > SMI LARB should only be configured in secure world. Thus, we add some > SMC command for multimedia master to enable/disable MM IOMMU in ATF > by > setting the register of SMI LARB. This function is prepared for > MT8188. > > Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com> > --- > drivers/memory/mtk-smi.c | 19 +++++++++++++++++++ > include/linux/soc/mediatek/mtk_sip_svc.h | 3 +++ > include/soc/mediatek/smi.h | 5 +++++ > 3 files changed, 27 insertions(+) > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > index 08c1668d47bf..28e1123f9d76 100644 > --- a/drivers/memory/mtk-smi.c > +++ b/drivers/memory/mtk-smi.c > @@ -3,6 +3,7 @@ > * Copyright (c) 2015-2016 MediaTek Inc. > * Author: Yong Wu <yong.wu@mediatek.com> > */ > +#include <linux/arm-smccc.h> > #include <linux/clk.h> > #include <linux/component.h> > #include <linux/device.h> > @@ -14,6 +15,7 @@ > #include <linux/of_platform.h> > #include <linux/platform_device.h> > #include <linux/pm_runtime.h> > +#include <linux/soc/mediatek/mtk_sip_svc.h> > #include <soc/mediatek/smi.h> > #include <dt-bindings/memory/mt2701-larb-port.h> > #include <dt-bindings/memory/mtk-memory-port.h> > @@ -89,6 +91,7 @@ > #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) > #define MTK_SMI_FLAG_SW_FLAG BIT(1) > #define MTK_SMI_FLAG_SLEEP_CTL BIT(2) > +#define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3) > #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) > > struct mtk_smi_reg_pair { > @@ -238,6 +241,7 @@ static int > mtk_smi_larb_config_port_gen2_general(struct device *dev) > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > u32 reg, flags_general = larb->larb_gen->flags_general; > const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen- > >ostd[larb->larbid] : NULL; > + struct arm_smccc_res res; > int i; > > if (BIT(larb->larbid) & larb->larb_gen- > >larb_direct_to_common_mask) > @@ -262,6 +266,21 @@ static int > mtk_smi_larb_config_port_gen2_general(struct device *dev) > reg |= BANK_SEL(larb->bank[i]); > writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); > } > + > + /* > + * We still need to write above NONSEC_CON register for bank > selection > + * even if enabling IOMMU is failed by SMC call. Otherwise, all > master > + * will be configured to bank 0 with a state of IOMMU enable > due to the > + * HW default value of register. I don't understand this. Does bankX(X!=0) make sense if SMC fail? I guess the below segment should be before SMI_LARB_NONSEC_CON. It means we shouldn't touch bank_sel while SMC fail. Just add a comment like: /* When mmu_en bits are in security world, the bank_sel still is in the LARB_NONSEC_CON below. and the mmu_en of LARB_NONSEC_CON have no effect in this case. */ > + */ > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_CFG_PORT_SEC_CTL)) > { > + arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, > IOMMU_ATF_CMD_CONFIG_SMI_LARB, > + larb->larbid, (u32)(*larb->mmu), 0, 0, 0, The type of mmu is "u32", no need the "(u32)". > 0, &res); > + if (res.a0 != 0) { > + dev_err(dev, "Enable iommu fail, ret %ld\n", > res.a0); > + return -EINVAL; > + } > + } > return 0; > } > > diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h > b/include/linux/soc/mediatek/mtk_sip_svc.h > index 082398e0cfb1..0761128b4354 100644 > --- a/include/linux/soc/mediatek/mtk_sip_svc.h > +++ b/include/linux/soc/mediatek/mtk_sip_svc.h > @@ -22,4 +22,7 @@ > ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, > \ > ARM_SMCCC_OWNER_SIP, fn_id) > > +/* IOMMU related SMC call */ > +#define MTK_SIP_KERNEL_IOMMU_CONTROL MTK_SIP_SMC_CMD(0x514) > + > #endif > diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h > index 11f7d6b59642..dfd8efca5e60 100644 > --- a/include/soc/mediatek/smi.h > +++ b/include/soc/mediatek/smi.h > @@ -11,6 +11,11 @@ > > #if IS_ENABLED(CONFIG_MTK_SMI) > > +enum iommu_atf_cmd { > + IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to > en/disable iommu */ > + IOMMU_ATF_CMD_MAX, > +}; > + > #define MTK_SMI_MMU_EN(port) BIT(port) > > struct mtk_smi_larb_iommu { _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4 3/4] memory: mtk-smi: Add enable IOMMU SMC command for MM master 2022-08-09 5:58 ` Yong Wu @ 2022-08-17 12:43 ` Chengci.Xu 0 siblings, 0 replies; 9+ messages in thread From: Chengci.Xu @ 2022-08-17 12:43 UTC (permalink / raw) To: Yong Wu, Krzysztof Kozlowski, Matthias Brugger Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, yi.kuo, anthony.huang, wendy-st.lin, Rob Herring On Tue, 2022-08-09 at 13:58 +0800, Yong Wu wrote: > On Mon, 2022-08-01 at 10:18 +0800, Chengci.Xu wrote: > > For concerns about security, the register to enable/disable IOMMU > > of > > SMI LARB should only be configured in secure world. Thus, we add > > some > > SMC command for multimedia master to enable/disable MM IOMMU in ATF > > by > > setting the register of SMI LARB. This function is prepared for > > MT8188. > > > > Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com> > > --- > > drivers/memory/mtk-smi.c | 19 +++++++++++++++++++ > > include/linux/soc/mediatek/mtk_sip_svc.h | 3 +++ > > include/soc/mediatek/smi.h | 5 +++++ > > 3 files changed, 27 insertions(+) > > > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c > > index 08c1668d47bf..28e1123f9d76 100644 > > --- a/drivers/memory/mtk-smi.c > > +++ b/drivers/memory/mtk-smi.c > > @@ -3,6 +3,7 @@ > > * Copyright (c) 2015-2016 MediaTek Inc. > > * Author: Yong Wu <yong.wu@mediatek.com> > > */ > > +#include <linux/arm-smccc.h> > > #include <linux/clk.h> > > #include <linux/component.h> > > #include <linux/device.h> > > @@ -14,6 +15,7 @@ > > #include <linux/of_platform.h> > > #include <linux/platform_device.h> > > #include <linux/pm_runtime.h> > > +#include <linux/soc/mediatek/mtk_sip_svc.h> > > #include <soc/mediatek/smi.h> > > #include <dt-bindings/memory/mt2701-larb-port.h> > > #include <dt-bindings/memory/mtk-memory-port.h> > > @@ -89,6 +91,7 @@ > > #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) > > #define MTK_SMI_FLAG_SW_FLAG BIT(1) > > #define MTK_SMI_FLAG_SLEEP_CTL BIT(2) > > +#define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3) > > #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) > > > > struct mtk_smi_reg_pair { > > @@ -238,6 +241,7 @@ static int > > mtk_smi_larb_config_port_gen2_general(struct device *dev) > > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > u32 reg, flags_general = larb->larb_gen->flags_general; > > const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen- > > > ostd[larb->larbid] : NULL; > > > > + struct arm_smccc_res res; > > int i; > > > > if (BIT(larb->larbid) & larb->larb_gen- > > > larb_direct_to_common_mask) > > > > @@ -262,6 +266,21 @@ static int > > mtk_smi_larb_config_port_gen2_general(struct device *dev) > > reg |= BANK_SEL(larb->bank[i]); > > writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); > > } > > + > > + /* > > + * We still need to write above NONSEC_CON register for bank > > selection > > + * even if enabling IOMMU is failed by SMC call. Otherwise, all > > master > > + * will be configured to bank 0 with a state of IOMMU enable > > due to the > > + * HW default value of register. > > I don't understand this. Does bankX(X!=0) make sense if SMC fail? > > I guess the below segment should be before SMI_LARB_NONSEC_CON. It > means we shouldn't touch bank_sel while SMC fail. If SMC call failed, we do have no need to configure bank_sel. All we can do is stop following step and report an error. So it is a good choice to put the code about MTK_SMI_FLAG_CFG_PORT_SEC_CTL in front of SMI_LARB_NONSEC_CON. I will do it in next version. > > Just add a comment like: > /* When mmu_en bits are in security world, the bank_sel still is in > the > LARB_NONSEC_CON below. and the mmu_en of LARB_NONSEC_CON have no > effect > in this case. */ OK, got it, thanks. > > > + */ > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_CFG_PORT_SEC_CTL)) > > { > > + arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, > > IOMMU_ATF_CMD_CONFIG_SMI_LARB, > > + larb->larbid, (u32)(*larb->mmu), 0, 0, 0, > > The type of mmu is "u32", no need the "(u32)". > > > 0, &res); > > + if (res.a0 != 0) { > > + dev_err(dev, "Enable iommu fail, ret %ld\n", > > res.a0); > > + return -EINVAL; > > + } > > + } > > return 0; > > } > > > > diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h > > b/include/linux/soc/mediatek/mtk_sip_svc.h > > index 082398e0cfb1..0761128b4354 100644 > > --- a/include/linux/soc/mediatek/mtk_sip_svc.h > > +++ b/include/linux/soc/mediatek/mtk_sip_svc.h > > @@ -22,4 +22,7 @@ > > ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, > > \ > > ARM_SMCCC_OWNER_SIP, fn_id) > > > > +/* IOMMU related SMC call */ > > +#define MTK_SIP_KERNEL_IOMMU_CONTROL MTK_SIP_SMC_CMD(0x514) > > + > > #endif > > diff --git a/include/soc/mediatek/smi.h > > b/include/soc/mediatek/smi.h > > index 11f7d6b59642..dfd8efca5e60 100644 > > --- a/include/soc/mediatek/smi.h > > +++ b/include/soc/mediatek/smi.h > > @@ -11,6 +11,11 @@ > > > > #if IS_ENABLED(CONFIG_MTK_SMI) > > > > +enum iommu_atf_cmd { > > + IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to > > en/disable iommu */ > > + IOMMU_ATF_CMD_MAX, > > +}; > > + > > #define MTK_SMI_MMU_EN(port) BIT(port) > > > > struct mtk_smi_larb_iommu { > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 4/4] memory: mtk-smi: mt8188: Add SMI Support 2022-08-01 2:18 [PATCH v4 0/4] MT8188 SMI SUPPORT Chengci.Xu ` (2 preceding siblings ...) 2022-08-01 2:18 ` [PATCH v4 3/4] memory: mtk-smi: Add enable IOMMU SMC command for MM master Chengci.Xu @ 2022-08-01 2:18 ` Chengci.Xu 2022-08-09 5:58 ` Yong Wu 3 siblings, 1 reply; 9+ messages in thread From: Chengci.Xu @ 2022-08-01 2:18 UTC (permalink / raw) To: Yong Wu, Krzysztof Kozlowski, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, yi.kuo, anthony.huang, wendy-st.lin, Chengci.Xu, AngeloGioacchino Del Regno Add mt8188 smi common & larb support Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/memory/mtk-smi.c | 71 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index 28e1123f9d76..e7d9769a122a 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -284,6 +284,55 @@ static int mtk_smi_larb_config_port_gen2_general(struct device *dev) return 0; } +static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = { + [0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,}, + [1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,}, + [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, + [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, + [4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,}, + [5] = {0x02, 0x01, 0x04, 0x02, 0x06, 0x01, 0x06, 0x0a,}, + [6] = {0x06, 0x01, 0x06, 0x0a,}, + [7] = {0x0c, 0x0c, 0x12,}, + [8] = {0x0c, 0x01, 0x0a, 0x05, 0x02, 0x03, 0x01, 0x01, 0x14, 0x14, + 0x0a, 0x14, 0x1e, 0x01, 0x0c, 0x0a, 0x05, 0x02, 0x02, 0x05, + 0x03, 0x01, 0x1e, 0x01, 0x05,}, + [9] = {0x1e, 0x01, 0x0a, 0x0a, 0x01, 0x01, 0x03, 0x1e, 0x1e, 0x10, + 0x07, 0x01, 0x0a, 0x06, 0x03, 0x03, 0x0e, 0x01, 0x04, 0x28,}, + [10] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c, + 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14, + 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,}, + [11] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c, + 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14, + 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,}, + [12] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c, + 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14, + 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,}, + [13] = {0x07, 0x02, 0x04, 0x02, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, + 0x07, 0x02, 0x04, 0x02, 0x05, 0x05,}, + [14] = {0x02, 0x02, 0x0c, 0x0c, 0x0c, 0x0c, 0x01, 0x01, 0x02, 0x02, + 0x02, 0x02, 0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x01, 0x01,}, + [15] = {0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x0c, 0x0c, + 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02, + 0x0c, 0x01, 0x01,}, + [16] = {0x28, 0x28, 0x03, 0x01, 0x01, 0x03, 0x14, 0x14, 0x0a, 0x0d, + 0x03, 0x05, 0x0e, 0x01, 0x01, 0x05, 0x06, 0x0d, 0x01,}, + [17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, + 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,}, + [18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, + 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,}, + [19] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, + [20] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, + [21] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, + 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, + 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, + [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, + 0x01,}, + [23] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x18, 0x01, 0x01,}, + [24] = {0x12, 0x06, 0x12, 0x06,}, + [25] = {0x01}, +}; + static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ @@ -370,6 +419,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = { .flags_general = MTK_SMI_FLAG_SLEEP_CTL, }; +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = { + .config_port = mtk_smi_larb_config_port_gen2_general, + .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | + MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL, + .ostd = mtk_smi_larb_mt8188_ostd, +}; + static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { .config_port = mtk_smi_larb_config_port_gen2_general, }; @@ -390,6 +446,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186}, + {.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188}, {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, {} @@ -622,6 +679,18 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = { .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7), }; +static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vdo = { + .type = MTK_SMI_GEN2, + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(5) | F_MMU1_LARB(7), + .init = mtk_smi_common_mt8195_init, +}; + +static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = { + .type = MTK_SMI_GEN2, + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), + .init = mtk_smi_common_mt8195_init, +}; + static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { .type = MTK_SMI_GEN2, .has_gals = true, @@ -658,6 +727,8 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, + {.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo}, + {.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp}, {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v4 4/4] memory: mtk-smi: mt8188: Add SMI Support 2022-08-01 2:18 ` [PATCH v4 4/4] memory: mtk-smi: mt8188: Add SMI Support Chengci.Xu @ 2022-08-09 5:58 ` Yong Wu 0 siblings, 0 replies; 9+ messages in thread From: Yong Wu @ 2022-08-09 5:58 UTC (permalink / raw) To: Chengci.Xu, Krzysztof Kozlowski, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, yi.kuo, anthony.huang, wendy-st.lin, AngeloGioacchino Del Regno On Mon, 2022-08-01 at 10:18 +0800, Chengci.Xu wrote: > Add mt8188 smi common & larb support > > Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Reviewed-by: Yong Wu <yong.wu@mediatek.com> I remembered I have given this. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-08-17 12:55 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-08-01 2:18 [PATCH v4 0/4] MT8188 SMI SUPPORT Chengci.Xu 2022-08-01 2:18 ` [PATCH v4 1/4] dt-bindings: memory: mediatek: Add mt8188 smi binding Chengci.Xu 2022-08-01 2:18 ` [PATCH v4 2/4] memory: mtk-smi: Add return value for configure port function Chengci.Xu 2022-08-09 5:58 ` Yong Wu 2022-08-01 2:18 ` [PATCH v4 3/4] memory: mtk-smi: Add enable IOMMU SMC command for MM master Chengci.Xu 2022-08-09 5:58 ` Yong Wu 2022-08-17 12:43 ` Chengci.Xu 2022-08-01 2:18 ` [PATCH v4 4/4] memory: mtk-smi: mt8188: Add SMI Support Chengci.Xu 2022-08-09 5:58 ` Yong Wu
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