From: "Marek Behún" <kabel@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <helgaas@kernel.org>
Cc: "Krzysztof Wilczyński" <kw@linux.com>,
pali@kernel.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
"Marek Behún" <kabel@kernel.org>
Subject: [PATCH 11/11] PCI: aardvark: Cleanup some register macros
Date: Thu, 18 Aug 2022 15:51:40 +0200 [thread overview]
Message-ID: <20220818135140.5996-12-kabel@kernel.org> (raw)
In-Reply-To: <20220818135140.5996-1-kabel@kernel.org>
From: Pali Rohár <pali@kernel.org>
Define SPEED_GEN_* macros with correct PCIE_GEN_SEL_SHIFT.
Simplify macro for setting root complex mode (use BIT instead of
MSK + SHIFT).
Rename PCIE_MSG_PM_PME_MASK to PCIE_ISR0_MSG_PM_PME to match existing
naming convention, rename PCIE_ISR0_MSI_INT_PENDING to PCIE_ISR0_MSI_INT
as it is used for both interrupt mask and pending bit.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
---
drivers/pci/controller/pci-aardvark.c | 28 +++++++++++++--------------
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 73a604f70f06..11afafe71e3d 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -66,11 +66,10 @@
#define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
#define PCIE_GEN_SEL_MSK 0x3
#define PCIE_GEN_SEL_SHIFT 0x0
-#define SPEED_GEN_1 0
-#define SPEED_GEN_2 1
-#define SPEED_GEN_3 2
-#define IS_RC_MSK 1
-#define IS_RC_SHIFT 2
+#define SPEED_GEN_1 (0 << PCIE_GEN_SEL_SHIFT)
+#define SPEED_GEN_2 (1 << PCIE_GEN_SEL_SHIFT)
+#define SPEED_GEN_3 (2 << PCIE_GEN_SEL_SHIFT)
+#define IS_RC BIT(2)
#define LANE_CNT_MSK 0x18
#define LANE_CNT_SHIFT 0x3
#define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
@@ -95,16 +94,16 @@
#define PCIE_CORE_REF_CLK_RX_ENABLE BIT(2)
#define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
#define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
-#define PCIE_MSG_PM_PME_MASK BIT(7)
#define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
-#define PCIE_ISR0_MSI_INT_PENDING BIT(24)
#define PCIE_ISR0_LINK_DOWN BIT(1)
+#define PCIE_ISR0_MSG_PM_PME BIT(7)
#define PCIE_ISR0_CORR_ERR BIT(11)
#define PCIE_ISR0_NFAT_ERR BIT(12)
#define PCIE_ISR0_FAT_ERR BIT(13)
#define PCIE_ISR0_ERR_MASK GENMASK(13, 11)
#define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
#define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
+#define PCIE_ISR0_MSI_INT BIT(24)
#define PCIE_ISR0_ALL_MASK GENMASK(31, 0)
#define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
@@ -546,7 +545,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Set PCI global control register to RC mode */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
- reg |= (IS_RC_MSK << IS_RC_SHIFT);
+ reg |= IS_RC;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
/*
@@ -633,7 +632,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Unmask summary MSI interrupt */
reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- reg &= ~PCIE_ISR0_MSI_INT_PENDING;
+ reg &= ~PCIE_ISR0_MSI_INT;
advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
/* Unmask Link Down interrupt */
@@ -643,7 +642,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Unmask PME interrupt for processing of PME requester */
reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- reg &= ~PCIE_MSG_PM_PME_MASK;
+ reg &= ~PCIE_ISR0_MSG_PM_PME;
advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
/* Enable summary interrupt for GIC SPI source */
@@ -1661,7 +1660,7 @@ static void advk_pcie_handle_pme(struct advk_pcie *pcie)
{
u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16;
- advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);
+ advk_writel(pcie, PCIE_ISR0_MSG_PM_PME, PCIE_ISR0_REG);
/*
* PCIE_MSG_LOG_REG contains the last inbound message, so store
@@ -1700,8 +1699,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx);
}
- advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
- PCIE_ISR0_REG);
+ advk_writel(pcie, PCIE_ISR0_MSI_INT, PCIE_ISR0_REG);
}
static void advk_pcie_handle_int(struct advk_pcie *pcie)
@@ -1720,7 +1718,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie)
isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
/* Process PME interrupt as the first one to do not miss PME requester id */
- if (isr0_status & PCIE_MSG_PM_PME_MASK)
+ if (isr0_status & PCIE_ISR0_MSG_PM_PME)
advk_pcie_handle_pme(pcie);
/* Process ERR interrupt */
@@ -1756,7 +1754,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie)
}
/* Process MSI interrupts */
- if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
+ if (isr0_status & PCIE_ISR0_MSI_INT)
advk_pcie_handle_msi(pcie);
/* Process legacy interrupts */
--
2.35.1
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prev parent reply other threads:[~2022-08-18 14:07 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 13:51 [PATCH 00/11] PCI: aardvark controller changes BATCH 6 Marek Behún
2022-08-18 13:51 ` [PATCH 01/11] PCI: pciehp: Enable DLLSC interrupt only if supported Marek Behún
[not found] ` <20220821124621.GA23239@wunner.de>
2022-08-22 10:37 ` Marek Behún
2022-08-18 13:51 ` [PATCH 02/11] PCI: pciehp: Enable Command Completed Interrupt " Marek Behún
2022-09-28 8:39 ` Lorenzo Pieralisi
2022-08-18 13:51 ` [PATCH 03/11] PCI: aardvark: Add support for DLLSC and hotplug interrupt Marek Behún
2022-09-09 14:57 ` Lorenzo Pieralisi
2022-09-16 16:23 ` Marek Behún
2022-09-27 8:29 ` Lorenzo Pieralisi
2022-09-27 11:13 ` Pali Rohár
2022-09-27 15:57 ` Lorenzo Pieralisi
2022-09-17 9:05 ` Marc Zyngier
2022-09-26 11:49 ` Lorenzo Pieralisi
2022-09-26 12:35 ` Marc Zyngier
2022-09-26 14:00 ` Lorenzo Pieralisi
2022-09-27 13:40 ` Marek Behún
2022-08-18 13:51 ` [PATCH 04/11] PCI: aardvark: Send Set_Slot_Power_Limit message Marek Behún
2022-08-18 13:51 ` [PATCH 05/11] arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe Marek Behún
2022-08-18 13:51 ` [PATCH 06/11] PCI: aardvark: Add clock support Marek Behún
2022-08-18 13:51 ` [PATCH 07/11] PCI: aardvark: Add suspend to RAM support Marek Behún
2022-09-09 10:33 ` Lorenzo Pieralisi
2022-09-27 8:30 ` Lorenzo Pieralisi
2022-08-18 13:51 ` [PATCH 08/11] PCI: aardvark: Replace custom PCIE_CORE_ERR_CAPCTL_* macros by linux/pci_regs.h macros Marek Behún
2022-08-18 13:51 ` [PATCH 09/11] PCI: aardvark: Don't write read-only bits explicitly in PCI_ERR_CAP register Marek Behún
2022-08-18 13:51 ` [PATCH 10/11] PCI: aardvark: Explicitly disable Marvell strict ordering Marek Behún
2022-08-18 13:51 ` Marek Behún [this message]
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