* [PATCH 0/5] drm/msm+iommu/arm-smmu-qcom: tlbinv optimizations
@ 2022-08-21 18:19 Rob Clark
2022-08-21 18:19 ` [PATCH 2/5] iommu/arm-smmu-qcom: Provide way to access current TTBR0 Rob Clark
2022-08-21 18:19 ` [PATCH 3/5] iommu/arm-smmu-qcom: Add private interface to tlbinv by ASID Rob Clark
0 siblings, 2 replies; 3+ messages in thread
From: Rob Clark @ 2022-08-21 18:19 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-msm, freedreno, Rob Clark, Akhil P Oommen,
Bjorn Andersson, Chia-I Wu, Dmitry Baryshkov, Douglas Anderson,
open list:IOMMU DRIVERS, open list:IOMMU DRIVERS, Konrad Dybcio,
moderated list:ARM SMMU DRIVERS, open list, Loic Poulain,
Lu Baolu, Robin Murphy, Sean Paul, Sibi Sankar, Vinod Koul,
Will Deacon, Yang Yingliang
From: Rob Clark <robdclark@chromium.org>
Two additions to adreno_smmu_priv to allow for a couple of
optimizations:
+ Use a separate ASID for each set of pgtables to avoid
over-invalidation.
+ Detect the case of unmapping from non-current pgtables
where we can skip the redundant tlbinv
Rob Clark (5):
iommu/arm-smmu-qcom: Fix indentation
iommu/arm-smmu-qcom: Provide way to access current TTBR0
iommu/arm-smmu-qcom: Add private interface to tlbinv by ASID
drm/msm: Use separate ASID for each set of pgtables
drm/msm: Skip tlbinv on unmap from non-current pgtables
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++
drivers/gpu/drm/msm/msm_iommu.c | 44 +++++++++++++++++++---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 10 +++++
drivers/iommu/arm/arm-smmu/arm-smmu.c | 43 +++++++++++++++++++--
drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 +
include/linux/adreno-smmu-priv.h | 18 +++++----
6 files changed, 106 insertions(+), 16 deletions(-)
--
2.37.2
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^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 2/5] iommu/arm-smmu-qcom: Provide way to access current TTBR0
2022-08-21 18:19 [PATCH 0/5] drm/msm+iommu/arm-smmu-qcom: tlbinv optimizations Rob Clark
@ 2022-08-21 18:19 ` Rob Clark
2022-08-21 18:19 ` [PATCH 3/5] iommu/arm-smmu-qcom: Add private interface to tlbinv by ASID Rob Clark
1 sibling, 0 replies; 3+ messages in thread
From: Rob Clark @ 2022-08-21 18:19 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-msm, freedreno, Rob Clark, Will Deacon, Robin Murphy,
Joerg Roedel, Bjorn Andersson, Konrad Dybcio, Loic Poulain,
Vinod Koul, Sibi Sankar, moderated list:ARM SMMU DRIVERS,
open list:IOMMU DRIVERS, open list:IOMMU DRIVERS, open list
From: Rob Clark <robdclark@chromium.org>
The drm driver can skip tlbinv when unmapping from something that isn't
the current pgtables, as there is already a tlbinv on context switch.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 +++++++++
include/linux/adreno-smmu-priv.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 7820711c4560..59b460c1c9a5 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -157,6 +157,14 @@ static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
return 0;
}
+static u64 qcom_adreno_smmu_get_ttbr0(const void *cookie)
+{
+ struct arm_smmu_domain *smmu_domain = (void *)cookie;
+ struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
+
+ return arm_smmu_cb_readq(smmu_domain->smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
+}
+
static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
struct arm_smmu_device *smmu,
struct device *dev, int start)
@@ -217,6 +225,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
priv->cookie = smmu_domain;
priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
+ priv->get_ttbr0 = qcom_adreno_smmu_get_ttbr0;
priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
priv->set_stall = qcom_adreno_smmu_set_stall;
priv->resume_translation = qcom_adreno_smmu_resume_translation;
diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h
index ac4c2c0ab724..4ad90541a095 100644
--- a/include/linux/adreno-smmu-priv.h
+++ b/include/linux/adreno-smmu-priv.h
@@ -43,6 +43,7 @@ struct adreno_smmu_fault_info {
* @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A
* NULL config disables TTBR0 translation, otherwise
* TTBR0 translation is enabled with the specified cfg
+ * @get_ttbr0: Get current TTBR0 value
* @get_fault_info: Called by the GPU fault handler to get information about
* the fault
* @set_stall: Configure whether stall on fault (CFCFG) is enabled. Call
@@ -64,6 +65,7 @@ struct adreno_smmu_priv {
const void *cookie;
const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
+ u64 (*get_ttbr0)(const void *cookie);
void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
void (*set_stall)(const void *cookie, bool enabled);
void (*resume_translation)(const void *cookie, bool terminate);
--
2.37.2
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 3/5] iommu/arm-smmu-qcom: Add private interface to tlbinv by ASID
2022-08-21 18:19 [PATCH 0/5] drm/msm+iommu/arm-smmu-qcom: tlbinv optimizations Rob Clark
2022-08-21 18:19 ` [PATCH 2/5] iommu/arm-smmu-qcom: Provide way to access current TTBR0 Rob Clark
@ 2022-08-21 18:19 ` Rob Clark
1 sibling, 0 replies; 3+ messages in thread
From: Rob Clark @ 2022-08-21 18:19 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-msm, freedreno, Rob Clark, Will Deacon, Robin Murphy,
Joerg Roedel, Bjorn Andersson, Konrad Dybcio, Sibi Sankar,
Vinod Koul, Loic Poulain, Yang Yingliang, Lu Baolu,
moderated list:ARM SMMU DRIVERS, open list:IOMMU DRIVERS,
open list:IOMMU DRIVERS, open list
From: Rob Clark <robdclark@chromium.org>
This will let the drm driver use different ASID values for each set of
pgtables to avoid over-invalidation on unmap.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
drivers/iommu/arm/arm-smmu/arm-smmu.c | 43 ++++++++++++++++++++--
drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 +
include/linux/adreno-smmu-priv.h | 2 +
4 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 59b460c1c9a5..3230348729ab 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -229,6 +229,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
priv->set_stall = qcom_adreno_smmu_set_stall;
priv->resume_translation = qcom_adreno_smmu_resume_translation;
+ priv->tlb_inv_by_id = arm_smmu_tlb_inv_by_id;
return 0;
}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 2ed3594f384e..624359bb2092 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -252,7 +252,7 @@ static void arm_smmu_tlb_sync_context(struct arm_smmu_domain *smmu_domain)
spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
}
-static void arm_smmu_tlb_inv_context_s1(void *cookie)
+static void arm_smmu_tlb_inv_context_s1_asid(void *cookie, u16 asid)
{
struct arm_smmu_domain *smmu_domain = cookie;
/*
@@ -261,21 +261,56 @@ static void arm_smmu_tlb_inv_context_s1(void *cookie)
*/
wmb();
arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx,
- ARM_SMMU_CB_S1_TLBIASID, smmu_domain->cfg.asid);
+ ARM_SMMU_CB_S1_TLBIASID, asid);
arm_smmu_tlb_sync_context(smmu_domain);
}
-static void arm_smmu_tlb_inv_context_s2(void *cookie)
+static void arm_smmu_tlb_inv_context_s1(void *cookie)
+{
+ struct arm_smmu_domain *smmu_domain = cookie;
+
+ arm_smmu_tlb_inv_context_s1_asid(cookie, smmu_domain->cfg.asid);
+}
+
+static void arm_smmu_tlb_inv_context_s2_vmid(void *cookie, u16 vmid)
{
struct arm_smmu_domain *smmu_domain = cookie;
struct arm_smmu_device *smmu = smmu_domain->smmu;
/* See above */
wmb();
- arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid);
+ arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, vmid);
arm_smmu_tlb_sync_global(smmu);
}
+static void arm_smmu_tlb_inv_context_s2(void *cookie)
+{
+ struct arm_smmu_domain *smmu_domain = cookie;
+
+ arm_smmu_tlb_inv_context_s2_vmid(cookie, smmu_domain->cfg.vmid);
+}
+
+void arm_smmu_tlb_inv_by_id(const void *cookie, u16 id)
+{
+ struct arm_smmu_domain *smmu_domain = (void *)cookie;
+ struct arm_smmu_device *smmu = smmu_domain->smmu;
+
+ arm_smmu_rpm_get(smmu);
+ switch (smmu_domain->stage) {
+ case ARM_SMMU_DOMAIN_S1:
+ arm_smmu_tlb_inv_context_s1_asid(smmu_domain, id);
+ break;
+ case ARM_SMMU_DOMAIN_S2:
+ case ARM_SMMU_DOMAIN_NESTED:
+ arm_smmu_tlb_inv_context_s2_vmid(smmu_domain, id);
+ break;
+ case ARM_SMMU_DOMAIN_BYPASS:
+ break;
+ }
+
+ arm_smmu_rpm_put(smmu);
+}
+
static void arm_smmu_tlb_inv_range_s1(unsigned long iova, size_t size,
size_t granule, void *cookie, int reg)
{
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index 2b9b42fb6f30..f6fb52d6f841 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -527,6 +527,7 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu);
struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu);
struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
+void arm_smmu_tlb_inv_by_id(const void *cookie, u16 id);
void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);
int arm_mmu500_reset(struct arm_smmu_device *smmu);
diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h
index 4ad90541a095..c44fc68d4de8 100644
--- a/include/linux/adreno-smmu-priv.h
+++ b/include/linux/adreno-smmu-priv.h
@@ -50,6 +50,7 @@ struct adreno_smmu_fault_info {
* before set_ttbr0_cfg(). If stalling on fault is enabled,
* the GPU driver must call resume_translation()
* @resume_translation: Resume translation after a fault
+ * @tlb_inv_by_id: Flush TLB by ASID/VMID
*
*
* The GPU driver (drm/msm) and adreno-smmu work together for controlling
@@ -69,6 +70,7 @@ struct adreno_smmu_priv {
void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
void (*set_stall)(const void *cookie, bool enabled);
void (*resume_translation)(const void *cookie, bool terminate);
+ void (*tlb_inv_by_id)(const void *cookie, u16 id);
};
#endif /* __ADRENO_SMMU_PRIV_H */
--
2.37.2
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