From: Lucas Stach <l.stach@pengutronix.de>
To: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>,
Kieran Bingham <kieran.bingham@ideasonboard.com>,
linux-arm-kernel@lists.infradead.org,
patchwork-lst@pengutronix.de, kernel@pengutronix.de
Subject: [PATCH 2/3] soc: imx: imx8mp-blk-ctrl: enable global pixclk with HDMI_TX_PHY PD
Date: Fri, 26 Aug 2022 21:13:04 +0200 [thread overview]
Message-ID: <20220826191305.3215706-2-l.stach@pengutronix.de> (raw)
In-Reply-To: <20220826191305.3215706-1-l.stach@pengutronix.de>
NXP internal information shows that the PHY refclk is gated by the
GLOBAL_TX_PIX_CLK_EN bit, so to allow the PHY PLL to lock without the
LCDIF being already active, tie this bit to the HDMI_TX_PHY power
domain.
Fixes: e3442022f543 ("soc: imx: add i.MX8MP HDMI blk-ctrl")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/soc/imx/imx8mp-blk-ctrl.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
index 9401df25c85a..73f672104aaa 100644
--- a/drivers/soc/imx/imx8mp-blk-ctrl.c
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -192,7 +192,7 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
break;
case IMX8MP_HDMIBLK_PD_LCDIF:
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
- BIT(7) | BIT(16) | BIT(17) | BIT(18) |
+ BIT(16) | BIT(17) | BIT(18) |
BIT(19) | BIT(20));
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
@@ -221,6 +221,7 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
break;
case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
+ regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
@@ -243,7 +244,7 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
BIT(4) | BIT(5) | BIT(6));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
- BIT(7) | BIT(16) | BIT(17) | BIT(18) |
+ BIT(16) | BIT(17) | BIT(18) |
BIT(19) | BIT(20));
break;
case IMX8MP_HDMIBLK_PD_PAI:
@@ -271,6 +272,7 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
+ regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
break;
default:
--
2.30.2
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next prev parent reply other threads:[~2022-08-26 19:32 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 19:13 [PATCH 1/3] soc: imx: imx8mp-blk-ctrl: don't set power device name in Lucas Stach
2022-08-26 19:13 ` Lucas Stach [this message]
2022-08-29 1:56 ` [PATCH 2/3] soc: imx: imx8mp-blk-ctrl: enable global pixclk with HDMI_TX_PHY PD Peng Fan
2022-12-15 15:09 ` Lucas Stach
2022-12-31 5:41 ` Shawn Guo
2022-08-26 19:13 ` [PATCH 3/3] soc: imx: gpcv2: split PGC domain probe in two passes Lucas Stach
2022-08-29 1:55 ` Peng Fan
2022-08-29 7:15 ` Lucas Stach
2022-08-29 1:51 ` [PATCH 1/3] soc: imx: imx8mp-blk-ctrl: don't set power device name in Peng Fan
2022-12-31 5:31 ` Shawn Guo
2023-01-01 3:15 ` Shawn Guo
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