From: Shawn Guo <shawnguo@kernel.org>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>,
Kieran Bingham <kieran.bingham@ideasonboard.com>,
linux-arm-kernel@lists.infradead.org,
patchwork-lst@pengutronix.de, kernel@pengutronix.de
Subject: Re: [PATCH 2/3] soc: imx: imx8mp-blk-ctrl: enable global pixclk with HDMI_TX_PHY PD
Date: Sat, 31 Dec 2022 13:41:29 +0800 [thread overview]
Message-ID: <20221231054128.GB6112@T480> (raw)
In-Reply-To: <20220826191305.3215706-2-l.stach@pengutronix.de>
On Fri, Aug 26, 2022 at 09:13:04PM +0200, Lucas Stach wrote:
> NXP internal information shows that the PHY refclk is gated by the
> GLOBAL_TX_PIX_CLK_EN bit, so to allow the PHY PLL to lock without the
> LCDIF being already active, tie this bit to the HDMI_TX_PHY power
> domain.
>
> Fixes: e3442022f543 ("soc: imx: add i.MX8MP HDMI blk-ctrl")
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Applied, thanks!
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next prev parent reply other threads:[~2022-12-31 5:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 19:13 [PATCH 1/3] soc: imx: imx8mp-blk-ctrl: don't set power device name in Lucas Stach
2022-08-26 19:13 ` [PATCH 2/3] soc: imx: imx8mp-blk-ctrl: enable global pixclk with HDMI_TX_PHY PD Lucas Stach
2022-08-29 1:56 ` Peng Fan
2022-12-15 15:09 ` Lucas Stach
2022-12-31 5:41 ` Shawn Guo [this message]
2022-08-26 19:13 ` [PATCH 3/3] soc: imx: gpcv2: split PGC domain probe in two passes Lucas Stach
2022-08-29 1:55 ` Peng Fan
2022-08-29 7:15 ` Lucas Stach
2022-08-29 1:51 ` [PATCH 1/3] soc: imx: imx8mp-blk-ctrl: don't set power device name in Peng Fan
2022-12-31 5:31 ` Shawn Guo
2023-01-01 3:15 ` Shawn Guo
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