From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
Elaine Zhang <zhangqing@rock-chips.com>,
kernel@collabora.com,
Sebastian Reichel <sebastian.reichel@collabora.com>
Subject: [PATCHv2 4/9] clk: rockchip: add register offset of the cores select parent
Date: Fri, 30 Sep 2022 17:38:52 +0200 [thread overview]
Message-ID: <20220930153857.299396-5-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20220930153857.299396-1-sebastian.reichel@collabora.com>
From: Elaine Zhang <zhangqing@rock-chips.com>
The cores select parent register is special on RK3588.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk-cpu.c | 28 ++++++++++++++++++++--------
drivers/clk/rockchip/clk.h | 3 +++
2 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 47288197c9d7..11aa2259b532 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -166,10 +166,16 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
}
}
/* select alternate parent */
- writel(HIWORD_UPDATE(reg_data->mux_core_alt,
- reg_data->mux_core_mask,
- reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg[0]);
+ if (reg_data->mux_core_reg)
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->mux_core_reg);
+ else
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->core_reg[0]);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
@@ -202,10 +208,16 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
* primary parent by the extra dividers that were needed for the alt.
*/
- writel(HIWORD_UPDATE(reg_data->mux_core_main,
- reg_data->mux_core_mask,
- reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg[0]);
+ if (reg_data->mux_core_reg)
+ writel(HIWORD_UPDATE(reg_data->mux_core_main,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->mux_core_reg);
+ else
+ writel(HIWORD_UPDATE(reg_data->mux_core_main,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->core_reg[0]);
/* remove dividers */
for (i = 0; i < reg_data->num_cores; i++) {
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 7aa45cc70287..6aece7f07a7d 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -370,6 +370,8 @@ struct rockchip_cpuclk_rate_table {
* @div_core_shift[]: cores divider offset used to divide the pll value
* @div_core_mask[]: cores divider mask
* @num_cores: number of cpu cores
+ * @mux_core_reg: register offset of the cores select parent
+ * @mux_core_alt: mux value to select alternate parent
* @mux_core_main: mux value to select main parent of core
* @mux_core_shift: offset of the core multiplexer
* @mux_core_mask: core multiplexer mask
@@ -379,6 +381,7 @@ struct rockchip_cpuclk_reg_data {
u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
int num_cores;
+ int mux_core_reg;
u8 mux_core_alt;
u8 mux_core_main;
u8 mux_core_shift;
--
2.35.1
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next prev parent reply other threads:[~2022-09-30 15:40 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 15:38 [PATCHv2 0/9] RK3588 Clock and Reset Support Sebastian Reichel
2022-09-30 15:38 ` [PATCHv2 1/9] dt-bindings: clock: add rk3588 clock definitions Sebastian Reichel
2022-10-03 16:39 ` Rob Herring
2022-09-30 15:38 ` [PATCHv2 2/9] dt-bindings: reset: add rk3588 reset definitions Sebastian Reichel
2022-10-03 16:39 ` Rob Herring
2022-09-30 15:38 ` [PATCHv2 3/9] dt-bindings: clock: add rk3588 cru bindings Sebastian Reichel
2022-10-03 16:40 ` Rob Herring
2022-09-30 15:38 ` Sebastian Reichel [this message]
2022-09-30 15:38 ` [PATCHv2 5/9] clk: rockchip: add pll type for RK3588 Sebastian Reichel
2022-09-30 15:38 ` [PATCHv2 6/9] clk: rockchip: clk-cpu: add mux setting for cpu change frequency Sebastian Reichel
2022-09-30 15:38 ` [PATCHv2 7/9] clk: rockchip: simplify rockchip_clk_add_lookup Sebastian Reichel
2022-09-30 15:38 ` [PATCHv2 8/9] clk: rockchip: add lookup table support Sebastian Reichel
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