From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
Elaine Zhang <zhangqing@rock-chips.com>,
kernel@collabora.com,
Sebastian Reichel <sebastian.reichel@collabora.com>
Subject: [PATCHv2 6/9] clk: rockchip: clk-cpu: add mux setting for cpu change frequency
Date: Fri, 30 Sep 2022 17:38:54 +0200 [thread overview]
Message-ID: <20220930153857.299396-7-sebastian.reichel@collabora.com> (raw)
In-Reply-To: <20220930153857.299396-1-sebastian.reichel@collabora.com>
From: Elaine Zhang <zhangqing@rock-chips.com>
In order to improve the main frequency of CPU, the clock path of CPU is
simplified as follows:
|--\
| \ |--\
--apll--|\ | \ | \
| |--apll_core--| \ | \
--24M---|/ |mux1 |--[gate]--|mux2|---clk_core
| / | /
--gpll--|\ | / |------| /
| |--gpll_core--| / | |--/
--24M---|/ |--/ |
|
-------apll_directly--------------|
When the CPU requests high frequency, we want to use MUX2 select the
"apll_directly".
At low frequencies use MUX1 to select “apll_core" and then MUX2 to
select "apll_core_gate".
However, in this way, the CPU frequency conversion needs to be
in the following order:
1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core"
2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL
sets normal_mode
3. MUX1 select "apll_core", MUX2 select "apll_directly"
So add pre_muxs and post_muxs to cover this special requirements.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[rebase]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/clk/rockchip/clk-cpu.c | 41 ++++++++++++++++++++++++++++++++++
drivers/clk/rockchip/clk.h | 2 ++
2 files changed, 43 insertions(+)
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 11aa2259b532..6ea7fba9f9e5 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -113,6 +113,42 @@ static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,
}
}
+static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk,
+ const struct rockchip_cpuclk_rate_table *rate)
+{
+ int i;
+
+ /* alternate parent is active now. set the pre_muxs */
+ for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) {
+ const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i];
+
+ if (!clksel->reg)
+ break;
+
+ pr_debug("%s: setting reg 0x%x to 0x%x\n",
+ __func__, clksel->reg, clksel->val);
+ writel(clksel->val, cpuclk->reg_base + clksel->reg);
+ }
+}
+
+static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk,
+ const struct rockchip_cpuclk_rate_table *rate)
+{
+ int i;
+
+ /* alternate parent is active now. set the muxs */
+ for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) {
+ const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i];
+
+ if (!clksel->reg)
+ break;
+
+ pr_debug("%s: setting reg 0x%x to 0x%x\n",
+ __func__, clksel->reg, clksel->val);
+ writel(clksel->val, cpuclk->reg_base + clksel->reg);
+ }
+}
+
static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
struct clk_notifier_data *ndata)
{
@@ -165,6 +201,9 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
cpuclk->reg_base + reg_data->core_reg[i]);
}
}
+
+ rockchip_cpuclk_set_pre_muxs(cpuclk, rate);
+
/* select alternate parent */
if (reg_data->mux_core_reg)
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
@@ -219,6 +258,8 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->core_reg[0]);
+ rockchip_cpuclk_set_post_muxs(cpuclk, rate);
+
/* remove dividers */
for (i = 0; i < reg_data->num_cores; i++) {
writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index bf7c8d082fde..2bd1863a7418 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -380,6 +380,8 @@ struct rockchip_cpuclk_clksel {
struct rockchip_cpuclk_rate_table {
unsigned long prate;
struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
+ struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
+ struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
};
/**
--
2.35.1
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next prev parent reply other threads:[~2022-09-30 15:42 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 15:38 [PATCHv2 0/9] RK3588 Clock and Reset Support Sebastian Reichel
2022-09-30 15:38 ` [PATCHv2 1/9] dt-bindings: clock: add rk3588 clock definitions Sebastian Reichel
2022-10-03 16:39 ` Rob Herring
2022-09-30 15:38 ` [PATCHv2 2/9] dt-bindings: reset: add rk3588 reset definitions Sebastian Reichel
2022-10-03 16:39 ` Rob Herring
2022-09-30 15:38 ` [PATCHv2 3/9] dt-bindings: clock: add rk3588 cru bindings Sebastian Reichel
2022-10-03 16:40 ` Rob Herring
2022-09-30 15:38 ` [PATCHv2 4/9] clk: rockchip: add register offset of the cores select parent Sebastian Reichel
2022-09-30 15:38 ` [PATCHv2 5/9] clk: rockchip: add pll type for RK3588 Sebastian Reichel
2022-09-30 15:38 ` Sebastian Reichel [this message]
2022-09-30 15:38 ` [PATCHv2 7/9] clk: rockchip: simplify rockchip_clk_add_lookup Sebastian Reichel
2022-09-30 15:38 ` [PATCHv2 8/9] clk: rockchip: add lookup table support Sebastian Reichel
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