[PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Jagan Teki]

This series supports common bridge support for Samsung MIPI DSIM
which is used in Exynos and i.MX8MM SoC's.

The final bridge supports both the Exynos and i.MX8MM DSI devices.

Changes for v7:
* fix the drm bridge attach chain for exynos drm dsi driver
* fix the hw_type checking logic

Changes for v6:
* handle previous bridge for exynos dsi while attaching bridge 

Changes for v5:
* bridge changes to support multi-arch
* updated and clear commit messages
* add hw_type via plat data
* removed unneeded quirk
* rebased on linux-next

Changes for v4:
* include Inki Dae in MAINTAINERS
* remove dsi_driver probe in exynos_drm_drv to support multi-arch build
* update init handling to ensure host init done on first cmd transfer

Changes for v3:
* fix the mult-arch build
* fix dsi host init
* updated commit messages

Changes for v2:
* fix bridge handling
* fix dsi host init
* correct the commit messages

Patch 0001: 	Samsung DSIM bridge

Patch 0002:	PHY optional

Patch 0003:	OF-graph or Child node lookup

Patch 0004: 	DSI host initialization 

Patch 0005:	atomic check

Patch 0006:	PMS_P offset via plat data

Patch 0007:	atomic_get_input_bus_fmts

Patch 0008:	input_bus_flags

Patch 0009:	document fsl,imx8mm-mipi-dsim

Patch 0010:	add i.MX8MM DSIM support

Tested in Engicam i.Core MX8M Mini SoM.

Repo:
https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v7

Any inputs?
Jagan.

Jagan Teki (10):
  drm: bridge: Add Samsung DSIM bridge driver
  drm: bridge: samsung-dsim: Lookup OF-graph or Child node devices
  drm: bridge: samsung-dsim: Mark PHY as optional
  drm: bridge: samsung-dsim: Handle proper DSI host initialization
  drm: bridge: samsung-dsim: Add atomic_check
  drm: bridge: samsung-dsim: Add platform PLL_P (PMS_P) offset
  drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts
  drm: bridge: samsung-dsim: Add input_bus_flags
  dt-bindings: display: exynos: dsim: Add NXP i.MX8MM support
  drm: bridge: samsung-dsim: Add i.MX8MM support

 .../bindings/display/exynos/exynos_dsim.txt   |    1 +
 MAINTAINERS                                   |    9 +
 drivers/gpu/drm/bridge/Kconfig                |   12 +
 drivers/gpu/drm/bridge/Makefile               |    1 +
 drivers/gpu/drm/bridge/samsung-dsim.c         | 1856 +++++++++++++++++
 drivers/gpu/drm/exynos/Kconfig                |    1 +
 drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1766 +---------------
 include/drm/bridge/samsung-dsim.h             |  115 +
 8 files changed, 2108 insertions(+), 1653 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
 create mode 100644 include/drm/bridge/samsung-dsim.h

-- 
2.25.1


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[PATCH v7 02/10] drm: bridge: samsung-dsim: Lookup OF-graph or Child node devices

[Jagan Teki]

The child devices in MIPI DSI can be binding with OF-graph
and also via child nodes.

The OF-graph interface represents the child devices via
remote and associated endpoint numbers like

dsi {
   compatible = "fsl,imx8mm-mipi-dsim";

   ports {
	port@0 {
	     reg = <0>;

	     dsi_in_lcdif: endpoint@0 {
		  reg = <0>;
		  remote-endpoint = <&lcdif_out_dsi>;
	     };
	};

	port@1 {
	     reg = <1>;

	     dsi_out_bridge: endpoint {
		  remote-endpoint = <&bridge_in_dsi>;
	     };
	};
};

The child node interface represents the child devices via
conventional child nodes on given DSI parent like

dsi {
   compatible = "samsung,exynos5433-mipi-dsi";

   ports {
        port@0 {
             reg = <0>;

             dsi_to_mic: endpoint {
                  remote-endpoint = <&mic_to_dsi>;
             };
        };
   };

   panel@0 {
        reg = <0>;
   };
};

As Samsung DSIM bridge is common DSI IP across all Exynos DSI
and NXP i.MX8M host controllers, this patch adds support to
lookup the child devices whether its bindings on the associated
host represent OF-graph or child node interfaces.

v7, v6, v5, v4, v3:
* none

v2:
* new patch

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 38 +++++++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 07563d00a420..c34c6abac815 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1356,18 +1356,52 @@ static int samsung_dsim_host_attach(struct mipi_dsi_host *host,
 	struct samsung_dsim *dsi = host_to_dsi(host);
 	const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
 	struct device *dev = dsi->dev;
+	struct device_node *np = dev->of_node;
+	struct device_node *remote;
 	struct drm_panel *panel;
 	int ret;
 
-	panel = of_drm_find_panel(device->dev.of_node);
+	/**
+	 * Devices can also be child nodes when we also control that device
+	 * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
+	 *
+	 * Lookup for a child node of the given parent that isn't either port
+	 * or ports.
+	 */
+	for_each_available_child_of_node(np, remote) {
+		if (of_node_name_eq(remote, "port") ||
+		    of_node_name_eq(remote, "ports"))
+			continue;
+
+		goto of_find_panel_or_bridge;
+	}
+
+	/*
+	 * of_graph_get_remote_node() produces a noisy error message if port
+	 * node isn't found and the absence of the port is a legit case here,
+	 * so at first we silently check whether graph presents in the
+	 * device-tree node.
+	 */
+	if (!of_graph_is_present(np))
+		return -ENODEV;
+
+	remote = of_graph_get_remote_node(np, 1, 0);
+
+of_find_panel_or_bridge:
+	if (!remote)
+		return -ENODEV;
+
+	panel = of_drm_find_panel(remote);
 	if (!IS_ERR(panel)) {
 		dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel);
 	} else {
-		dsi->out_bridge = of_drm_find_bridge(device->dev.of_node);
+		dsi->out_bridge = of_drm_find_bridge(remote);
 		if (!dsi->out_bridge)
 			dsi->out_bridge = ERR_PTR(-EINVAL);
 	}
 
+	of_node_put(remote);
+
 	if (IS_ERR(dsi->out_bridge)) {
 		ret = PTR_ERR(dsi->out_bridge);
 		DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret);
-- 
2.25.1


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[PATCH v7 03/10] drm: bridge: samsung-dsim: Mark PHY as optional

[Jagan Teki]

In i.MX8M Mini/Nano SoC the DSI Phy requires a MIPI DPHY bit
to reset in order to activate the PHY and that can be done via
upstream i.MX8M blk-ctrl driver.

So, mark the phy get as optional.

v7, v6, v5, v4, v3, v2:
* none

v1:
* new patch

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index c34c6abac815..1bae3673151b 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1584,7 +1584,7 @@ int samsung_dsim_probe(struct platform_device *pdev)
 	if (IS_ERR(dsi->reg_base))
 		return PTR_ERR(dsi->reg_base);
 
-	dsi->phy = devm_phy_get(dev, "dsim");
+	dsi->phy = devm_phy_optional_get(dev, "dsim");
 	if (IS_ERR(dsi->phy)) {
 		dev_info(dev, "failed to get dsim phy\n");
 		return PTR_ERR(dsi->phy);
-- 
2.25.1


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[PATCH v7 04/10] drm: bridge: samsung-dsim: Handle proper DSI host initialization

[Jagan Teki]

DSI host initialization handling in previous exynos dsi driver has
some pitfalls. It initializes the host during host transfer() hook
that is indeed not the desired call flow for I2C and any other DSI
configured downstream bridges.

Host transfer() is usually triggered for downstream DSI panels or
bridges and I2C-configured-DSI bridges miss these host initialization
as these downstream bridges use bridge operations hooks like pre_enable,
and enable in order to initialize or set up the host.

This patch is trying to handle the host init handler to satisfy all
downstream panels and bridges. Added the DSIM_STATE_REINITIALIZED state
flag to ensure that host init is also done on first cmd transfer, this
helps existing DSI panels work on exynos platform (form Marek
Szyprowski).

v7, v6, v5:
* none

v4:
* update init handling to ensure host init done on first cmd transfer

v3:
* none

v2:
* check initialized state in samsung_dsim_init

v1:
* keep DSI init in host transfer

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 25 +++++++++++++++++--------
 include/drm/bridge/samsung-dsim.h     |  5 +++--
 2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 1bae3673151b..563781bb27c4 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1234,12 +1234,17 @@ static void samsung_dsim_disable_irq(struct samsung_dsim *dsi)
 	disable_irq(dsi->irq);
 }
 
-static int samsung_dsim_init(struct samsung_dsim *dsi)
+static int samsung_dsim_init(struct samsung_dsim *dsi, unsigned int flag)
 {
 	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
 
+	if (dsi->state & flag)
+		return 0;
+
 	samsung_dsim_reset(dsi);
-	samsung_dsim_enable_irq(dsi);
+
+	if (!(dsi->state & DSIM_STATE_INITIALIZED))
+		samsung_dsim_enable_irq(dsi);
 
 	if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
 		samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1);
@@ -1250,6 +1255,8 @@ static int samsung_dsim_init(struct samsung_dsim *dsi)
 	samsung_dsim_set_phy_ctrl(dsi);
 	samsung_dsim_init_link(dsi);
 
+	dsi->state |= flag;
+
 	return 0;
 }
 
@@ -1269,6 +1276,10 @@ static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge,
 	}
 
 	dsi->state |= DSIM_STATE_ENABLED;
+
+	ret = samsung_dsim_init(dsi, DSIM_STATE_INITIALIZED);
+	if (ret)
+		return;
 }
 
 static void samsung_dsim_atomic_enable(struct drm_bridge *bridge,
@@ -1458,12 +1469,9 @@ static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host,
 	if (!(dsi->state & DSIM_STATE_ENABLED))
 		return -EINVAL;
 
-	if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
-		ret = samsung_dsim_init(dsi);
-		if (ret)
-			return ret;
-		dsi->state |= DSIM_STATE_INITIALIZED;
-	}
+	ret = samsung_dsim_init(dsi, DSIM_STATE_REINITIALIZED);
+	if (ret)
+		return ret;
 
 	ret = mipi_dsi_create_packet(&xfer.packet, msg);
 	if (ret < 0)
@@ -1653,6 +1661,7 @@ static int __maybe_unused samsung_dsim_suspend(struct device *dev)
 
 	if (dsi->state & DSIM_STATE_INITIALIZED) {
 		dsi->state &= ~DSIM_STATE_INITIALIZED;
+		dsi->state &= ~DSIM_STATE_REINITIALIZED;
 
 		samsung_dsim_disable_clock(dsi);
 
diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
index b8132bf8e36f..0c5a905f3de7 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -17,8 +17,9 @@ struct samsung_dsim;
 
 #define DSIM_STATE_ENABLED		BIT(0)
 #define DSIM_STATE_INITIALIZED		BIT(1)
-#define DSIM_STATE_CMD_LPM		BIT(2)
-#define DSIM_STATE_VIDOUT_AVAILABLE	BIT(3)
+#define DSIM_STATE_REINITIALIZED	BIT(2)
+#define DSIM_STATE_CMD_LPM		BIT(3)
+#define DSIM_STATE_VIDOUT_AVAILABLE	BIT(4)
 
 enum samsung_dsim_type {
 	SAMSUNG_DSIM_TYPE_EXYNOS3250,
-- 
2.25.1


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[PATCH v7 05/10] drm: bridge: samsung-dsim: Add atomic_check

[Jagan Teki]

Look like an explicit fixing up of mode_flags is required for DSIM IP
present in i.MX8M Mini/Nano SoCs.

At least the LCDIF + DSIM needs active low sync polarities in order
to correlate the correct sync flags of the surrounding components in
the chain to make sure the whole pipeline can work properly.

On the other hand the i.MX 8M Mini Applications Processor Reference Manual,
Rev. 3, 11/2020 says.
"13.6.3.5.2 RGB interface
 Vsync, Hsync, and VDEN are active high signals."

No clear evidence about whether it can be documentation issues or
something, so added a comment FIXME for this and updated the active low
sync polarities using SAMSUNG_DSIM_TYPE_IMX8MM hw_type.

v7:
* fix the hw_type checking logic

v6:
* none

v5:
* rebase based new bridge changes [mszyprow]
* remove DSIM_QUIRK_FIXUP_SYNC_POL
* add hw_type check for sync polarities change.

v4:
* none

v3:
* add DSIM_QUIRK_FIXUP_SYNC_POL to handle mode_flasg fixup

v2:
* none

v1:
* fix mode flags in atomic_check instead of mode_fixup

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 563781bb27c4..b46346232c52 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1315,6 +1315,31 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
 	pm_runtime_put_sync(dsi->dev);
 }
 
+static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
+				     struct drm_bridge_state *bridge_state,
+				     struct drm_crtc_state *crtc_state,
+				     struct drm_connector_state *conn_state)
+{
+	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
+	struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
+
+	if (dsi->plat_data->hw_type == SAMSUNG_DSIM_TYPE_IMX8MM) {
+		/**
+		 * FIXME:
+		 * At least LCDIF + DSIM needs active low sync,
+		 * but i.MX 8M Mini Applications Processor Reference Manual,
+		 * Rev. 3, 11/2020 says
+		 *
+		 * 13.6.3.5.2 RGB interface
+		 * Vsync, Hsync, and VDEN are active high signals.
+		 */
+		adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
+		adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
+	}
+
+	return 0;
+}
+
 static void samsung_dsim_mode_set(struct drm_bridge *bridge,
 				  const struct drm_display_mode *mode,
 				  const struct drm_display_mode *adjusted_mode)
@@ -1353,6 +1378,7 @@ static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
 	.atomic_duplicate_state		= drm_atomic_helper_bridge_duplicate_state,
 	.atomic_destroy_state		= drm_atomic_helper_bridge_destroy_state,
 	.atomic_reset			= drm_atomic_helper_bridge_reset,
+	.atomic_check			= samsung_dsim_atomic_check,
 	.atomic_pre_enable		= samsung_dsim_atomic_pre_enable,
 	.atomic_enable			= samsung_dsim_atomic_enable,
 	.atomic_disable			= samsung_dsim_atomic_disable,
-- 
2.25.1


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[PATCH v7 06/10] drm: bridge: samsung-dsim: Add platform PLL_P (PMS_P) offset

[Jagan Teki]

Look like PLL PMS_P offset value varies between platforms that have
Samsung DSIM IP.

However, there is no clear evidence for it as both Exynos and i.MX
8M Mini Application Processor Reference Manual is still referring
the PMS_P offset as 13.

The offset 13 is not working for i.MX8M Mini SoCs but the downstream
NXP sec-dsim.c driver is using offset 14 for i.MX8M Mini SoC platforms
[1] [2].

PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P()
with offset 13 and then an additional offset of one bit added in
sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS().

Not sure whether it is reference manual documentation or something else
but this patch trusts the downstream code and handle PLL_P offset via
platform driver data so-that imx8mm driver data shall use pll_p_offset
to 14.

[1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n210
[2] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211

v7, v6:
* none

v5:
* updated clear commit message

v4, v3, v2:
* none

v1:
* updated commit message
* add downstream driver link

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 10 ++++++++--
 include/drm/bridge/samsung-dsim.h     |  1 +
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index b46346232c52..41970e794a7c 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -168,7 +168,7 @@
 /* DSIM_PLLCTRL */
 #define DSIM_FREQ_BAND(x)		((x) << 24)
 #define DSIM_PLL_EN			(1 << 23)
-#define DSIM_PLL_P(x)			((x) << 13)
+#define DSIM_PLL_P(x, offset)		((x) << (offset))
 #define DSIM_PLL_M(x)			((x) << 4)
 #define DSIM_PLL_S(x)			((x) << 1)
 
@@ -368,6 +368,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
 	.max_freq = 1000,
 	.wait_for_reset = 1,
 	.num_bits_resol = 11,
+	.pll_p_offset = 13,
 	.reg_values = reg_values,
 };
 
@@ -380,6 +381,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
 	.max_freq = 1000,
 	.wait_for_reset = 1,
 	.num_bits_resol = 11,
+	.pll_p_offset = 13,
 	.reg_values = reg_values,
 };
 
@@ -390,6 +392,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
 	.max_freq = 1000,
 	.wait_for_reset = 1,
 	.num_bits_resol = 11,
+	.pll_p_offset = 13,
 	.reg_values = reg_values,
 };
 
@@ -401,6 +404,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
 	.max_freq = 1500,
 	.wait_for_reset = 0,
 	.num_bits_resol = 12,
+	.pll_p_offset = 13,
 	.reg_values = exynos5433_reg_values,
 };
 
@@ -412,6 +416,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
 	.max_freq = 1500,
 	.wait_for_reset = 1,
 	.num_bits_resol = 12,
+	.pll_p_offset = 13,
 	.reg_values = exynos5422_reg_values,
 };
 
@@ -543,7 +548,8 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
 	writel(driver_data->reg_values[PLL_TIMER],
 			dsi->reg_base + driver_data->plltmr_reg);
 
-	reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
+	reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
+	      DSIM_PLL_M(m) | DSIM_PLL_S(s);
 
 	if (driver_data->has_freqband) {
 		static const unsigned long freq_bands[] = {
diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
index 0c5a905f3de7..df3d030daec6 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -53,6 +53,7 @@ struct samsung_dsim_driver_data {
 	unsigned int max_freq;
 	unsigned int wait_for_reset;
 	unsigned int num_bits_resol;
+	unsigned int pll_p_offset;
 	const unsigned int *reg_values;
 };
 
-- 
2.25.1


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[PATCH v7 07/10] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts

[Jagan Teki]

Finding the right input bus format throughout the pipeline is hard
so add atomic_get_input_bus_fmts callback and initialize with the
default RGB888_1X24 bus format on DSI-end.

This format can be used in pipeline for negotiating bus format between
the DSI-end of this bridge and the other component closer to pipeline
components.

v7, v6, v5, v4:
* none

v3:
* include media-bus-format.h

v2:
* none

v1:
* new patch

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 28 +++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 41970e794a7c..f714e49c1eab 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/irq.h>
+#include <linux/media-bus-format.h>
 #include <linux/of_device.h>
 #include <linux/phy/phy.h>
 
@@ -1321,6 +1322,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
 	pm_runtime_put_sync(dsi->dev);
 }
 
+#define MAX_INPUT_SEL_FORMATS	1
+
+static u32 *
+samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+				       struct drm_bridge_state *bridge_state,
+				       struct drm_crtc_state *crtc_state,
+				       struct drm_connector_state *conn_state,
+				       u32 output_fmt,
+				       unsigned int *num_input_fmts)
+{
+	u32 *input_fmts;
+
+	*num_input_fmts = 0;
+
+	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
+			     GFP_KERNEL);
+	if (!input_fmts)
+		return NULL;
+
+	/* This is the DSI-end bus format */
+	input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
+	*num_input_fmts = 1;
+
+	return input_fmts;
+}
+
 static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
 				     struct drm_bridge_state *bridge_state,
 				     struct drm_crtc_state *crtc_state,
@@ -1384,6 +1411,7 @@ static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
 	.atomic_duplicate_state		= drm_atomic_helper_bridge_duplicate_state,
 	.atomic_destroy_state		= drm_atomic_helper_bridge_destroy_state,
 	.atomic_reset			= drm_atomic_helper_bridge_reset,
+	.atomic_get_input_bus_fmts	= samsung_dsim_atomic_get_input_bus_fmts,
 	.atomic_check			= samsung_dsim_atomic_check,
 	.atomic_pre_enable		= samsung_dsim_atomic_pre_enable,
 	.atomic_enable			= samsung_dsim_atomic_enable,
-- 
2.25.1


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[PATCH v7 08/10] drm: bridge: samsung-dsim: Add input_bus_flags

[Jagan Teki]

eLCDIF is expecting to have input_bus_flags as DE_LOW in order to
set active low during valid data transfer on each horizontal line.

Add DE_LOW flag via drm bridge timings.

v7, v6:
* none

v5:
* rebased based on updated bridge changes

v4, v3, v2, v1:
* none

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index f714e49c1eab..f5cd80641cea 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1601,6 +1601,10 @@ static const struct samsung_dsim_host_ops samsung_dsim_generic_host_ops = {
 	.unregister_host = samsung_dsim_unregister_host,
 };
 
+static const struct drm_bridge_timings samsung_dsim_bridge_timings = {
+	.input_bus_flags = DRM_BUS_FLAG_DE_LOW,
+};
+
 int samsung_dsim_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -1681,6 +1685,7 @@ int samsung_dsim_probe(struct platform_device *pdev)
 
 	dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
 	dsi->bridge.of_node = dev->of_node;
+	dsi->bridge.timings = &samsung_dsim_bridge_timings;
 	dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
 	if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host)
-- 
2.25.1


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[PATCH v7 09/10] dt-bindings: display: exynos: dsim: Add NXP i.MX8MM support

[Jagan Teki]

Samsung MIPI DSIM bridge can also be found in i.MX8MM SoC.

Add dt-bingings for it.

v7, v6, v5, v4:
* none

v3:
* collect Rob Acked-by

v2:
* updated comments

v1:
* new patch

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
index be377786e8cd..8efcf4728e0b 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
@@ -7,6 +7,7 @@ Required properties:
 		"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
 		"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
 		"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
+		"fsl,imx8mm-mipi-dsim" /* for i.MX8M Mini SoCs */
   - reg: physical base address and length of the registers set for the device
   - interrupts: should contain DSI interrupt
   - clocks: list of clock specifiers, must contain an entry for each required
-- 
2.25.1


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[PATCH v7 10/10] drm: bridge: samsung-dsim: Add i.MX8MM support

[Jagan Teki]

Samsung MIPI DSIM master can also be found in i.MX8MM SoC.

Add compatible and associated driver_data for it.

v7, v6:
* none

v3:
* enable DSIM_QUIRK_FIXUP_SYNC_POL quirk

v5:
* [mszyprow] rebased and adjusted to the new driver initialization
* drop quirk

v4:
* none

v3:
* enable DSIM_QUIRK_FIXUP_SYNC_POL quirk

v2:
* collect Laurent r-b

v1:
* none

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 45 +++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index f5cd80641cea..1b5ba33dc635 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -360,6 +360,24 @@ static const unsigned int exynos5433_reg_values[] = {
 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
 };
 
+static const unsigned int imx8mm_dsim_reg_values[] = {
+	[RESET_TYPE] = DSIM_SWRST,
+	[PLL_TIMER] = 500,
+	[STOP_STATE_CNT] = 0xf,
+	[PHYCTRL_ULPS_EXIT] = 0,
+	[PHYCTRL_VREG_LP] = 0,
+	[PHYCTRL_SLEW_UP] = 0,
+	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
+	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
+	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
+	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26),
+	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
+	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
+	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08),
+	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
+	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
+};
+
 static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
 	.reg_ofs = exynos_reg_ofs,
 	.plltmr_reg = 0x50,
@@ -421,6 +439,23 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
 	.reg_values = exynos5422_reg_values,
 };
 
+static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
+	.reg_ofs = exynos5433_reg_ofs,
+	.plltmr_reg = 0xa0,
+	.has_clklane_stop = 1,
+	.num_clks = 2,
+	.max_freq = 2100,
+	.wait_for_reset = 0,
+	.num_bits_resol = 12,
+	/**
+	 * FIXME:
+	 * Offset value used from downstream drivers/gpu/drm/bridge/sec-dsim.c
+	 * remove this comment if it is true else update the logic.
+	 */
+	.pll_p_offset = 14,
+	.reg_values = imx8mm_dsim_reg_values,
+};
+
 static const struct samsung_dsim_driver_data *
 samsung_dsim_types[SAMSUNG_DSIM_TYPE_COUNT] = {
 	[SAMSUNG_DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data,
@@ -428,6 +463,7 @@ samsung_dsim_types[SAMSUNG_DSIM_TYPE_COUNT] = {
 	[SAMSUNG_DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data,
 	[SAMSUNG_DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data,
 	[SAMSUNG_DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data,
+	[SAMSUNG_DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data,
 };
 
 static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h)
@@ -1788,7 +1824,16 @@ const struct dev_pm_ops samsung_dsim_pm_ops = {
 };
 EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops);
 
+static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = {
+	.hw_type = SAMSUNG_DSIM_TYPE_IMX8MM,
+	.host_ops = &samsung_dsim_generic_host_ops,
+};
+
 static const struct of_device_id samsung_dsim_of_match[] = {
+	{
+		.compatible = "fsl,imx8mm-mipi-dsim",
+		.data = &samsung_dsim_imx8mm_pdata,
+	},
 	{ /* sentinel. */ }
 };
 MODULE_DEVICE_TABLE(of, samsung_dsim_of_match);
-- 
2.25.1


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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Marek Szyprowski]

Hi Jagan,

On 05.10.2022 17:12, Jagan Teki wrote:
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
>
> The final bridge supports both the Exynos and i.MX8MM DSI devices.
>
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
>
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge
>
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
>
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
>
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
>
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
>
> Patch 0001: 	Samsung DSIM bridge
>
> Patch 0002:	PHY optional
>
> Patch 0003:	OF-graph or Child node lookup
>
> Patch 0004: 	DSI host initialization
>
> Patch 0005:	atomic check
>
> Patch 0006:	PMS_P offset via plat data
>
> Patch 0007:	atomic_get_input_bus_fmts
>
> Patch 0008:	input_bus_flags
>
> Patch 0009:	document fsl,imx8mm-mipi-dsim
>
> Patch 0010:	add i.MX8MM DSIM support
>
> Tested in Engicam i.Core MX8M Mini SoM.

This finally doesn't break Exynos DSI. :) Feel free to add:

Acked-by: Marek Szyprowski

Tested-by: Marek Szyprowski

The next step would be to merge Dave's patchset and remove the hacks 
added here and there. Otherwise we will end up adding even more hacks soon.

> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v7
>
> Any inputs?
> Jagan.
>
> Jagan Teki (10):
>    drm: bridge: Add Samsung DSIM bridge driver
>    drm: bridge: samsung-dsim: Lookup OF-graph or Child node devices
>    drm: bridge: samsung-dsim: Mark PHY as optional
>    drm: bridge: samsung-dsim: Handle proper DSI host initialization
>    drm: bridge: samsung-dsim: Add atomic_check
>    drm: bridge: samsung-dsim: Add platform PLL_P (PMS_P) offset
>    drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts
>    drm: bridge: samsung-dsim: Add input_bus_flags
>    dt-bindings: display: exynos: dsim: Add NXP i.MX8MM support
>    drm: bridge: samsung-dsim: Add i.MX8MM support
>
>   .../bindings/display/exynos/exynos_dsim.txt   |    1 +
>   MAINTAINERS                                   |    9 +
>   drivers/gpu/drm/bridge/Kconfig                |   12 +
>   drivers/gpu/drm/bridge/Makefile               |    1 +
>   drivers/gpu/drm/bridge/samsung-dsim.c         | 1856 +++++++++++++++++
>   drivers/gpu/drm/exynos/Kconfig                |    1 +
>   drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1766 +---------------
>   include/drm/bridge/samsung-dsim.h             |  115 +
>   8 files changed, 2108 insertions(+), 1653 deletions(-)
>   create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
>   create mode 100644 include/drm/bridge/samsung-dsim.h
>
Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland


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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Jagan Teki]

Hi Marek,

On Thu, Oct 6, 2022 at 2:21 AM Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
>
> Hi Jagan,
>
> On 05.10.2022 17:12, Jagan Teki wrote:
> > This series supports common bridge support for Samsung MIPI DSIM
> > which is used in Exynos and i.MX8MM SoC's.
> >
> > The final bridge supports both the Exynos and i.MX8MM DSI devices.
> >
> > Changes for v7:
> > * fix the drm bridge attach chain for exynos drm dsi driver
> > * fix the hw_type checking logic
> >
> > Changes for v6:
> > * handle previous bridge for exynos dsi while attaching bridge
> >
> > Changes for v5:
> > * bridge changes to support multi-arch
> > * updated and clear commit messages
> > * add hw_type via plat data
> > * removed unneeded quirk
> > * rebased on linux-next
> >
> > Changes for v4:
> > * include Inki Dae in MAINTAINERS
> > * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> > * update init handling to ensure host init done on first cmd transfer
> >
> > Changes for v3:
> > * fix the mult-arch build
> > * fix dsi host init
> > * updated commit messages
> >
> > Changes for v2:
> > * fix bridge handling
> > * fix dsi host init
> > * correct the commit messages
> >
> > Patch 0001:   Samsung DSIM bridge
> >
> > Patch 0002:   PHY optional
> >
> > Patch 0003:   OF-graph or Child node lookup
> >
> > Patch 0004:   DSI host initialization
> >
> > Patch 0005:   atomic check
> >
> > Patch 0006:   PMS_P offset via plat data
> >
> > Patch 0007:   atomic_get_input_bus_fmts
> >
> > Patch 0008:   input_bus_flags
> >
> > Patch 0009:   document fsl,imx8mm-mipi-dsim
> >
> > Patch 0010:   add i.MX8MM DSIM support
> >
> > Tested in Engicam i.Core MX8M Mini SoM.
>
> This finally doesn't break Exynos DSI. :) Feel free to add:
>
> Acked-by: Marek Szyprowski
>
> Tested-by: Marek Szyprowski
>
> The next step would be to merge Dave's patchset and remove the hacks
> added here and there. Otherwise we will end up adding even more hacks soon.

I've some concerns about one of those patches, I will try to comment
on that patch in mailing list or will send updated changes on top of
those.

Thanks,
Jagan.

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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Tim Harvey]

On Wed, Oct 5, 2022 at 1:51 PM Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
>
> Hi Jagan,
>
> On 05.10.2022 17:12, Jagan Teki wrote:
> > This series supports common bridge support for Samsung MIPI DSIM
> > which is used in Exynos and i.MX8MM SoC's.
> >
> > The final bridge supports both the Exynos and i.MX8MM DSI devices.
> >
> > Changes for v7:
> > * fix the drm bridge attach chain for exynos drm dsi driver
> > * fix the hw_type checking logic
> >
> > Changes for v6:
> > * handle previous bridge for exynos dsi while attaching bridge
> >
> > Changes for v5:
> > * bridge changes to support multi-arch
> > * updated and clear commit messages
> > * add hw_type via plat data
> > * removed unneeded quirk
> > * rebased on linux-next
> >
> > Changes for v4:
> > * include Inki Dae in MAINTAINERS
> > * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> > * update init handling to ensure host init done on first cmd transfer
> >
> > Changes for v3:
> > * fix the mult-arch build
> > * fix dsi host init
> > * updated commit messages
> >
> > Changes for v2:
> > * fix bridge handling
> > * fix dsi host init
> > * correct the commit messages
> >
> > Patch 0001:   Samsung DSIM bridge
> >
> > Patch 0002:   PHY optional
> >
> > Patch 0003:   OF-graph or Child node lookup
> >
> > Patch 0004:   DSI host initialization
> >
> > Patch 0005:   atomic check
> >
> > Patch 0006:   PMS_P offset via plat data
> >
> > Patch 0007:   atomic_get_input_bus_fmts
> >
> > Patch 0008:   input_bus_flags
> >
> > Patch 0009:   document fsl,imx8mm-mipi-dsim
> >
> > Patch 0010:   add i.MX8MM DSIM support
> >
> > Tested in Engicam i.Core MX8M Mini SoM.
>
> This finally doesn't break Exynos DSI. :) Feel free to add:
>
> Acked-by: Marek Szyprowski
>
> Tested-by: Marek Szyprowski
>
> The next step would be to merge Dave's patchset and remove the hacks
> added here and there. Otherwise we will end up adding even more hacks soon.

Jagan,

I've also tested this latest series with a Gateworks
imx8mm-venice-gw73xx-0x with a RaspberryPi MIPI DSI compatible DFR0550
display with the following dt overlay:

/dts-v1/;
/plugin/;

&{/} {
        compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";

        panel {
                compatible = "powertip,ph800480t013-idf02";
                power-supply = <&attiny>;
                backlight = <&attiny>;

                port {
                        panel_out_bridge: endpoint {
                                remote-endpoint = <&bridge_out_panel>;
                        };
                };
        };
};

&i2c3 {
        #address-cells = <1>;
        #size-cells = <0>;

        attiny: regulator@45 {
                compatible = "raspberrypi,7inch-touchscreen-panel-regulator";
                reg = <0x45>;
        };
};

&dsi {
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";

        bridge@0 {
                compatible = "toshiba,tc358762";
                reg = <0>;
                vddc-supply = <&attiny>;
                status = "okay";

                ports {
                        #address-cells = <1>;
                        #size-cells = <0>;

                        port@0 {
                                reg = <0>;
                                bridge_in_dsi: endpoint {
                                        remote-endpoint = <&dsi_out_bridge>;

                                };
                        };

                        port@1 {
                                reg = <1>;
                                bridge_out_panel: endpoint {
                                        remote-endpoint = <&panel_out_bridge>;
                                };
                        };
                };
        };

        ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@1 {
                        reg = <1>;

                        dsi_out_bridge: endpoint {
                                remote-endpoint = <&bridge_in_dsi>;
                        };
                };
        };
};

&lcdif {
        status = "okay";
};


Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-gw73xx-0x

Thanks for all your work on this!

Best Regards,

Tim



>
> > Repo:
> > https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v7
> >
> > Any inputs?
> > Jagan.
> >
> > Jagan Teki (10):
> >    drm: bridge: Add Samsung DSIM bridge driver
> >    drm: bridge: samsung-dsim: Lookup OF-graph or Child node devices
> >    drm: bridge: samsung-dsim: Mark PHY as optional
> >    drm: bridge: samsung-dsim: Handle proper DSI host initialization
> >    drm: bridge: samsung-dsim: Add atomic_check
> >    drm: bridge: samsung-dsim: Add platform PLL_P (PMS_P) offset
> >    drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts
> >    drm: bridge: samsung-dsim: Add input_bus_flags
> >    dt-bindings: display: exynos: dsim: Add NXP i.MX8MM support
> >    drm: bridge: samsung-dsim: Add i.MX8MM support
> >
> >   .../bindings/display/exynos/exynos_dsim.txt   |    1 +
> >   MAINTAINERS                                   |    9 +
> >   drivers/gpu/drm/bridge/Kconfig                |   12 +
> >   drivers/gpu/drm/bridge/Makefile               |    1 +
> >   drivers/gpu/drm/bridge/samsung-dsim.c         | 1856 +++++++++++++++++
> >   drivers/gpu/drm/exynos/Kconfig                |    1 +
> >   drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1766 +---------------
> >   include/drm/bridge/samsung-dsim.h             |  115 +
> >   8 files changed, 2108 insertions(+), 1653 deletions(-)
> >   create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
> >   create mode 100644 include/drm/bridge/samsung-dsim.h
> >
> Best regards
> --
> Marek Szyprowski, PhD
> Samsung R&D Institute Poland
>

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Re: [PATCH v7 05/10] drm: bridge: samsung-dsim: Add atomic_check

[Marek Vasut]

On 10/5/22 17:13, Jagan Teki wrote:
> Look like an explicit fixing up of mode_flags is required for DSIM IP
> present in i.MX8M Mini/Nano SoCs.
> 
> At least the LCDIF + DSIM needs active low sync polarities in order
> to correlate the correct sync flags of the surrounding components in
> the chain to make sure the whole pipeline can work properly.
> 
> On the other hand the i.MX 8M Mini Applications Processor Reference Manual,
> Rev. 3, 11/2020 says.
> "13.6.3.5.2 RGB interface
>   Vsync, Hsync, and VDEN are active high signals."
> 
> No clear evidence about whether it can be documentation issues or
> something, so added a comment FIXME for this and updated the active low
> sync polarities using SAMSUNG_DSIM_TYPE_IMX8MM hw_type.

[...]

> +static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
> +				     struct drm_bridge_state *bridge_state,
> +				     struct drm_crtc_state *crtc_state,
> +				     struct drm_connector_state *conn_state)
> +{
> +	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
> +	struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
> +
> +	if (dsi->plat_data->hw_type == SAMSUNG_DSIM_TYPE_IMX8MM) {
> +		/**
> +		 * FIXME:
> +		 * At least LCDIF + DSIM needs active low sync,
> +		 * but i.MX 8M Mini Applications Processor Reference Manual,
> +		 * Rev. 3, 11/2020 says
> +		 *
> +		 * 13.6.3.5.2 RGB interface
> +		 * Vsync, Hsync, and VDEN are active high signals.
> +		 */
> +		adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> +		adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> +	}

It would be good to explain what exactly is going on here in the 
comment, the comment says "Vsync, Hsync, and VDEN are active high 
signals." and the code below does exact opposite and sets NxSYNC flags.

Yes, the MX8MM/MN does need HS/VS/DE active LOW, it is a quirk of that 
MXSFB-DSIM glue logic. The MX8MP needs the exact opposite on all three, 
active HIGH.

It would also be good to mention both MX8MM and MX8MN are affected, not 
only MX8MM.

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Re: [PATCH v7 10/10] drm: bridge: samsung-dsim: Add i.MX8MM support

[Marek Vasut]

On 10/5/22 17:13, Jagan Teki wrote:

[...]

> +static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
> +	.reg_ofs = exynos5433_reg_ofs,
> +	.plltmr_reg = 0xa0,
> +	.has_clklane_stop = 1,
> +	.num_clks = 2,
> +	.max_freq = 2100,
> +	.wait_for_reset = 0,
> +	.num_bits_resol = 12,
> +	/**

Should this really be kerneldoc style /** comment or plain /* comment ?
If the later, please fix globally, there are multiple such FIXME comments.

> +	 * FIXME:
> +	 * Offset value used from downstream drivers/gpu/drm/bridge/sec-dsim.c
> +	 * remove this comment if it is true else update the logic.
> +	 */
> +	.pll_p_offset = 14,
> +	.reg_values = imx8mm_dsim_reg_values,
> +};

[...]

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Re: [PATCH v7 08/10] drm: bridge: samsung-dsim: Add input_bus_flags

[Marek Vasut]

On 10/5/22 17:13, Jagan Teki wrote:

[...]

> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index f714e49c1eab..f5cd80641cea 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -1601,6 +1601,10 @@ static const struct samsung_dsim_host_ops samsung_dsim_generic_host_ops = {
>   	.unregister_host = samsung_dsim_unregister_host,
>   };
>   
> +static const struct drm_bridge_timings samsung_dsim_bridge_timings = {
> +	.input_bus_flags = DRM_BUS_FLAG_DE_LOW,
> +};
> +
>   int samsung_dsim_probe(struct platform_device *pdev)
>   {
>   	struct device *dev = &pdev->dev;
> @@ -1681,6 +1685,7 @@ int samsung_dsim_probe(struct platform_device *pdev)
>   
>   	dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
>   	dsi->bridge.of_node = dev->of_node;
> +	dsi->bridge.timings = &samsung_dsim_bridge_timings;

Is this really valid on Exynos too ?

My impression is that the DE_LOW requirement is only needed for MX8MM/MN 
where the LCDIF-DSIM glue logic inverts the HS/VS/DE signals, while on 
all other platforms (at least MX8MP) the inversion does not take place, 
so DE is really active HIGH there.

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Re: [PATCH v7 01/10] drm: bridge: Add Samsung DSIM bridge driver

[Marek Vasut]

On 10/5/22 17:13, Jagan Teki wrote:
> Samsung MIPI DSIM controller is common DSI IP that can be used in various
> SoCs like Exynos, i.MX8M Mini/Nano.
> 
> In order to access this DSI controller between various platform SoCs,
> the ideal way to incorporate this in the drm stack is via the drm bridge
> driver.
> 
> This patch is trying to differentiate platform-specific and bridge driver
> code by maintaining exynos platform glue code in exynos_drm_dsi.c driver
> and common bridge driver code in samsung-dsim.c providing that the new
> platform-specific glue should be supported in the bridge driver, unlike
> exynos platform drm drivers.
> 
> - Add samsung_dsim_plat_data for keeping platform-specific attributes like
>    host_ops, irq_ops, and hw_type.
> 
> - Initialize the plat_data hooks for exynos platform in exynos_drm_dsi.c.
> 
> - samsung_dsim_probe is the common probe call across exynos_drm_dsi.c and
>    samsung-dsim.c.
> 
> - plat_data hooks like host_ops and irq_ops are invoked during the
>    respective bridge call chains.

Maybe the Subject should say "Split ... driver" or "Move ... driver" , 
since it is not adding a new driver here ?

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Re: [PATCH v7 02/10] drm: bridge: samsung-dsim: Lookup OF-graph or Child node devices

[Marek Vasut]

On 10/5/22 17:13, Jagan Teki wrote:
> The child devices in MIPI DSI can be binding with OF-graph
> and also via child nodes.
> 
> The OF-graph interface represents the child devices via
> remote and associated endpoint numbers like
> 
> dsi {
>     compatible = "fsl,imx8mm-mipi-dsim";
> 
>     ports {
> 	port@0 {
> 	     reg = <0>;
> 
> 	     dsi_in_lcdif: endpoint@0 {
> 		  reg = <0>;
> 		  remote-endpoint = <&lcdif_out_dsi>;
> 	     };
> 	};
> 
> 	port@1 {
> 	     reg = <1>;
> 
> 	     dsi_out_bridge: endpoint {
> 		  remote-endpoint = <&bridge_in_dsi>;
> 	     };
> 	};
> };
> 
> The child node interface represents the child devices via
> conventional child nodes on given DSI parent like
> 
> dsi {
>     compatible = "samsung,exynos5433-mipi-dsi";
> 
>     ports {
>          port@0 {
>               reg = <0>;
> 
>               dsi_to_mic: endpoint {
>                    remote-endpoint = <&mic_to_dsi>;
>               };
>          };
>     };
> 
>     panel@0 {
>          reg = <0>;
>     };
> };
> 
> As Samsung DSIM bridge is common DSI IP across all Exynos DSI
> and NXP i.MX8M host controllers, this patch adds support to
> lookup the child devices whether its bindings on the associated
> host represent OF-graph or child node interfaces.

This looks like a good candidate for common/helper code which can be 
reused by other similar drivers.

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Re: [PATCH v7 03/10] drm: bridge: samsung-dsim: Mark PHY as optional

[Marek Vasut]

On 10/5/22 17:13, Jagan Teki wrote:
> In i.MX8M Mini/Nano SoC the DSI Phy requires a MIPI DPHY bit

8M Plus too.

> to reset in order to activate the PHY and that can be done via
> upstream i.MX8M blk-ctrl driver.
> 
> So, mark the phy get as optional.

Reviewed-by: Marek Vasut <marex@denx.de>

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Re: [PATCH v7 06/10] drm: bridge: samsung-dsim: Add platform PLL_P (PMS_P) offset

[Marek Vasut]

On 10/5/22 17:13, Jagan Teki wrote:
> Look like PLL PMS_P offset value varies between platforms that have
> Samsung DSIM IP.
> 
> However, there is no clear evidence for it as both Exynos and i.MX
> 8M Mini Application Processor Reference Manual is still referring
> the PMS_P offset as 13.
> 
> The offset 13 is not working for i.MX8M Mini SoCs but the downstream
> NXP sec-dsim.c driver is using offset 14 for i.MX8M Mini SoC platforms
> [1] [2].
> 
> PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P()
> with offset 13 and then an additional offset of one bit added in
> sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS().
> 
> Not sure whether it is reference manual documentation or something else
> but this patch trusts the downstream code and handle PLL_P offset via
> platform driver data so-that imx8mm driver data shall use pll_p_offset
> to 14.
> 
> [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n210
> [2] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211

You also add to the commit message that all of 8M Mini/Nano/Plus have 
P=14 , unlike Exynos. It also seems like the PLL in the DSIM and the 
clock PLLs in the 8M are the same design from Samsung.

Reviewed-by: Marek Vasut <marex@denx.de>

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Re: [PATCH v7 07/10] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts

[Marek Vasut]

On 10/5/22 17:13, Jagan Teki wrote:

[...]

> @@ -1321,6 +1322,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
>   	pm_runtime_put_sync(dsi->dev);
>   }
>   
> +#define MAX_INPUT_SEL_FORMATS	1
> +
> +static u32 *
> +samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> +				       struct drm_bridge_state *bridge_state,
> +				       struct drm_crtc_state *crtc_state,
> +				       struct drm_connector_state *conn_state,
> +				       u32 output_fmt,
> +				       unsigned int *num_input_fmts)
> +{
> +	u32 *input_fmts;
> +
> +	*num_input_fmts = 0;
> +
> +	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
> +			     GFP_KERNEL);
> +	if (!input_fmts)
> +		return NULL;
> +
> +	/* This is the DSI-end bus format */
> +	input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
> +	*num_input_fmts = 1;

Is this the only supported format ? NXP AN13573 lists the following:

i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
3.7.4 Pixel formats
Table 14. DSI pixel packing formats

Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2
Packed Pixel Stream, 24-bit YCbCr, 4:2:2
Packed Pixel Stream, 16-bit YCbCr, 4:2:2
Packed Pixel Stream, 30-bit RGB, 10-10-10
Packed Pixel Stream, 36-bit RGB, 12-12-12
Packed Pixel Stream, 12-bit YCbCr, 4:2:0
Packed Pixel Stream, 16-bit RGB, 5-6-5
Packed Pixel Stream, 18-bit RGB, 6-6-6
Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6
Packed Pixel Stream, 24-bit RGB, 8-8-8 Format

The MX8MM/MN LCDIF can generate all of those RGB formats , the MX8MP 
LCDIFv3 can also generate the 16bit YCbCr .

It seems there should be more formats here.

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Re: [PATCH v7 09/10] dt-bindings: display: exynos: dsim: Add NXP i.MX8MM support

[Marek Vasut]

On 10/5/22 17:13, Jagan Teki wrote:
> Samsung MIPI DSIM bridge can also be found in i.MX8MM SoC.
> 
> Add dt-bingings for it.
> 
> v7, v6, v5, v4:
> * none
> 
> v3:
> * collect Rob Acked-by
> 
> v2:
> * updated comments
> 
> v1:
> * new patch
> 
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>   Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> index be377786e8cd..8efcf4728e0b 100644
> --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> @@ -7,6 +7,7 @@ Required properties:
>   		"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
>   		"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
>   		"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
> +		"fsl,imx8mm-mipi-dsim" /* for i.MX8M Mini SoCs */

This also covers Nano, can you add it into the comment ?

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Re: [PATCH v7 01/10] drm: bridge: Add Samsung DSIM bridge driver

[Jagan Teki]

On Sun, Oct 16, 2022 at 3:16 AM Marek Vasut <marex@denx.de> wrote:
>
> On 10/5/22 17:13, Jagan Teki wrote:
> > Samsung MIPI DSIM controller is common DSI IP that can be used in various
> > SoCs like Exynos, i.MX8M Mini/Nano.
> >
> > In order to access this DSI controller between various platform SoCs,
> > the ideal way to incorporate this in the drm stack is via the drm bridge
> > driver.
> >
> > This patch is trying to differentiate platform-specific and bridge driver
> > code by maintaining exynos platform glue code in exynos_drm_dsi.c driver
> > and common bridge driver code in samsung-dsim.c providing that the new
> > platform-specific glue should be supported in the bridge driver, unlike
> > exynos platform drm drivers.
> >
> > - Add samsung_dsim_plat_data for keeping platform-specific attributes like
> >    host_ops, irq_ops, and hw_type.
> >
> > - Initialize the plat_data hooks for exynos platform in exynos_drm_dsi.c.
> >
> > - samsung_dsim_probe is the common probe call across exynos_drm_dsi.c and
> >    samsung-dsim.c.
> >
> > - plat_data hooks like host_ops and irq_ops are invoked during the
> >    respective bridge call chains.
>
> Maybe the Subject should say "Split ... driver" or "Move ... driver" ,
> since it is not adding a new driver here ?

Though it is not added a completely new driver, it is adding more
infrastructure platform code to be compatible with both Exynos and
i.MX8M. This is the prime reason for adding that commit head and
explaining the same in the commit body.

Jagan.

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Re: [PATCH v7 02/10] drm: bridge: samsung-dsim: Lookup OF-graph or Child node devices

[Jagan Teki]

On Sun, Oct 16, 2022 at 3:18 AM Marek Vasut <marex@denx.de> wrote:
>
> On 10/5/22 17:13, Jagan Teki wrote:
> > The child devices in MIPI DSI can be binding with OF-graph
> > and also via child nodes.
> >
> > The OF-graph interface represents the child devices via
> > remote and associated endpoint numbers like
> >
> > dsi {
> >     compatible = "fsl,imx8mm-mipi-dsim";
> >
> >     ports {
> >       port@0 {
> >            reg = <0>;
> >
> >            dsi_in_lcdif: endpoint@0 {
> >                 reg = <0>;
> >                 remote-endpoint = <&lcdif_out_dsi>;
> >            };
> >       };
> >
> >       port@1 {
> >            reg = <1>;
> >
> >            dsi_out_bridge: endpoint {
> >                 remote-endpoint = <&bridge_in_dsi>;
> >            };
> >       };
> > };
> >
> > The child node interface represents the child devices via
> > conventional child nodes on given DSI parent like
> >
> > dsi {
> >     compatible = "samsung,exynos5433-mipi-dsi";
> >
> >     ports {
> >          port@0 {
> >               reg = <0>;
> >
> >               dsi_to_mic: endpoint {
> >                    remote-endpoint = <&mic_to_dsi>;
> >               };
> >          };
> >     };
> >
> >     panel@0 {
> >          reg = <0>;
> >     };
> > };
> >
> > As Samsung DSIM bridge is common DSI IP across all Exynos DSI
> > and NXP i.MX8M host controllers, this patch adds support to
> > lookup the child devices whether its bindings on the associated
> > host represent OF-graph or child node interfaces.
>
> This looks like a good candidate for common/helper code which can be
> reused by other similar drivers.

Tried that but unfortunately, it cannot hold to handle things in a generic way.
80253168dbfd ("drm: of: Lookup if child node has panel or bridge")

Jagan.

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Re: [PATCH v7 05/10] drm: bridge: samsung-dsim: Add atomic_check

[Jagan Teki]

On Sun, Oct 16, 2022 at 2:53 AM Marek Vasut <marex@denx.de> wrote:
>
> On 10/5/22 17:13, Jagan Teki wrote:
> > Look like an explicit fixing up of mode_flags is required for DSIM IP
> > present in i.MX8M Mini/Nano SoCs.
> >
> > At least the LCDIF + DSIM needs active low sync polarities in order
> > to correlate the correct sync flags of the surrounding components in
> > the chain to make sure the whole pipeline can work properly.
> >
> > On the other hand the i.MX 8M Mini Applications Processor Reference Manual,
> > Rev. 3, 11/2020 says.
> > "13.6.3.5.2 RGB interface
> >   Vsync, Hsync, and VDEN are active high signals."
> >
> > No clear evidence about whether it can be documentation issues or
> > something, so added a comment FIXME for this and updated the active low
> > sync polarities using SAMSUNG_DSIM_TYPE_IMX8MM hw_type.
>
> [...]
>
> > +static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
> > +                                  struct drm_bridge_state *bridge_state,
> > +                                  struct drm_crtc_state *crtc_state,
> > +                                  struct drm_connector_state *conn_state)
> > +{
> > +     struct samsung_dsim *dsi = bridge_to_dsi(bridge);
> > +     struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
> > +
> > +     if (dsi->plat_data->hw_type == SAMSUNG_DSIM_TYPE_IMX8MM) {
> > +             /**
> > +              * FIXME:
> > +              * At least LCDIF + DSIM needs active low sync,
> > +              * but i.MX 8M Mini Applications Processor Reference Manual,
> > +              * Rev. 3, 11/2020 says
> > +              *
> > +              * 13.6.3.5.2 RGB interface
> > +              * Vsync, Hsync, and VDEN are active high signals.
> > +              */
> > +             adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> > +             adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> > +     }
>
> It would be good to explain what exactly is going on here in the
> comment, the comment says "Vsync, Hsync, and VDEN are active high
> signals." and the code below does exact opposite and sets NxSYNC flags.
>
> Yes, the MX8MM/MN does need HS/VS/DE active LOW, it is a quirk of that
> MXSFB-DSIM glue logic. The MX8MP needs the exact opposite on all three,
> active HIGH.

This is what exactly is mentioned in the comments.

2nd line mentioned the active low of signals.
> > +              * At least LCDIF + DSIM needs active low sync,

from 3rd line onwards it mentioned what reference manual is referring

Not quite understand what is misleading here.

>
> It would also be good to mention both MX8MM and MX8MN are affected, not
> only MX8MM.

I think I can do this once I refer to the MX8MN manual.

Jagan.

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Re: [PATCH v7 07/10] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts

[Jagan Teki]

On Sun, Oct 16, 2022 at 3:31 AM Marek Vasut <marex@denx.de> wrote:
>
> On 10/5/22 17:13, Jagan Teki wrote:
>
> [...]
>
> > @@ -1321,6 +1322,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
> >       pm_runtime_put_sync(dsi->dev);
> >   }
> >
> > +#define MAX_INPUT_SEL_FORMATS        1
> > +
> > +static u32 *
> > +samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> > +                                    struct drm_bridge_state *bridge_state,
> > +                                    struct drm_crtc_state *crtc_state,
> > +                                    struct drm_connector_state *conn_state,
> > +                                    u32 output_fmt,
> > +                                    unsigned int *num_input_fmts)
> > +{
> > +     u32 *input_fmts;
> > +
> > +     *num_input_fmts = 0;
> > +
> > +     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
> > +                          GFP_KERNEL);
> > +     if (!input_fmts)
> > +             return NULL;
> > +
> > +     /* This is the DSI-end bus format */
> > +     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
> > +     *num_input_fmts = 1;
>
> Is this the only supported format ? NXP AN13573 lists the following:

At least it only formats I have tested on my panel.

>
> i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
> 3.7.4 Pixel formats
> Table 14. DSI pixel packing formats
>
> Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2
> Packed Pixel Stream, 24-bit YCbCr, 4:2:2
> Packed Pixel Stream, 16-bit YCbCr, 4:2:2
> Packed Pixel Stream, 30-bit RGB, 10-10-10
> Packed Pixel Stream, 36-bit RGB, 12-12-12
> Packed Pixel Stream, 12-bit YCbCr, 4:2:0
> Packed Pixel Stream, 16-bit RGB, 5-6-5
> Packed Pixel Stream, 18-bit RGB, 6-6-6
> Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6
> Packed Pixel Stream, 24-bit RGB, 8-8-8 Format
>
> The MX8MM/MN LCDIF can generate all of those RGB formats , the MX8MP
> LCDIFv3 can also generate the 16bit YCbCr .
>
> It seems there should be more formats here.

The idea of this patch is to support the default format first, and can
possibly add future patches with the addition of new formats.

Thanks,
Jagan.

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Re: [PATCH v7 01/10] drm: bridge: Add Samsung DSIM bridge driver

[Marek Vasut]

On 10/17/22 04:49, Jagan Teki wrote:
> On Sun, Oct 16, 2022 at 3:16 AM Marek Vasut <marex@denx.de> wrote:
>>
>> On 10/5/22 17:13, Jagan Teki wrote:
>>> Samsung MIPI DSIM controller is common DSI IP that can be used in various
>>> SoCs like Exynos, i.MX8M Mini/Nano.
>>>
>>> In order to access this DSI controller between various platform SoCs,
>>> the ideal way to incorporate this in the drm stack is via the drm bridge
>>> driver.
>>>
>>> This patch is trying to differentiate platform-specific and bridge driver
>>> code by maintaining exynos platform glue code in exynos_drm_dsi.c driver
>>> and common bridge driver code in samsung-dsim.c providing that the new
>>> platform-specific glue should be supported in the bridge driver, unlike
>>> exynos platform drm drivers.
>>>
>>> - Add samsung_dsim_plat_data for keeping platform-specific attributes like
>>>     host_ops, irq_ops, and hw_type.
>>>
>>> - Initialize the plat_data hooks for exynos platform in exynos_drm_dsi.c.
>>>
>>> - samsung_dsim_probe is the common probe call across exynos_drm_dsi.c and
>>>     samsung-dsim.c.
>>>
>>> - plat_data hooks like host_ops and irq_ops are invoked during the
>>>     respective bridge call chains.
>>
>> Maybe the Subject should say "Split ... driver" or "Move ... driver" ,
>> since it is not adding a new driver here ?
> 
> Though it is not added a completely new driver, it is adding more
> infrastructure platform code to be compatible with both Exynos and
> i.MX8M. This is the prime reason for adding that commit head and
> explaining the same in the commit body.

Diffstat looks like this:

  drivers/gpu/drm/bridge/samsung-dsim.c   | 1703 ++++++++++++++++++++++
  drivers/gpu/drm/exynos/Kconfig          |    1 +
  drivers/gpu/drm/exynos/exynos_drm_dsi.c | 1766 ++---------------------
  include/drm/bridge/samsung-dsim.h       |  113 ++
  7 files changed, 1952 insertions(+), 1653 deletions(-)

Looks to me like most of the code is just moved from existing driver in 
this patch.

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Re: [PATCH v7 05/10] drm: bridge: samsung-dsim: Add atomic_check

[Marek Vasut]

On 10/17/22 05:54, Jagan Teki wrote:
> On Sun, Oct 16, 2022 at 2:53 AM Marek Vasut <marex@denx.de> wrote:
>>
>> On 10/5/22 17:13, Jagan Teki wrote:
>>> Look like an explicit fixing up of mode_flags is required for DSIM IP
>>> present in i.MX8M Mini/Nano SoCs.
>>>
>>> At least the LCDIF + DSIM needs active low sync polarities in order
>>> to correlate the correct sync flags of the surrounding components in
>>> the chain to make sure the whole pipeline can work properly.
>>>
>>> On the other hand the i.MX 8M Mini Applications Processor Reference Manual,
>>> Rev. 3, 11/2020 says.
>>> "13.6.3.5.2 RGB interface
>>>    Vsync, Hsync, and VDEN are active high signals."
>>>
>>> No clear evidence about whether it can be documentation issues or
>>> something, so added a comment FIXME for this and updated the active low
>>> sync polarities using SAMSUNG_DSIM_TYPE_IMX8MM hw_type.
>>
>> [...]
>>
>>> +static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
>>> +                                  struct drm_bridge_state *bridge_state,
>>> +                                  struct drm_crtc_state *crtc_state,
>>> +                                  struct drm_connector_state *conn_state)
>>> +{
>>> +     struct samsung_dsim *dsi = bridge_to_dsi(bridge);
>>> +     struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
>>> +
>>> +     if (dsi->plat_data->hw_type == SAMSUNG_DSIM_TYPE_IMX8MM) {
>>> +             /**
>>> +              * FIXME:
>>> +              * At least LCDIF + DSIM needs active low sync,
>>> +              * but i.MX 8M Mini Applications Processor Reference Manual,
>>> +              * Rev. 3, 11/2020 says
>>> +              *
>>> +              * 13.6.3.5.2 RGB interface
>>> +              * Vsync, Hsync, and VDEN are active high signals.
>>> +              */
>>> +             adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
>>> +             adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
>>> +     }
>>
>> It would be good to explain what exactly is going on here in the
>> comment, the comment says "Vsync, Hsync, and VDEN are active high
>> signals." and the code below does exact opposite and sets NxSYNC flags.
>>
>> Yes, the MX8MM/MN does need HS/VS/DE active LOW, it is a quirk of that
>> MXSFB-DSIM glue logic. The MX8MP needs the exact opposite on all three,
>> active HIGH.
> 
> This is what exactly is mentioned in the comments.
> 
> 2nd line mentioned the active low of signals.
>>> +              * At least LCDIF + DSIM needs active low sync,
> 
> from 3rd line onwards it mentioned what reference manual is referring
> 
> Not quite understand what is misleading here.

This part:
"
+  * Vsync, Hsync, and VDEN are active high signals.
+  */
+  adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
"

Comment claims the signals are active high by quoting datasheet, and 
then sets the exact opposite on next line of code.

Have a look at this patch, I updated the comment there for MX8MP too:
[PATCH] drm: bridge: samsung-dsim: Add i.MX8M Plus support

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Re: [PATCH v7 07/10] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts

[Marek Vasut]

On 10/17/22 05:58, Jagan Teki wrote:
> On Sun, Oct 16, 2022 at 3:31 AM Marek Vasut <marex@denx.de> wrote:
>>
>> On 10/5/22 17:13, Jagan Teki wrote:
>>
>> [...]
>>
>>> @@ -1321,6 +1322,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
>>>        pm_runtime_put_sync(dsi->dev);
>>>    }
>>>
>>> +#define MAX_INPUT_SEL_FORMATS        1
>>> +
>>> +static u32 *
>>> +samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>>> +                                    struct drm_bridge_state *bridge_state,
>>> +                                    struct drm_crtc_state *crtc_state,
>>> +                                    struct drm_connector_state *conn_state,
>>> +                                    u32 output_fmt,
>>> +                                    unsigned int *num_input_fmts)
>>> +{
>>> +     u32 *input_fmts;
>>> +
>>> +     *num_input_fmts = 0;
>>> +
>>> +     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
>>> +                          GFP_KERNEL);
>>> +     if (!input_fmts)
>>> +             return NULL;
>>> +
>>> +     /* This is the DSI-end bus format */
>>> +     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
>>> +     *num_input_fmts = 1;
>>
>> Is this the only supported format ? NXP AN13573 lists the following:
> 
> At least it only formats I have tested on my panel.
> 
>>
>> i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
>> 3.7.4 Pixel formats
>> Table 14. DSI pixel packing formats
>>
>> Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2
>> Packed Pixel Stream, 24-bit YCbCr, 4:2:2
>> Packed Pixel Stream, 16-bit YCbCr, 4:2:2
>> Packed Pixel Stream, 30-bit RGB, 10-10-10
>> Packed Pixel Stream, 36-bit RGB, 12-12-12
>> Packed Pixel Stream, 12-bit YCbCr, 4:2:0
>> Packed Pixel Stream, 16-bit RGB, 5-6-5
>> Packed Pixel Stream, 18-bit RGB, 6-6-6
>> Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6
>> Packed Pixel Stream, 24-bit RGB, 8-8-8 Format
>>
>> The MX8MM/MN LCDIF can generate all of those RGB formats , the MX8MP
>> LCDIFv3 can also generate the 16bit YCbCr .
>>
>> It seems there should be more formats here.
> 
> The idea of this patch is to support the default format first, and can
> possibly add future patches with the addition of new formats.

Since you already know about the list, please add all the formats, so we 
won't be adding known broken code first, only to fix it later.

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Re: [PATCH v7 01/10] drm: bridge: Add Samsung DSIM bridge driver

[Jagan Teki]

On Mon, Oct 17, 2022 at 12:49 PM Marek Vasut <marex@denx.de> wrote:
>
> On 10/17/22 04:49, Jagan Teki wrote:
> > On Sun, Oct 16, 2022 at 3:16 AM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 10/5/22 17:13, Jagan Teki wrote:
> >>> Samsung MIPI DSIM controller is common DSI IP that can be used in various
> >>> SoCs like Exynos, i.MX8M Mini/Nano.
> >>>
> >>> In order to access this DSI controller between various platform SoCs,
> >>> the ideal way to incorporate this in the drm stack is via the drm bridge
> >>> driver.
> >>>
> >>> This patch is trying to differentiate platform-specific and bridge driver
> >>> code by maintaining exynos platform glue code in exynos_drm_dsi.c driver
> >>> and common bridge driver code in samsung-dsim.c providing that the new
> >>> platform-specific glue should be supported in the bridge driver, unlike
> >>> exynos platform drm drivers.
> >>>
> >>> - Add samsung_dsim_plat_data for keeping platform-specific attributes like
> >>>     host_ops, irq_ops, and hw_type.
> >>>
> >>> - Initialize the plat_data hooks for exynos platform in exynos_drm_dsi.c.
> >>>
> >>> - samsung_dsim_probe is the common probe call across exynos_drm_dsi.c and
> >>>     samsung-dsim.c.
> >>>
> >>> - plat_data hooks like host_ops and irq_ops are invoked during the
> >>>     respective bridge call chains.
> >>
> >> Maybe the Subject should say "Split ... driver" or "Move ... driver" ,
> >> since it is not adding a new driver here ?
> >
> > Though it is not added a completely new driver, it is adding more
> > infrastructure platform code to be compatible with both Exynos and
> > i.MX8M. This is the prime reason for adding that commit head and
> > explaining the same in the commit body.
>
> Diffstat looks like this:
>
>   drivers/gpu/drm/bridge/samsung-dsim.c   | 1703 ++++++++++++++++++++++
>   drivers/gpu/drm/exynos/Kconfig          |    1 +
>   drivers/gpu/drm/exynos/exynos_drm_dsi.c | 1766 ++---------------------
>   include/drm/bridge/samsung-dsim.h       |  113 ++
>   7 files changed, 1952 insertions(+), 1653 deletions(-)
>
> Looks to me like most of the code is just moved from existing driver in
> this patch.

Yeah, as I explained (from commit) it is moved, updated, and written
the plat code. How about this head?

"drm: bridge: Add Samsung DSIM bridge (Split from exynos_drm_dsi)"

Jagan.

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Re: [PATCH v7 05/10] drm: bridge: samsung-dsim: Add atomic_check

[Jagan Teki]

On Mon, Oct 17, 2022 at 12:53 PM Marek Vasut <marex@denx.de> wrote:
>
> On 10/17/22 05:54, Jagan Teki wrote:
> > On Sun, Oct 16, 2022 at 2:53 AM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 10/5/22 17:13, Jagan Teki wrote:
> >>> Look like an explicit fixing up of mode_flags is required for DSIM IP
> >>> present in i.MX8M Mini/Nano SoCs.
> >>>
> >>> At least the LCDIF + DSIM needs active low sync polarities in order
> >>> to correlate the correct sync flags of the surrounding components in
> >>> the chain to make sure the whole pipeline can work properly.
> >>>
> >>> On the other hand the i.MX 8M Mini Applications Processor Reference Manual,
> >>> Rev. 3, 11/2020 says.
> >>> "13.6.3.5.2 RGB interface
> >>>    Vsync, Hsync, and VDEN are active high signals."
> >>>
> >>> No clear evidence about whether it can be documentation issues or
> >>> something, so added a comment FIXME for this and updated the active low
> >>> sync polarities using SAMSUNG_DSIM_TYPE_IMX8MM hw_type.
> >>
> >> [...]
> >>
> >>> +static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
> >>> +                                  struct drm_bridge_state *bridge_state,
> >>> +                                  struct drm_crtc_state *crtc_state,
> >>> +                                  struct drm_connector_state *conn_state)
> >>> +{
> >>> +     struct samsung_dsim *dsi = bridge_to_dsi(bridge);
> >>> +     struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
> >>> +
> >>> +     if (dsi->plat_data->hw_type == SAMSUNG_DSIM_TYPE_IMX8MM) {
> >>> +             /**
> >>> +              * FIXME:
> >>> +              * At least LCDIF + DSIM needs active low sync,
> >>> +              * but i.MX 8M Mini Applications Processor Reference Manual,
> >>> +              * Rev. 3, 11/2020 says
> >>> +              *
> >>> +              * 13.6.3.5.2 RGB interface
> >>> +              * Vsync, Hsync, and VDEN are active high signals.
> >>> +              */
> >>> +             adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> >>> +             adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> >>> +     }
> >>
> >> It would be good to explain what exactly is going on here in the
> >> comment, the comment says "Vsync, Hsync, and VDEN are active high
> >> signals." and the code below does exact opposite and sets NxSYNC flags.
> >>
> >> Yes, the MX8MM/MN does need HS/VS/DE active LOW, it is a quirk of that
> >> MXSFB-DSIM glue logic. The MX8MP needs the exact opposite on all three,
> >> active HIGH.
> >
> > This is what exactly is mentioned in the comments.
> >
> > 2nd line mentioned the active low of signals.
> >>> +              * At least LCDIF + DSIM needs active low sync,
> >
> > from 3rd line onwards it mentioned what reference manual is referring
> >
> > Not quite understand what is misleading here.
>
> This part:
> "
> +  * Vsync, Hsync, and VDEN are active high signals.
> +  */
> +  adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
> "
>
> Comment claims the signals are active high by quoting datasheet, and
> then sets the exact opposite on next line of code.

The comment stated what is done first and then gave the datasheet
reference. look this sequence seems confusing, I will recheck and
update the best possible comment.

>
> Have a look at this patch, I updated the comment there for MX8MP too:
> [PATCH] drm: bridge: samsung-dsim: Add i.MX8M Plus support

I will check.

Thanks,
Jagan.

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Re: [PATCH v7 01/10] drm: bridge: Add Samsung DSIM bridge driver

[Marek Vasut]

On 10/17/22 09:43, Jagan Teki wrote:
> On Mon, Oct 17, 2022 at 12:49 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 10/17/22 04:49, Jagan Teki wrote:
>>> On Sun, Oct 16, 2022 at 3:16 AM Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 10/5/22 17:13, Jagan Teki wrote:
>>>>> Samsung MIPI DSIM controller is common DSI IP that can be used in various
>>>>> SoCs like Exynos, i.MX8M Mini/Nano.
>>>>>
>>>>> In order to access this DSI controller between various platform SoCs,
>>>>> the ideal way to incorporate this in the drm stack is via the drm bridge
>>>>> driver.
>>>>>
>>>>> This patch is trying to differentiate platform-specific and bridge driver
>>>>> code by maintaining exynos platform glue code in exynos_drm_dsi.c driver
>>>>> and common bridge driver code in samsung-dsim.c providing that the new
>>>>> platform-specific glue should be supported in the bridge driver, unlike
>>>>> exynos platform drm drivers.
>>>>>
>>>>> - Add samsung_dsim_plat_data for keeping platform-specific attributes like
>>>>>      host_ops, irq_ops, and hw_type.
>>>>>
>>>>> - Initialize the plat_data hooks for exynos platform in exynos_drm_dsi.c.
>>>>>
>>>>> - samsung_dsim_probe is the common probe call across exynos_drm_dsi.c and
>>>>>      samsung-dsim.c.
>>>>>
>>>>> - plat_data hooks like host_ops and irq_ops are invoked during the
>>>>>      respective bridge call chains.
>>>>
>>>> Maybe the Subject should say "Split ... driver" or "Move ... driver" ,
>>>> since it is not adding a new driver here ?
>>>
>>> Though it is not added a completely new driver, it is adding more
>>> infrastructure platform code to be compatible with both Exynos and
>>> i.MX8M. This is the prime reason for adding that commit head and
>>> explaining the same in the commit body.
>>
>> Diffstat looks like this:
>>
>>    drivers/gpu/drm/bridge/samsung-dsim.c   | 1703 ++++++++++++++++++++++
>>    drivers/gpu/drm/exynos/Kconfig          |    1 +
>>    drivers/gpu/drm/exynos/exynos_drm_dsi.c | 1766 ++---------------------
>>    include/drm/bridge/samsung-dsim.h       |  113 ++
>>    7 files changed, 1952 insertions(+), 1653 deletions(-)
>>
>> Looks to me like most of the code is just moved from existing driver in
>> this patch.
> 
> Yeah, as I explained (from commit) it is moved, updated, and written
> the plat code. How about this head?
> 
> "drm: bridge: Add Samsung DSIM bridge (Split from exynos_drm_dsi)"

I disagree with the "Add" part of the Subject, but I'll wait for others' 
opinion here.

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Re: [PATCH v7 01/10] drm: bridge: Add Samsung DSIM bridge driver

[Marek Szyprowski]

Hi,

On 17.10.2022 10:48, Marek Vasut wrote:
> On 10/17/22 09:43, Jagan Teki wrote:
>> On Mon, Oct 17, 2022 at 12:49 PM Marek Vasut <marex@denx.de> wrote:
>>> On 10/17/22 04:49, Jagan Teki wrote:
>>>> On Sun, Oct 16, 2022 at 3:16 AM Marek Vasut <marex@denx.de> wrote:
>>>>>
>>>>> On 10/5/22 17:13, Jagan Teki wrote:
>>>>>> Samsung MIPI DSIM controller is common DSI IP that can be used in 
>>>>>> various
>>>>>> SoCs like Exynos, i.MX8M Mini/Nano.
>>>>>>
>>>>>> In order to access this DSI controller between various platform 
>>>>>> SoCs,
>>>>>> the ideal way to incorporate this in the drm stack is via the drm 
>>>>>> bridge
>>>>>> driver.
>>>>>>
>>>>>> This patch is trying to differentiate platform-specific and 
>>>>>> bridge driver
>>>>>> code by maintaining exynos platform glue code in exynos_drm_dsi.c 
>>>>>> driver
>>>>>> and common bridge driver code in samsung-dsim.c providing that 
>>>>>> the new
>>>>>> platform-specific glue should be supported in the bridge driver, 
>>>>>> unlike
>>>>>> exynos platform drm drivers.
>>>>>>
>>>>>> - Add samsung_dsim_plat_data for keeping platform-specific 
>>>>>> attributes like
>>>>>>      host_ops, irq_ops, and hw_type.
>>>>>>
>>>>>> - Initialize the plat_data hooks for exynos platform in 
>>>>>> exynos_drm_dsi.c.
>>>>>>
>>>>>> - samsung_dsim_probe is the common probe call across 
>>>>>> exynos_drm_dsi.c and
>>>>>>      samsung-dsim.c.
>>>>>>
>>>>>> - plat_data hooks like host_ops and irq_ops are invoked during the
>>>>>>      respective bridge call chains.
>>>>>
>>>>> Maybe the Subject should say "Split ... driver" or "Move ... 
>>>>> driver" ,
>>>>> since it is not adding a new driver here ?
>>>>
>>>> Though it is not added a completely new driver, it is adding more
>>>> infrastructure platform code to be compatible with both Exynos and
>>>> i.MX8M. This is the prime reason for adding that commit head and
>>>> explaining the same in the commit body.
>>>
>>> Diffstat looks like this:
>>>
>>>    drivers/gpu/drm/bridge/samsung-dsim.c   | 1703 
>>> ++++++++++++++++++++++
>>>    drivers/gpu/drm/exynos/Kconfig          |    1 +
>>>    drivers/gpu/drm/exynos/exynos_drm_dsi.c | 1766 
>>> ++---------------------
>>>    include/drm/bridge/samsung-dsim.h       |  113 ++
>>>    7 files changed, 1952 insertions(+), 1653 deletions(-)
>>>
>>> Looks to me like most of the code is just moved from existing driver in
>>> this patch.
>>
>> Yeah, as I explained (from commit) it is moved, updated, and written
>> the plat code. How about this head?
>>
>> "drm: bridge: Add Samsung DSIM bridge (Split from exynos_drm_dsi)"
>
> I disagree with the "Add" part of the Subject, but I'll wait for 
> others' opinion here.

Maybe something like a "Generalize Exynos-DSI DRM driver into a generic 
Samsung DSIM bridge"?

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland


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Re: [PATCH v7 01/10] drm: bridge: Add Samsung DSIM bridge driver

[Jagan Teki]

On Mon, Oct 17, 2022 at 2:31 PM Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
>
> Hi,
>
> On 17.10.2022 10:48, Marek Vasut wrote:
> > On 10/17/22 09:43, Jagan Teki wrote:
> >> On Mon, Oct 17, 2022 at 12:49 PM Marek Vasut <marex@denx.de> wrote:
> >>> On 10/17/22 04:49, Jagan Teki wrote:
> >>>> On Sun, Oct 16, 2022 at 3:16 AM Marek Vasut <marex@denx.de> wrote:
> >>>>>
> >>>>> On 10/5/22 17:13, Jagan Teki wrote:
> >>>>>> Samsung MIPI DSIM controller is common DSI IP that can be used in
> >>>>>> various
> >>>>>> SoCs like Exynos, i.MX8M Mini/Nano.
> >>>>>>
> >>>>>> In order to access this DSI controller between various platform
> >>>>>> SoCs,
> >>>>>> the ideal way to incorporate this in the drm stack is via the drm
> >>>>>> bridge
> >>>>>> driver.
> >>>>>>
> >>>>>> This patch is trying to differentiate platform-specific and
> >>>>>> bridge driver
> >>>>>> code by maintaining exynos platform glue code in exynos_drm_dsi.c
> >>>>>> driver
> >>>>>> and common bridge driver code in samsung-dsim.c providing that
> >>>>>> the new
> >>>>>> platform-specific glue should be supported in the bridge driver,
> >>>>>> unlike
> >>>>>> exynos platform drm drivers.
> >>>>>>
> >>>>>> - Add samsung_dsim_plat_data for keeping platform-specific
> >>>>>> attributes like
> >>>>>>      host_ops, irq_ops, and hw_type.
> >>>>>>
> >>>>>> - Initialize the plat_data hooks for exynos platform in
> >>>>>> exynos_drm_dsi.c.
> >>>>>>
> >>>>>> - samsung_dsim_probe is the common probe call across
> >>>>>> exynos_drm_dsi.c and
> >>>>>>      samsung-dsim.c.
> >>>>>>
> >>>>>> - plat_data hooks like host_ops and irq_ops are invoked during the
> >>>>>>      respective bridge call chains.
> >>>>>
> >>>>> Maybe the Subject should say "Split ... driver" or "Move ...
> >>>>> driver" ,
> >>>>> since it is not adding a new driver here ?
> >>>>
> >>>> Though it is not added a completely new driver, it is adding more
> >>>> infrastructure platform code to be compatible with both Exynos and
> >>>> i.MX8M. This is the prime reason for adding that commit head and
> >>>> explaining the same in the commit body.
> >>>
> >>> Diffstat looks like this:
> >>>
> >>>    drivers/gpu/drm/bridge/samsung-dsim.c   | 1703
> >>> ++++++++++++++++++++++
> >>>    drivers/gpu/drm/exynos/Kconfig          |    1 +
> >>>    drivers/gpu/drm/exynos/exynos_drm_dsi.c | 1766
> >>> ++---------------------
> >>>    include/drm/bridge/samsung-dsim.h       |  113 ++
> >>>    7 files changed, 1952 insertions(+), 1653 deletions(-)
> >>>
> >>> Looks to me like most of the code is just moved from existing driver in
> >>> this patch.
> >>
> >> Yeah, as I explained (from commit) it is moved, updated, and written
> >> the plat code. How about this head?
> >>
> >> "drm: bridge: Add Samsung DSIM bridge (Split from exynos_drm_dsi)"
> >
> > I disagree with the "Add" part of the Subject, but I'll wait for
> > others' opinion here.
>
> Maybe something like a "Generalize Exynos-DSI DRM driver into a generic
> Samsung DSIM bridge"?

I agreed.

Jagan.

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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Marcel Ziswiler]

Hi Jagan

On Wed, 2022-10-05 at 20:42 +0530, Jagan Teki wrote:
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
> 
> The final bridge supports both the Exynos and i.MX8MM DSI devices.
> 
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
> 
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge 
> 
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
> 
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
> 
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
> 
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
> 
> Patch 0001:     Samsung DSIM bridge
> 
> Patch 0002:     PHY optional
> 
> Patch 0003:     OF-graph or Child node lookup
> 
> Patch 0004:     DSI host initialization 
> 
> Patch 0005:     atomic check
> 
> Patch 0006:     PMS_P offset via plat data
> 
> Patch 0007:     atomic_get_input_bus_fmts
> 
> Patch 0008:     input_bus_flags
> 
> Patch 0009:     document fsl,imx8mm-mipi-dsim
> 
> Patch 0010:     add i.MX8MM DSIM support
> 
> Tested in Engicam i.Core MX8M Mini SoM.

Thanks for this work!

This also works great on Verdin iMX8M Mini together with the SN65DSI84-based Verdin DSI to LVDS Adapter.

Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v7
> 
> Any inputs?
> Jagan.
> 
> Jagan Teki (10):
>   drm: bridge: Add Samsung DSIM bridge driver
>   drm: bridge: samsung-dsim: Lookup OF-graph or Child node devices
>   drm: bridge: samsung-dsim: Mark PHY as optional
>   drm: bridge: samsung-dsim: Handle proper DSI host initialization
>   drm: bridge: samsung-dsim: Add atomic_check
>   drm: bridge: samsung-dsim: Add platform PLL_P (PMS_P) offset
>   drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts
>   drm: bridge: samsung-dsim: Add input_bus_flags
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8MM support
>   drm: bridge: samsung-dsim: Add i.MX8MM support
> 
>  .../bindings/display/exynos/exynos_dsim.txt   |    1 +
>  MAINTAINERS                                   |    9 +
>  drivers/gpu/drm/bridge/Kconfig                |   12 +
>  drivers/gpu/drm/bridge/Makefile               |    1 +
>  drivers/gpu/drm/bridge/samsung-dsim.c         | 1856 +++++++++++++++++
>  drivers/gpu/drm/exynos/Kconfig                |    1 +
>  drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1766 +---------------
>  include/drm/bridge/samsung-dsim.h             |  115 +
>  8 files changed, 2108 insertions(+), 1653 deletions(-)
>  create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
>  create mode 100644 include/drm/bridge/samsung-dsim.h

Cheers

Marcel
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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Robert Foss]

Hey Jagan,

On Wed, 5 Oct 2022 at 17:13, Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
>
> The final bridge supports both the Exynos and i.MX8MM DSI devices.
>
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
>
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge
>
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
>
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
>
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
>
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
>
> Patch 0001:     Samsung DSIM bridge
>
> Patch 0002:     PHY optional
>
> Patch 0003:     OF-graph or Child node lookup
>
> Patch 0004:     DSI host initialization
>
> Patch 0005:     atomic check
>
> Patch 0006:     PMS_P offset via plat data
>
> Patch 0007:     atomic_get_input_bus_fmts
>
> Patch 0008:     input_bus_flags
>
> Patch 0009:     document fsl,imx8mm-mipi-dsim
>
> Patch 0010:     add i.MX8MM DSIM support
>
> Tested in Engicam i.Core MX8M Mini SoM.
>
> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v7
>
> Any inputs?
> Jagan.
>
> Jagan Teki (10):
>   drm: bridge: Add Samsung DSIM bridge driver
>   drm: bridge: samsung-dsim: Lookup OF-graph or Child node devices
>   drm: bridge: samsung-dsim: Mark PHY as optional
>   drm: bridge: samsung-dsim: Handle proper DSI host initialization
>   drm: bridge: samsung-dsim: Add atomic_check
>   drm: bridge: samsung-dsim: Add platform PLL_P (PMS_P) offset
>   drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts
>   drm: bridge: samsung-dsim: Add input_bus_flags
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8MM support
>   drm: bridge: samsung-dsim: Add i.MX8MM support
>
>  .../bindings/display/exynos/exynos_dsim.txt   |    1 +
>  MAINTAINERS                                   |    9 +
>  drivers/gpu/drm/bridge/Kconfig                |   12 +
>  drivers/gpu/drm/bridge/Makefile               |    1 +
>  drivers/gpu/drm/bridge/samsung-dsim.c         | 1856 +++++++++++++++++
>  drivers/gpu/drm/exynos/Kconfig                |    1 +
>  drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1766 +---------------
>  include/drm/bridge/samsung-dsim.h             |  115 +
>  8 files changed, 2108 insertions(+), 1653 deletions(-)
>  create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
>  create mode 100644 include/drm/bridge/samsung-dsim.h

I'm seeing some checkpatch --strict warnings throughout this series,
do you mind having a look at them?

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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi Jagan,

Am Mittwoch, 5. Oktober 2022, 17:12:59 CEST schrieb Jagan Teki:
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
> 
> The final bridge supports both the Exynos and i.MX8MM DSI devices.
> 
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
> 
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge
> 
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
> 
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
> 
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
> 
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
> 
> Patch 0001: 	Samsung DSIM bridge
> 
> Patch 0002:	PHY optional
> 
> Patch 0003:	OF-graph or Child node lookup
> 
> Patch 0004: 	DSI host initialization
> 
> Patch 0005:	atomic check
> 
> Patch 0006:	PMS_P offset via plat data
> 
> Patch 0007:	atomic_get_input_bus_fmts
> 
> Patch 0008:	input_bus_flags
> 
> Patch 0009:	document fsl,imx8mm-mipi-dsim
> 
> Patch 0010:	add i.MX8MM DSIM support
> 
> Tested in Engicam i.Core MX8M Mini SoM.

Thanks for working on this!

This works on TQMa8MQML + MBa8Mx (imx8mm) using a SN65DSI83 DSI-LVDS-Bridge.
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Best regards,
Alexander

> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v7
> 
> Any inputs?
> Jagan.
> 
> Jagan Teki (10):
>   drm: bridge: Add Samsung DSIM bridge driver
>   drm: bridge: samsung-dsim: Lookup OF-graph or Child node devices
>   drm: bridge: samsung-dsim: Mark PHY as optional
>   drm: bridge: samsung-dsim: Handle proper DSI host initialization
>   drm: bridge: samsung-dsim: Add atomic_check
>   drm: bridge: samsung-dsim: Add platform PLL_P (PMS_P) offset
>   drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts
>   drm: bridge: samsung-dsim: Add input_bus_flags
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8MM support
>   drm: bridge: samsung-dsim: Add i.MX8MM support
> 
>  .../bindings/display/exynos/exynos_dsim.txt   |    1 +
>  MAINTAINERS                                   |    9 +
>  drivers/gpu/drm/bridge/Kconfig                |   12 +
>  drivers/gpu/drm/bridge/Makefile               |    1 +
>  drivers/gpu/drm/bridge/samsung-dsim.c         | 1856 +++++++++++++++++
>  drivers/gpu/drm/exynos/Kconfig                |    1 +
>  drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1766 +---------------
>  include/drm/bridge/samsung-dsim.h             |  115 +
>  8 files changed, 2108 insertions(+), 1653 deletions(-)
>  create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
>  create mode 100644 include/drm/bridge/samsung-dsim.h





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Re: [PATCH v7 01/10] drm: bridge: Add Samsung DSIM bridge driver

[Jagan Teki]

On Tue, Oct 18, 2022 at 8:35 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Mon, Oct 17, 2022 at 2:31 PM Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
> >
> > Hi,
> >
> > On 17.10.2022 10:48, Marek Vasut wrote:
> > > On 10/17/22 09:43, Jagan Teki wrote:
> > >> On Mon, Oct 17, 2022 at 12:49 PM Marek Vasut <marex@denx.de> wrote:
> > >>> On 10/17/22 04:49, Jagan Teki wrote:
> > >>>> On Sun, Oct 16, 2022 at 3:16 AM Marek Vasut <marex@denx.de> wrote:
> > >>>>>
> > >>>>> On 10/5/22 17:13, Jagan Teki wrote:
> > >>>>>> Samsung MIPI DSIM controller is common DSI IP that can be used in
> > >>>>>> various
> > >>>>>> SoCs like Exynos, i.MX8M Mini/Nano.
> > >>>>>>
> > >>>>>> In order to access this DSI controller between various platform
> > >>>>>> SoCs,
> > >>>>>> the ideal way to incorporate this in the drm stack is via the drm
> > >>>>>> bridge
> > >>>>>> driver.
> > >>>>>>
> > >>>>>> This patch is trying to differentiate platform-specific and
> > >>>>>> bridge driver
> > >>>>>> code by maintaining exynos platform glue code in exynos_drm_dsi.c
> > >>>>>> driver
> > >>>>>> and common bridge driver code in samsung-dsim.c providing that
> > >>>>>> the new
> > >>>>>> platform-specific glue should be supported in the bridge driver,
> > >>>>>> unlike
> > >>>>>> exynos platform drm drivers.
> > >>>>>>
> > >>>>>> - Add samsung_dsim_plat_data for keeping platform-specific
> > >>>>>> attributes like
> > >>>>>>      host_ops, irq_ops, and hw_type.
> > >>>>>>
> > >>>>>> - Initialize the plat_data hooks for exynos platform in
> > >>>>>> exynos_drm_dsi.c.
> > >>>>>>
> > >>>>>> - samsung_dsim_probe is the common probe call across
> > >>>>>> exynos_drm_dsi.c and
> > >>>>>>      samsung-dsim.c.
> > >>>>>>
> > >>>>>> - plat_data hooks like host_ops and irq_ops are invoked during the
> > >>>>>>      respective bridge call chains.
> > >>>>>
> > >>>>> Maybe the Subject should say "Split ... driver" or "Move ...
> > >>>>> driver" ,
> > >>>>> since it is not adding a new driver here ?
> > >>>>
> > >>>> Though it is not added a completely new driver, it is adding more
> > >>>> infrastructure platform code to be compatible with both Exynos and
> > >>>> i.MX8M. This is the prime reason for adding that commit head and
> > >>>> explaining the same in the commit body.
> > >>>
> > >>> Diffstat looks like this:
> > >>>
> > >>>    drivers/gpu/drm/bridge/samsung-dsim.c   | 1703
> > >>> ++++++++++++++++++++++
> > >>>    drivers/gpu/drm/exynos/Kconfig          |    1 +
> > >>>    drivers/gpu/drm/exynos/exynos_drm_dsi.c | 1766
> > >>> ++---------------------
> > >>>    include/drm/bridge/samsung-dsim.h       |  113 ++
> > >>>    7 files changed, 1952 insertions(+), 1653 deletions(-)
> > >>>
> > >>> Looks to me like most of the code is just moved from existing driver in
> > >>> this patch.
> > >>
> > >> Yeah, as I explained (from commit) it is moved, updated, and written
> > >> the plat code. How about this head?
> > >>
> > >> "drm: bridge: Add Samsung DSIM bridge (Split from exynos_drm_dsi)"
> > >
> > > I disagree with the "Add" part of the Subject, but I'll wait for
> > > others' opinion here.
> >
> > Maybe something like a "Generalize Exynos-DSI DRM driver into a generic
> > Samsung DSIM bridge"?

I'm using this commit head for next version patches, hope all Okay with it.

Thanks,
Jagan.

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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Sébastien Szymanski]

Hello Jagan,

On 10/5/22 17:12, Jagan Teki wrote:
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
> 
> The final bridge supports both the Exynos and i.MX8MM DSI devices.
> 
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
> 
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge
> 
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
> 
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
> 
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
> 
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
> 
> Patch 0001: 	Samsung DSIM bridge
> 
> Patch 0002:	PHY optional
> 
> Patch 0003:	OF-graph or Child node lookup
> 
> Patch 0004: 	DSI host initialization
> 
> Patch 0005:	atomic check
> 
> Patch 0006:	PMS_P offset via plat data
> 
> Patch 0007:	atomic_get_input_bus_fmts
> 
> Patch 0008:	input_bus_flags
> 
> Patch 0009:	document fsl,imx8mm-mipi-dsim
> 
> Patch 0010:	add i.MX8MM DSIM support
> 
> Tested in Engicam i.Core MX8M Mini SoM.
> 
> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v7
> 
> Any inputs?

I tried this series on Armadeus OPOS8MM Dev (i.MX8MM) board with the 
PowerTrip PH720128T004-ZBC02 DSI panel  (720x1280, 2 lanes).

It works after I fixed the logic of some video mode flags:

in function samsung_dsim_init_link(struct samsung_dsim *dsi):

-if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP))
+if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
	reg |= DSIM_HFP_MODE;

The bit has to be set to disable HFP.
Same logic for HPB, HSA and EOT packets.

Regards,

> Jagan.
> 
> Jagan Teki (10):
>    drm: bridge: Add Samsung DSIM bridge driver
>    drm: bridge: samsung-dsim: Lookup OF-graph or Child node devices
>    drm: bridge: samsung-dsim: Mark PHY as optional
>    drm: bridge: samsung-dsim: Handle proper DSI host initialization
>    drm: bridge: samsung-dsim: Add atomic_check
>    drm: bridge: samsung-dsim: Add platform PLL_P (PMS_P) offset
>    drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts
>    drm: bridge: samsung-dsim: Add input_bus_flags
>    dt-bindings: display: exynos: dsim: Add NXP i.MX8MM support
>    drm: bridge: samsung-dsim: Add i.MX8MM support
> 
>   .../bindings/display/exynos/exynos_dsim.txt   |    1 +
>   MAINTAINERS                                   |    9 +
>   drivers/gpu/drm/bridge/Kconfig                |   12 +
>   drivers/gpu/drm/bridge/Makefile               |    1 +
>   drivers/gpu/drm/bridge/samsung-dsim.c         | 1856 +++++++++++++++++
>   drivers/gpu/drm/exynos/Kconfig                |    1 +
>   drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1766 +---------------
>   include/drm/bridge/samsung-dsim.h             |  115 +
>   8 files changed, 2108 insertions(+), 1653 deletions(-)
>   create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
>   create mode 100644 include/drm/bridge/samsung-dsim.h
> 

-- 
Sébastien Szymanski, Armadeus Systems
Software engineer


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Re: [PATCH v7 07/10] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts

[Jagan Teki]

On Mon, Oct 17, 2022 at 12:54 PM Marek Vasut <marex@denx.de> wrote:
>
> On 10/17/22 05:58, Jagan Teki wrote:
> > On Sun, Oct 16, 2022 at 3:31 AM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 10/5/22 17:13, Jagan Teki wrote:
> >>
> >> [...]
> >>
> >>> @@ -1321,6 +1322,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
> >>>        pm_runtime_put_sync(dsi->dev);
> >>>    }
> >>>
> >>> +#define MAX_INPUT_SEL_FORMATS        1
> >>> +
> >>> +static u32 *
> >>> +samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> >>> +                                    struct drm_bridge_state *bridge_state,
> >>> +                                    struct drm_crtc_state *crtc_state,
> >>> +                                    struct drm_connector_state *conn_state,
> >>> +                                    u32 output_fmt,
> >>> +                                    unsigned int *num_input_fmts)
> >>> +{
> >>> +     u32 *input_fmts;
> >>> +
> >>> +     *num_input_fmts = 0;
> >>> +
> >>> +     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
> >>> +                          GFP_KERNEL);
> >>> +     if (!input_fmts)
> >>> +             return NULL;
> >>> +
> >>> +     /* This is the DSI-end bus format */
> >>> +     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
> >>> +     *num_input_fmts = 1;
> >>
> >> Is this the only supported format ? NXP AN13573 lists the following:
> >
> > At least it only formats I have tested on my panel.
> >
> >>
> >> i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
> >> 3.7.4 Pixel formats
> >> Table 14. DSI pixel packing formats
> >>
> >> Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2
> >> Packed Pixel Stream, 24-bit YCbCr, 4:2:2
> >> Packed Pixel Stream, 16-bit YCbCr, 4:2:2
> >> Packed Pixel Stream, 30-bit RGB, 10-10-10
> >> Packed Pixel Stream, 36-bit RGB, 12-12-12
> >> Packed Pixel Stream, 12-bit YCbCr, 4:2:0
> >> Packed Pixel Stream, 16-bit RGB, 5-6-5
> >> Packed Pixel Stream, 18-bit RGB, 6-6-6
> >> Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6
> >> Packed Pixel Stream, 24-bit RGB, 8-8-8 Format
> >>
> >> The MX8MM/MN LCDIF can generate all of those RGB formats , the MX8MP
> >> LCDIFv3 can also generate the 16bit YCbCr .
> >>
> >> It seems there should be more formats here.
> >
> > The idea of this patch is to support the default format first, and can
> > possibly add future patches with the addition of new formats.
>
> Since you already know about the list, please add all the formats, so we
> won't be adding known broken code first, only to fix it later.

Okay. I can see the DSI section Mini TRM shown below formats. (13.6.2 Features)

Supports pixel format: 16bpp, 18bpp packed, 18bpp loosely packed (3 byte
format), and 24bpp

I will try to add these 4 formats. let me know.

Jagan.

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Re: [PATCH v7 07/10] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts

[Jagan Teki]

On Sun, Oct 16, 2022 at 3:31 AM Marek Vasut <marex@denx.de> wrote:
>
> On 10/5/22 17:13, Jagan Teki wrote:
>
> [...]
>
> > @@ -1321,6 +1322,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
> >       pm_runtime_put_sync(dsi->dev);
> >   }
> >
> > +#define MAX_INPUT_SEL_FORMATS        1
> > +
> > +static u32 *
> > +samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> > +                                    struct drm_bridge_state *bridge_state,
> > +                                    struct drm_crtc_state *crtc_state,
> > +                                    struct drm_connector_state *conn_state,
> > +                                    u32 output_fmt,
> > +                                    unsigned int *num_input_fmts)
> > +{
> > +     u32 *input_fmts;
> > +
> > +     *num_input_fmts = 0;
> > +
> > +     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
> > +                          GFP_KERNEL);
> > +     if (!input_fmts)
> > +             return NULL;
> > +
> > +     /* This is the DSI-end bus format */
> > +     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
> > +     *num_input_fmts = 1;
>
> Is this the only supported format ? NXP AN13573 lists the following:
>
> i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
> 3.7.4 Pixel formats
> Table 14. DSI pixel packing formats
>
> Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2
> Packed Pixel Stream, 24-bit YCbCr, 4:2:2
> Packed Pixel Stream, 16-bit YCbCr, 4:2:2

Look like these are unsupported in media-bus-format.h list.

> Packed Pixel Stream, 30-bit RGB, 10-10-10
> Packed Pixel Stream, 36-bit RGB, 12-12-12
> Packed Pixel Stream, 12-bit YCbCr, 4:2:0

Same issue, unsupported.

> Packed Pixel Stream, 16-bit RGB, 5-6-5

MEDIA_BUS_FMT_RGB565_1X16

> Packed Pixel Stream, 18-bit RGB, 6-6-6

Same issue, unsupported.

> Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6
> Packed Pixel Stream, 24-bit RGB, 8-8-8 Format

MEDIA_BUS_FMT_RGB666_1X18
MEDIA_BUS_FMT_RGB888_1X24

>
> The MX8MM/MN LCDIF can generate all of those RGB formats , the MX8MP
> LCDIFv3 can also generate the 16bit YCbCr .

Is YCbCr denoted as UYVY in media-bus-format.h ?

Thanks,
Jagan.

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Re: [PATCH v7 07/10] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts

[Marek Vasut]

On 11/3/22 10:39, Jagan Teki wrote:
> On Sun, Oct 16, 2022 at 3:31 AM Marek Vasut <marex@denx.de> wrote:
>>
>> On 10/5/22 17:13, Jagan Teki wrote:
>>
>> [...]
>>
>>> @@ -1321,6 +1322,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
>>>        pm_runtime_put_sync(dsi->dev);
>>>    }
>>>
>>> +#define MAX_INPUT_SEL_FORMATS        1
>>> +
>>> +static u32 *
>>> +samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>>> +                                    struct drm_bridge_state *bridge_state,
>>> +                                    struct drm_crtc_state *crtc_state,
>>> +                                    struct drm_connector_state *conn_state,
>>> +                                    u32 output_fmt,
>>> +                                    unsigned int *num_input_fmts)
>>> +{
>>> +     u32 *input_fmts;
>>> +
>>> +     *num_input_fmts = 0;
>>> +
>>> +     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
>>> +                          GFP_KERNEL);
>>> +     if (!input_fmts)
>>> +             return NULL;
>>> +
>>> +     /* This is the DSI-end bus format */
>>> +     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
>>> +     *num_input_fmts = 1;
>>
>> Is this the only supported format ? NXP AN13573 lists the following:
>>
>> i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
>> 3.7.4 Pixel formats
>> Table 14. DSI pixel packing formats
>>
>> Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2
>> Packed Pixel Stream, 24-bit YCbCr, 4:2:2
>> Packed Pixel Stream, 16-bit YCbCr, 4:2:2
> 
> Look like these are unsupported in media-bus-format.h list.

Aren't those:

MEDIA_BUS_FMT_UYVY12_1X24
MEDIA_BUS_FMT_UYVY8_1X16

?

Those are packed, and subsampled 4:2:2

>> Packed Pixel Stream, 30-bit RGB, 10-10-10

MEDIA_BUS_FMT_RGB101010_1X30

>> Packed Pixel Stream, 36-bit RGB, 12-12-12

MEDIA_BUS_FMT_RGB121212_1X36

>> Packed Pixel Stream, 12-bit YCbCr, 4:2:0
> 
> Same issue, unsupported.

The 12-bit packed 4:2:0 might be something along the lines of

drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
MEDIA_BUS_FMT_YUYV8_1_5X8, /* YUV420 */

>> Packed Pixel Stream, 16-bit RGB, 5-6-5
> 
> MEDIA_BUS_FMT_RGB565_1X16
> 
>> Packed Pixel Stream, 18-bit RGB, 6-6-6
> 
> Same issue, unsupported.

MEDIA_BUS_FMT_RGB666_1X18

>> Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6
>> Packed Pixel Stream, 24-bit RGB, 8-8-8 Format
> 
> MEDIA_BUS_FMT_RGB666_1X18
> MEDIA_BUS_FMT_RGB888_1X24
> 
>>
>> The MX8MM/MN LCDIF can generate all of those RGB formats , the MX8MP
>> LCDIFv3 can also generate the 16bit YCbCr .
> 
> Is YCbCr denoted as UYVY in media-bus-format.h ?
I think this applies:

https://www.kernel.org/doc/html/latest/userspace-api/media/v4l/colorspaces.html
"
Sometimes people confuse Y’CbCr as being a colorspace. This is not 
correct, it is just an encoding of an R’G’B’ color into luma and chroma 
values.
"

And esp. this:

"
In order to correctly interpret a color you need to know the 
quantization range, whether it is R’G’B’ or Y’CbCr, the used Y’CbCr 
encoding and the colorspace. From that information you can calculate the 
corresponding CIE XYZ color and map that again to whatever colorspace 
your display device uses.
"

Which means that in order to properly describe or interpret the data, 
you need the entire v4l2_mbus_framefmt content, not just the pixel code:

https://www.kernel.org/doc/html/latest/userspace-api/media/v4l/subdev-formats.html

But this information is not passed across the bus, that's metadata 
internal to the kernel.

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Re: [PATCH v7 07/10] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts

[Marek Vasut]

On 11/3/22 08:40, Jagan Teki wrote:
> On Mon, Oct 17, 2022 at 12:54 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 10/17/22 05:58, Jagan Teki wrote:
>>> On Sun, Oct 16, 2022 at 3:31 AM Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 10/5/22 17:13, Jagan Teki wrote:
>>>>
>>>> [...]
>>>>
>>>>> @@ -1321,6 +1322,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
>>>>>         pm_runtime_put_sync(dsi->dev);
>>>>>     }
>>>>>
>>>>> +#define MAX_INPUT_SEL_FORMATS        1
>>>>> +
>>>>> +static u32 *
>>>>> +samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>>>>> +                                    struct drm_bridge_state *bridge_state,
>>>>> +                                    struct drm_crtc_state *crtc_state,
>>>>> +                                    struct drm_connector_state *conn_state,
>>>>> +                                    u32 output_fmt,
>>>>> +                                    unsigned int *num_input_fmts)
>>>>> +{
>>>>> +     u32 *input_fmts;
>>>>> +
>>>>> +     *num_input_fmts = 0;
>>>>> +
>>>>> +     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
>>>>> +                          GFP_KERNEL);
>>>>> +     if (!input_fmts)
>>>>> +             return NULL;
>>>>> +
>>>>> +     /* This is the DSI-end bus format */
>>>>> +     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
>>>>> +     *num_input_fmts = 1;
>>>>
>>>> Is this the only supported format ? NXP AN13573 lists the following:
>>>
>>> At least it only formats I have tested on my panel.
>>>
>>>>
>>>> i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
>>>> 3.7.4 Pixel formats
>>>> Table 14. DSI pixel packing formats
>>>>
>>>> Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2
>>>> Packed Pixel Stream, 24-bit YCbCr, 4:2:2
>>>> Packed Pixel Stream, 16-bit YCbCr, 4:2:2
>>>> Packed Pixel Stream, 30-bit RGB, 10-10-10
>>>> Packed Pixel Stream, 36-bit RGB, 12-12-12
>>>> Packed Pixel Stream, 12-bit YCbCr, 4:2:0
>>>> Packed Pixel Stream, 16-bit RGB, 5-6-5
>>>> Packed Pixel Stream, 18-bit RGB, 6-6-6
>>>> Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6
>>>> Packed Pixel Stream, 24-bit RGB, 8-8-8 Format
>>>>
>>>> The MX8MM/MN LCDIF can generate all of those RGB formats , the MX8MP
>>>> LCDIFv3 can also generate the 16bit YCbCr .
>>>>
>>>> It seems there should be more formats here.
>>>
>>> The idea of this patch is to support the default format first, and can
>>> possibly add future patches with the addition of new formats.
>>
>> Since you already know about the list, please add all the formats, so we
>> won't be adding known broken code first, only to fix it later.
> 
> Okay. I can see the DSI section Mini TRM shown below formats. (13.6.2 Features)
> 
> Supports pixel format: 16bpp, 18bpp packed, 18bpp loosely packed (3 byte
> format), and 24bpp
> 
> I will try to add these 4 formats. let me know.

You should be able to add all but the 'Packed Pixel Stream, 12-bit 
YCbCr, 4:2:0' which would have to be defined (that's a few lines patch?).

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Re: [PATCH v7 07/10] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts

[Jagan Teki]

On Thu, Nov 3, 2022 at 9:56 PM Marek Vasut <marex@denx.de> wrote:
>
> On 11/3/22 10:39, Jagan Teki wrote:
> > On Sun, Oct 16, 2022 at 3:31 AM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 10/5/22 17:13, Jagan Teki wrote:
> >>
> >> [...]
> >>
> >>> @@ -1321,6 +1322,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
> >>>        pm_runtime_put_sync(dsi->dev);
> >>>    }
> >>>
> >>> +#define MAX_INPUT_SEL_FORMATS        1
> >>> +
> >>> +static u32 *
> >>> +samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> >>> +                                    struct drm_bridge_state *bridge_state,
> >>> +                                    struct drm_crtc_state *crtc_state,
> >>> +                                    struct drm_connector_state *conn_state,
> >>> +                                    u32 output_fmt,
> >>> +                                    unsigned int *num_input_fmts)
> >>> +{
> >>> +     u32 *input_fmts;
> >>> +
> >>> +     *num_input_fmts = 0;
> >>> +
> >>> +     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
> >>> +                          GFP_KERNEL);
> >>> +     if (!input_fmts)
> >>> +             return NULL;
> >>> +
> >>> +     /* This is the DSI-end bus format */
> >>> +     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
> >>> +     *num_input_fmts = 1;
> >>
> >> Is this the only supported format ? NXP AN13573 lists the following:
> >>
> >> i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
> >> 3.7.4 Pixel formats
> >> Table 14. DSI pixel packing formats
> >>
> >> Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2
> >> Packed Pixel Stream, 24-bit YCbCr, 4:2:2
> >> Packed Pixel Stream, 16-bit YCbCr, 4:2:2
> >
> > Look like these are unsupported in media-bus-format.h list.
>
> Aren't those:
>
> MEDIA_BUS_FMT_UYVY12_1X24

Why is UYVY12 - YCbCr, 4:2:2 is 4+2+2 = 8 then it has UYVY8 ?

> MEDIA_BUS_FMT_UYVY8_1X16

If YCbCr is UYVY (I still don't get this notation, sorry) then Packed
Pixel Stream, 24-bit YCbCr, 4:2:2 with 2 Pixels per packet from Table
14 can be

MEDIA_BUS_FMT_UYVY8_2X24
(YCbCr 4:2:2 is UYVY8)

 " based on a reference example from media bus format doc
4.13.3.4.1.1.3. Packed YUV Formats, For instance, a format where
pixels are encoded as 8-bit YUV values downsampled to 4:2:2 and
transferred as 2 8-bit bus samples per pixel in the U, Y, V, Y order
will be named MEDIA_BUS_FMT_UYVY8_2X8."

https://www.kernel.org/doc/html/latest/userspace-api/media/v4l/subdev-formats.html

_2X24 here 2 Pixels per packet is the exact packets to consider or we
can consider 1 Pixel per packet also. If later is true then _1X24 from
your notation is correct.

Thanks,
Jagan.

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Re: [PATCH v7 07/10] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts

[Marek Vasut]

On 11/3/22 18:27, Jagan Teki wrote:
> On Thu, Nov 3, 2022 at 9:56 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 11/3/22 10:39, Jagan Teki wrote:
>>> On Sun, Oct 16, 2022 at 3:31 AM Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 10/5/22 17:13, Jagan Teki wrote:
>>>>
>>>> [...]
>>>>
>>>>> @@ -1321,6 +1322,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
>>>>>         pm_runtime_put_sync(dsi->dev);
>>>>>     }
>>>>>
>>>>> +#define MAX_INPUT_SEL_FORMATS        1
>>>>> +
>>>>> +static u32 *
>>>>> +samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>>>>> +                                    struct drm_bridge_state *bridge_state,
>>>>> +                                    struct drm_crtc_state *crtc_state,
>>>>> +                                    struct drm_connector_state *conn_state,
>>>>> +                                    u32 output_fmt,
>>>>> +                                    unsigned int *num_input_fmts)
>>>>> +{
>>>>> +     u32 *input_fmts;
>>>>> +
>>>>> +     *num_input_fmts = 0;
>>>>> +
>>>>> +     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
>>>>> +                          GFP_KERNEL);
>>>>> +     if (!input_fmts)
>>>>> +             return NULL;
>>>>> +
>>>>> +     /* This is the DSI-end bus format */
>>>>> +     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
>>>>> +     *num_input_fmts = 1;
>>>>
>>>> Is this the only supported format ? NXP AN13573 lists the following:
>>>>
>>>> i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
>>>> 3.7.4 Pixel formats
>>>> Table 14. DSI pixel packing formats
>>>>
>>>> Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2
>>>> Packed Pixel Stream, 24-bit YCbCr, 4:2:2
>>>> Packed Pixel Stream, 16-bit YCbCr, 4:2:2
>>>
>>> Look like these are unsupported in media-bus-format.h list.
>>
>> Aren't those:
>>
>> MEDIA_BUS_FMT_UYVY12_1X24
> 
> Why is UYVY12 - YCbCr, 4:2:2 is 4+2+2 = 8 then it has UYVY8 ?

(someone please correct me if I'm totally wrong here)

The 12 is channel width (12 bit for each Y1/Y2/U/V channel sample).
The 4:2:2 is subsampling (where are the color components sampled 
relative to brightness component).

Picture is here:
https://upload.wikimedia.org/wikipedia/commons/f/f2/Common_chroma_subsampling_ratios.svg

Each Y square of the left is 12bit sample.
Each U+V square is 12bit sample for U and 12bit sample for V.

In case of 4:4:4 subsampling, each luminance (brightness) component has 
matching chrominance (color) components.

In case of the 4:2:2 subsampling, two neighboring luminance components 
share two chrominance components. To transfer one pixel including color 
information, you have to transfer two pixels, Y0+U as 2x12bit sample in 
one cycle of 24bit bus, and then Y1+V as 2x12bit sample in another cycle 
of 24bit bus (2 clock cycles total, 4 samples total). From that you can 
reconstruct the two top-left squares (purple pixels) in the rightmost 
YUV column of 4:2:2 row.

The entire trick is that because eye is less sensitive to color than it 
is to light, you can transfer less color information and thus save 
bandwidth without anyone noticing (much of it).

>> MEDIA_BUS_FMT_UYVY8_1X16
> 
> If YCbCr is UYVY (I still don't get this notation, sorry) then Packed
> Pixel Stream, 24-bit YCbCr, 4:2:2 with 2 Pixels per packet from Table
> 14 can be
> 
> MEDIA_BUS_FMT_UYVY8_2X24
> (YCbCr 4:2:2 is UYVY8)
> 
>   " based on a reference example from media bus format doc
> 4.13.3.4.1.1.3. Packed YUV Formats, For instance, a format where
> pixels are encoded as 8-bit YUV values downsampled to 4:2:2 and
> transferred as 2 8-bit bus samples per pixel in the U, Y, V, Y order
> will be named MEDIA_BUS_FMT_UYVY8_2X8."

The way I read the above is that the channel width of each channel is 
8-bit , so you start with two pixels Y0/U/Y1/V which add up to 32bit 
total. That is transferred over 8-bit bus, in 4 bus cycles total. One 
pixel therefore takes 2 cycles of the 8 bit bus to transfer, even if you 
cannot transfer one pixel separately .

> https://www.kernel.org/doc/html/latest/userspace-api/media/v4l/subdev-formats.html
> 
> _2X24 here 2 Pixels per packet is the exact packets to consider or we
> can consider 1 Pixel per packet also. If later is true then _1X24 from
> your notation is correct.

Since the DSIM input bus is 32bit wide, to transfer one such 4:2:2 
pixel, you need 1 bus cycle (2x12 bits per half of two pixels).

[...]

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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Frieder Schrempf]

On 05.10.22 17:12, Jagan Teki wrote:
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
> 
> The final bridge supports both the Exynos and i.MX8MM DSI devices.
> 
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
> 
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge 
> 
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
> 
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
> 
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
> 
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
> 
> Patch 0001: 	Samsung DSIM bridge
> 
> Patch 0002:	PHY optional
> 
> Patch 0003:	OF-graph or Child node lookup
> 
> Patch 0004: 	DSI host initialization 
> 
> Patch 0005:	atomic check
> 
> Patch 0006:	PMS_P offset via plat data
> 
> Patch 0007:	atomic_get_input_bus_fmts
> 
> Patch 0008:	input_bus_flags
> 
> Patch 0009:	document fsl,imx8mm-mipi-dsim
> 
> Patch 0010:	add i.MX8MM DSIM support
> 
> Tested in Engicam i.Core MX8M Mini SoM.
> 
> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v7
> 
> Any inputs?
> Jagan.

I tested this on the Kontron DL i.MX8MM which uses a TI SN65DSI84 bridge
and a Jenson 7" LVDS Display.

Thanks for your work, Jagan!

Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron DL
i.MX8MM

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Re: [PATCH v7 07/10] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts

[Jagan Teki]

Hi Marek,

On Fri, Nov 4, 2022 at 12:28 AM Marek Vasut <marex@denx.de> wrote:
>
> On 11/3/22 18:27, Jagan Teki wrote:
> > On Thu, Nov 3, 2022 at 9:56 PM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 11/3/22 10:39, Jagan Teki wrote:
> >>> On Sun, Oct 16, 2022 at 3:31 AM Marek Vasut <marex@denx.de> wrote:
> >>>>
> >>>> On 10/5/22 17:13, Jagan Teki wrote:
> >>>>
> >>>> [...]
> >>>>
> >>>>> @@ -1321,6 +1322,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
> >>>>>         pm_runtime_put_sync(dsi->dev);
> >>>>>     }
> >>>>>
> >>>>> +#define MAX_INPUT_SEL_FORMATS        1
> >>>>> +
> >>>>> +static u32 *
> >>>>> +samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> >>>>> +                                    struct drm_bridge_state *bridge_state,
> >>>>> +                                    struct drm_crtc_state *crtc_state,
> >>>>> +                                    struct drm_connector_state *conn_state,
> >>>>> +                                    u32 output_fmt,
> >>>>> +                                    unsigned int *num_input_fmts)
> >>>>> +{
> >>>>> +     u32 *input_fmts;
> >>>>> +
> >>>>> +     *num_input_fmts = 0;
> >>>>> +
> >>>>> +     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
> >>>>> +                          GFP_KERNEL);
> >>>>> +     if (!input_fmts)
> >>>>> +             return NULL;
> >>>>> +
> >>>>> +     /* This is the DSI-end bus format */
> >>>>> +     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
> >>>>> +     *num_input_fmts = 1;
> >>>>
> >>>> Is this the only supported format ? NXP AN13573 lists the following:
> >>>>
> >>>> i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
> >>>> 3.7.4 Pixel formats
> >>>> Table 14. DSI pixel packing formats
> >>>>
> >>>> Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2
> >>>> Packed Pixel Stream, 24-bit YCbCr, 4:2:2
> >>>> Packed Pixel Stream, 16-bit YCbCr, 4:2:2
> >>>
> >>> Look like these are unsupported in media-bus-format.h list.
> >>
> >> Aren't those:
> >>
> >> MEDIA_BUS_FMT_UYVY12_1X24
> >
> > Why is UYVY12 - YCbCr, 4:2:2 is 4+2+2 = 8 then it has UYVY8 ?
>
> (someone please correct me if I'm totally wrong here)
>
> The 12 is channel width (12 bit for each Y1/Y2/U/V channel sample).
> The 4:2:2 is subsampling (where are the color components sampled
> relative to brightness component).
>
> Picture is here:
> https://upload.wikimedia.org/wikipedia/commons/f/f2/Common_chroma_subsampling_ratios.svg
>
> Each Y square of the left is 12bit sample.
> Each U+V square is 12bit sample for U and 12bit sample for V.
>
> In case of 4:4:4 subsampling, each luminance (brightness) component has
> matching chrominance (color) components.
>
> In case of the 4:2:2 subsampling, two neighboring luminance components
> share two chrominance components. To transfer one pixel including color
> information, you have to transfer two pixels, Y0+U as 2x12bit sample in
> one cycle of 24bit bus, and then Y1+V as 2x12bit sample in another cycle
> of 24bit bus (2 clock cycles total, 4 samples total). From that you can
> reconstruct the two top-left squares (purple pixels) in the rightmost
> YUV column of 4:2:2 row.
>
> The entire trick is that because eye is less sensitive to color than it
> is to light, you can transfer less color information and thus save
> bandwidth without anyone noticing (much of it).
>
> >> MEDIA_BUS_FMT_UYVY8_1X16
> >
> > If YCbCr is UYVY (I still don't get this notation, sorry) then Packed
> > Pixel Stream, 24-bit YCbCr, 4:2:2 with 2 Pixels per packet from Table
> > 14 can be
> >
> > MEDIA_BUS_FMT_UYVY8_2X24
> > (YCbCr 4:2:2 is UYVY8)
> >
> >   " based on a reference example from media bus format doc
> > 4.13.3.4.1.1.3. Packed YUV Formats, For instance, a format where
> > pixels are encoded as 8-bit YUV values downsampled to 4:2:2 and
> > transferred as 2 8-bit bus samples per pixel in the U, Y, V, Y order
> > will be named MEDIA_BUS_FMT_UYVY8_2X8."
>
> The way I read the above is that the channel width of each channel is
> 8-bit , so you start with two pixels Y0/U/Y1/V which add up to 32bit
> total. That is transferred over 8-bit bus, in 4 bus cycles total. One
> pixel therefore takes 2 cycles of the 8 bit bus to transfer, even if you
> cannot transfer one pixel separately .
>
> > https://www.kernel.org/doc/html/latest/userspace-api/media/v4l/subdev-formats.html
> >
> > _2X24 here 2 Pixels per packet is the exact packets to consider or we
> > can consider 1 Pixel per packet also. If later is true then _1X24 from
> > your notation is correct.
>
> Since the DSIM input bus is 32bit wide, to transfer one such 4:2:2
> pixel, you need 1 bus cycle (2x12 bits per half of two pixels).

Thanks for your explanation. I need some time to understand and it
looks worth waiting for others to comment on this.

Meanwhile, I'm planning to send subsequent version patches with
possible supported formats like,

MEDIA_BUS_FMT_UYVY8_1X16,
MEDIA_BUS_FMT_RGB101010_1X30,
MEDIA_BUS_FMT_RGB121212_1X36,
MEDIA_BUS_FMT_RGB565_1X16,
MEDIA_BUS_FMT_RGB666_1X18,
MEDIA_BUS_FMT_RGB888_1X24,

Let me know.

Jagan.

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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Fabio Estevam]

Hi,

On Mon, Nov 7, 2022 at 1:34 PM Frieder Schrempf
<frieder.schrempf@kontron.de> wrote:

> I tested this on the Kontron DL i.MX8MM which uses a TI SN65DSI84 bridge
> and a Jenson 7" LVDS Display.
>
> Thanks for your work, Jagan!
>
> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron DL
> i.MX8MM

As this series has been successfully tested on multiple devices, is it possible
to apply it so people can make further adjustments?

Thanks

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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Jagan Teki]

On Thu, Nov 10, 2022 at 9:24 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi,
>
> On Mon, Nov 7, 2022 at 1:34 PM Frieder Schrempf
> <frieder.schrempf@kontron.de> wrote:
>
> > I tested this on the Kontron DL i.MX8MM which uses a TI SN65DSI84 bridge
> > and a Jenson 7" LVDS Display.
> >
> > Thanks for your work, Jagan!
> >
> > Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron DL
> > i.MX8MM
>
> As this series has been successfully tested on multiple devices, is it possible
> to apply it so people can make further adjustments?

I think the next version patchset on this would be clean and properly
address a few comments from Marek Vasut. However, I'm still waiting
for Marek's response to my comment on the input bus formats - if it is
Okay I will send the v8.
https://lore.kernel.org/all/CAMty3ZAM+fetmBQWaSbfjME7-Up4h+Ln3BRHaPgg5tuSsObPdw@mail.gmail.com/

Thanks,
Jagan.

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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 11/10/22 17:03, Jagan Teki wrote:
> On Thu, Nov 10, 2022 at 9:24 PM Fabio Estevam <festevam@gmail.com> wrote:
>>
>> Hi,
>>
>> On Mon, Nov 7, 2022 at 1:34 PM Frieder Schrempf
>> <frieder.schrempf@kontron.de> wrote:
>>
>>> I tested this on the Kontron DL i.MX8MM which uses a TI SN65DSI84 bridge
>>> and a Jenson 7" LVDS Display.
>>>
>>> Thanks for your work, Jagan!
>>>
>>> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron DL
>>> i.MX8MM
>>
>> As this series has been successfully tested on multiple devices, is it possible
>> to apply it so people can make further adjustments?
> 
> I think the next version patchset on this would be clean and properly
> address a few comments from Marek Vasut. However, I'm still waiting
> for Marek's response to my comment on the input bus formats - if it is
> Okay I will send the v8.
> https://lore.kernel.org/all/CAMty3ZAM+fetmBQWaSbfjME7-Up4h+Ln3BRHaPgg5tuSsObPdw@mail.gmail.com/

Just send a V8 and let's see how that looks, no need to wait for me.

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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Jagan Teki]

On Thu, Nov 10, 2022 at 10:29 PM Marek Vasut <marex@denx.de> wrote:
>
> On 11/10/22 17:03, Jagan Teki wrote:
> > On Thu, Nov 10, 2022 at 9:24 PM Fabio Estevam <festevam@gmail.com> wrote:
> >>
> >> Hi,
> >>
> >> On Mon, Nov 7, 2022 at 1:34 PM Frieder Schrempf
> >> <frieder.schrempf@kontron.de> wrote:
> >>
> >>> I tested this on the Kontron DL i.MX8MM which uses a TI SN65DSI84 bridge
> >>> and a Jenson 7" LVDS Display.
> >>>
> >>> Thanks for your work, Jagan!
> >>>
> >>> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron DL
> >>> i.MX8MM
> >>
> >> As this series has been successfully tested on multiple devices, is it possible
> >> to apply it so people can make further adjustments?
> >
> > I think the next version patchset on this would be clean and properly
> > address a few comments from Marek Vasut. However, I'm still waiting
> > for Marek's response to my comment on the input bus formats - if it is
> > Okay I will send the v8.
> > https://lore.kernel.org/all/CAMty3ZAM+fetmBQWaSbfjME7-Up4h+Ln3BRHaPgg5tuSsObPdw@mail.gmail.com/
>
> Just send a V8 and let's see how that looks, no need to wait for me.

Planning to include your 8M Plus patch as part of the v8, hope it's fine?

Jagan.

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Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 11/10/22 18:37, Jagan Teki wrote:
> On Thu, Nov 10, 2022 at 10:29 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 11/10/22 17:03, Jagan Teki wrote:
>>> On Thu, Nov 10, 2022 at 9:24 PM Fabio Estevam <festevam@gmail.com> wrote:
>>>>
>>>> Hi,
>>>>
>>>> On Mon, Nov 7, 2022 at 1:34 PM Frieder Schrempf
>>>> <frieder.schrempf@kontron.de> wrote:
>>>>
>>>>> I tested this on the Kontron DL i.MX8MM which uses a TI SN65DSI84 bridge
>>>>> and a Jenson 7" LVDS Display.
>>>>>
>>>>> Thanks for your work, Jagan!
>>>>>
>>>>> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron DL
>>>>> i.MX8MM
>>>>
>>>> As this series has been successfully tested on multiple devices, is it possible
>>>> to apply it so people can make further adjustments?
>>>
>>> I think the next version patchset on this would be clean and properly
>>> address a few comments from Marek Vasut. However, I'm still waiting
>>> for Marek's response to my comment on the input bus formats - if it is
>>> Okay I will send the v8.
>>> https://lore.kernel.org/all/CAMty3ZAM+fetmBQWaSbfjME7-Up4h+Ln3BRHaPgg5tuSsObPdw@mail.gmail.com/
>>
>> Just send a V8 and let's see how that looks, no need to wait for me.
> 
> Planning to include your 8M Plus patch as part of the v8, hope it's fine?

Fine

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