Re: [PATCH v3 02/13] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema

From: Serge Semin <fancer.lancer@gmail.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Rob Herring <robh@kernel.org>,
	Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	Dinh Nguyen <dinguyen@kernel.org>,
	Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>,
	James Morse <james.morse@arm.com>,
	Michal Simek <michal.simek@xilinx.com>,
	Tony Luck <tony.luck@intel.com>,
	Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>,
	linux-edac@vger.kernel.org, Borislav Petkov <bp@alien8.de>,
	Robert Richter <rric@kernel.org>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	linux-arm-kernel@lists.infradead.org,
	Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
	linux-kernel@vger.kernel.org,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Manish Narani <manish.narani@xilinx.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v3 02/13] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema
Date: Thu, 6 Oct 2022 15:26:46 +0300	[thread overview]
Message-ID: <20221006122646.u3vi4xwgo3yswyxj@mobilestation> (raw)
In-Reply-To: <3ee1bff2-ab11-2dcd-aede-628d2735d6de@linaro.org>

On Wed, Oct 05, 2022 at 04:59:52PM +0200, Krzysztof Kozlowski wrote:
> On 03/10/2022 15:24, Rob Herring wrote:
> > On Fri, 30 Sep 2022 02:41:10 +0300, Serge Semin wrote:
> >> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a
> >> with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There
> >> are individual IRQs for each ECC and DFI events. The dedicated scrubber
> >> clock source is absent since it's fully synchronous to the core clock.
> >> In addition to that the DFI-DDR PHY CSRs can be accessed via a separate
> >> registers space.
> >>
> >> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> >> Reviewed-by: Rob Herring <robh@kernel.org>
> >>
> >> ---
> >>
> >> Changelog v2:
> >> - Keep the alphabetically ordered compatible strings list. (@Krzysztof)
> >> - Fix grammar nitpicks in the patch log. (@Krzysztof)
> >> - Drop the PHY CSR region. (@Rob)
> >> - Move the device bindings to the separate DT-schema.
> >> ---
> >>  .../memory-controllers/baikal,bt1-ddrc.yaml   | 91 +++++++++++++++++++
> >>  1 file changed, 91 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml
> >>
> > 
> > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> > 
> > yamllint warnings/errors:
> > 
> > dtschema/dtc warnings/errors:
> > ./Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-common.yaml
> 

> This is result of patch #1 failing to apply:
> 
> https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20220929234121.13955-2-Sergey.Semin@baikalelectronics.ru/

I couldn't parse the patch-applied log 

< error: sha1 information is lacking or useless (Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml).
< error: could not build fake ancestor
< hint: Use 'git am --show-current-patch=diff' to see the failed patch

What does it mean?

-Sergey

> 
> The bindings look ok, but anyway it is a merge window now.
> 
> 
> Best regards,
> Krzysztof
> 

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