[PATCH v10, 0/4] mailbox: mtk-cmdq: add MT8186 support

[PATCH v10, 0/4] mailbox: mtk-cmdq: add MT8186 support

[Yongqiang Niu]

base linux-next/master

change since v9:
1. improve register GCE_GCTL_VALUE write method reviewd in v9

Yongqiang Niu (4):
  mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition instead of number
  mailbox: mtk-cmdq: add gce software ddr enable private data
  mailbox: mtk-cmdq: add gce ddr enable support flow
  mailbox: mtk-cmdq: add MT8186 support

 drivers/mailbox/mtk-cmdq-mailbox.c | 45 +++++++++++++++++++++++++++++-
 1 file changed, 44 insertions(+), 1 deletion(-)

-- 
2.25.1


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[PATCH v10, 1/4] mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition instead of number

[Yongqiang Niu]

Use GCE_CTRL_BY_SW definition instead of number

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 9465f9081515..c3cb24f51699 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -38,6 +38,7 @@
 #define CMDQ_THR_PRIORITY		0x40
 
 #define GCE_GCTL_VALUE			0x48
+#define GCE_CTRL_BY_SW				GENMASK(2, 0)
 
 #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
 #define CMDQ_THR_ENABLED		0x1
@@ -129,7 +130,8 @@ static void cmdq_init(struct cmdq *cmdq)
 
 	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
 	if (cmdq->control_by_sw)
-		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
+		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+
 	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
 	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
 		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
-- 
2.25.1


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[PATCH v10, 2/4] mailbox: mtk-cmdq: add gce software ddr enable private data

[Yongqiang Niu]

if gce work control by software, we need set software enable
for MT8186 Soc

there is a handshake flow between gce and ddr hardware,
if not set ddr enable flag of gce, ddr will fall into idle
mode, then gce instructions will not process done.
we need set this flag of gce to tell ddr when gce is idle or busy
controlled by software flow.

0x48[2:0] means control by software
0x48[18:16] means ddr enable
0x48[2:0] is pre-condition of 0x48[18:16].
if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same
time.
and only these bits is useful, other bits is useless bits

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index c3cb24f51699..d2363c6b8b7a 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -39,6 +39,7 @@
 
 #define GCE_GCTL_VALUE			0x48
 #define GCE_CTRL_BY_SW				GENMASK(2, 0)
+#define GCE_DDR_EN				GENMASK(18, 16)
 
 #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
 #define CMDQ_THR_ENABLED		0x1
@@ -81,6 +82,7 @@ struct cmdq {
 	bool			suspended;
 	u8			shift_pa;
 	bool			control_by_sw;
+	bool			sw_ddr_en;
 	u32			gce_num;
 };
 
@@ -88,6 +90,7 @@ struct gce_plat {
 	u32 thread_nr;
 	u8 shift;
 	bool control_by_sw;
+	bool sw_ddr_en;
 	u32 gce_num;
 };
 
@@ -127,10 +130,16 @@ static void cmdq_thread_resume(struct cmdq_thread *thread)
 static void cmdq_init(struct cmdq *cmdq)
 {
 	int i;
+	u32 gctl_regval = 0;
 
 	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
 	if (cmdq->control_by_sw)
-		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+		gctl_regval = GCE_CTRL_BY_SW;
+	if (cmdq->sw_ddr_en)
+		gctl_regval |= GCE_DDR_EN;
+
+	if (gctl_regval)
+		writel(gctl_regval, cmdq->base + GCE_GCTL_VALUE);
 
 	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
 	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
@@ -545,6 +554,7 @@ static int cmdq_probe(struct platform_device *pdev)
 	cmdq->thread_nr = plat_data->thread_nr;
 	cmdq->shift_pa = plat_data->shift;
 	cmdq->control_by_sw = plat_data->control_by_sw;
+	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
 	cmdq->gce_num = plat_data->gce_num;
 	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
 	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
-- 
2.25.1


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[PATCH v10, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow

[Yongqiang Niu]

add gce ddr enable control flow when gce suspend/resume

when all cmdq instruction task has been processed done,
we need set this gce ddr enable to disable status to tell
cmdq hardware gce there is none task need process, and the hardware
can go into idle mode and no access ddr anymore, then the spm can go
into suspend.

the original issue is gce still access ddr when cmdq suspend function
call, but there is no task run.
so, we need control gce access ddr with this flow.
when cmdq suspend function, there is no task need process, we can
disable gce access ddr, to make sure system go into suspend success.

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index d2363c6b8b7a..53904511598d 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -94,6 +94,18 @@ struct gce_plat {
 	u32 gce_num;
 };
 
+static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
+{
+	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
+
+	if (enable)
+		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+	else
+		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+
+	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
+}
+
 u8 cmdq_get_shift_pa(struct mbox_chan *chan)
 {
 	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
@@ -322,6 +334,9 @@ static int cmdq_suspend(struct device *dev)
 	if (task_running)
 		dev_warn(dev, "exist running task(s) in suspend\n");
 
+	if (cmdq->sw_ddr_en)
+		cmdq_sw_ddr_enable(cmdq, false);
+
 	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
 
 	return 0;
@@ -333,6 +348,10 @@ static int cmdq_resume(struct device *dev)
 
 	WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
 	cmdq->suspended = false;
+
+	if (cmdq->sw_ddr_en)
+		cmdq_sw_ddr_enable(cmdq, true);
+
 	return 0;
 }
 
@@ -340,6 +359,9 @@ static int cmdq_remove(struct platform_device *pdev)
 {
 	struct cmdq *cmdq = platform_get_drvdata(pdev);
 
+	if (cmdq->sw_ddr_en)
+		cmdq_sw_ddr_enable(cmdq, false);
+
 	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
 	return 0;
 }
-- 
2.25.1


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[PATCH v10, 4/4] mailbox: mtk-cmdq: add MT8186 support

[Yongqiang Niu]

add MT8186 cmdq support

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 53904511598d..c5229f377c5e 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -694,9 +694,18 @@ static const struct gce_plat gce_plat_v6 = {
 	.gce_num = 2
 };
 
+static const struct gce_plat gce_plat_v7 = {
+	.thread_nr = 24,
+	.shift = 3,
+	.control_by_sw = true,
+	.sw_ddr_en = true,
+	.gce_num = 1
+};
+
 static const struct of_device_id cmdq_of_ids[] = {
 	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
 	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
+	{.compatible = "mediatek,mt8186-gce", .data = (void *)&gce_plat_v7},
 	{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
 	{.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5},
 	{.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6},
-- 
2.25.1


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Re: [PATCH v10, 1/4] mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition instead of number

[CK Hu (胡俊光)]

Hi, Yongqiang:

On Mon, 2022-10-10 at 16:50 +0800, Yongqiang Niu wrote:
> Use GCE_CTRL_BY_SW definition instead of number

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 9465f9081515..c3cb24f51699 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -38,6 +38,7 @@
>  #define CMDQ_THR_PRIORITY		0x40
>  
>  #define GCE_GCTL_VALUE			0x48
> +#define GCE_CTRL_BY_SW				GENMASK(2, 0)
>  
>  #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
>  #define CMDQ_THR_ENABLED		0x1
> @@ -129,7 +130,8 @@ static void cmdq_init(struct cmdq *cmdq)
>  
>  	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
>  	if (cmdq->control_by_sw)
> -		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
> +		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> +
>  	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base +
> CMDQ_THR_SLOT_CYCLES);
>  	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
>  		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
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Re: [PATCH v10, 2/4] mailbox: mtk-cmdq: add gce software ddr enable private data

[CK Hu (胡俊光)]

Hi, Yongqiang:

On Mon, 2022-10-10 at 16:50 +0800, Yongqiang Niu wrote:
> if gce work control by software, we need set software enable
> for MT8186 Soc
> 
> there is a handshake flow between gce and ddr hardware,
> if not set ddr enable flag of gce, ddr will fall into idle
> mode, then gce instructions will not process done.
> we need set this flag of gce to tell ddr when gce is idle or busy
> controlled by software flow.
> 
> 0x48[2:0] means control by software
> 0x48[18:16] means ddr enable
> 0x48[2:0] is pre-condition of 0x48[18:16].
> if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same
> time.
> and only these bits is useful, other bits is useless bits

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index c3cb24f51699..d2363c6b8b7a 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -39,6 +39,7 @@
>  
>  #define GCE_GCTL_VALUE			0x48
>  #define GCE_CTRL_BY_SW				GENMASK(2, 0)
> +#define GCE_DDR_EN				GENMASK(18, 16)
>  
>  #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
>  #define CMDQ_THR_ENABLED		0x1
> @@ -81,6 +82,7 @@ struct cmdq {
>  	bool			suspended;
>  	u8			shift_pa;
>  	bool			control_by_sw;
> +	bool			sw_ddr_en;
>  	u32			gce_num;
>  };
>  
> @@ -88,6 +90,7 @@ struct gce_plat {
>  	u32 thread_nr;
>  	u8 shift;
>  	bool control_by_sw;
> +	bool sw_ddr_en;
>  	u32 gce_num;
>  };
>  
> @@ -127,10 +130,16 @@ static void cmdq_thread_resume(struct
> cmdq_thread *thread)
>  static void cmdq_init(struct cmdq *cmdq)
>  {
>  	int i;
> +	u32 gctl_regval = 0;
>  
>  	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
>  	if (cmdq->control_by_sw)
> -		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> +		gctl_regval = GCE_CTRL_BY_SW;
> +	if (cmdq->sw_ddr_en)
> +		gctl_regval |= GCE_DDR_EN;
> +
> +	if (gctl_regval)
> +		writel(gctl_regval, cmdq->base + GCE_GCTL_VALUE);
>  
>  	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base +
> CMDQ_THR_SLOT_CYCLES);
>  	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
> @@ -545,6 +554,7 @@ static int cmdq_probe(struct platform_device
> *pdev)
>  	cmdq->thread_nr = plat_data->thread_nr;
>  	cmdq->shift_pa = plat_data->shift;
>  	cmdq->control_by_sw = plat_data->control_by_sw;
> +	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
>  	cmdq->gce_num = plat_data->gce_num;
>  	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
>  	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler,
> IRQF_SHARED,
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Re: [PATCH v10, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow

[CK Hu (胡俊光)]

Hi, Yongqiang:

On Mon, 2022-10-10 at 16:50 +0800, Yongqiang Niu wrote:
> add gce ddr enable control flow when gce suspend/resume
> 
> when all cmdq instruction task has been processed done,
> we need set this gce ddr enable to disable status to tell
> cmdq hardware gce there is none task need process, and the hardware
> can go into idle mode and no access ddr anymore, then the spm can go
> into suspend.
> 
> the original issue is gce still access ddr when cmdq suspend function
> call, but there is no task run.
> so, we need control gce access ddr with this flow.
> when cmdq suspend function, there is no task need process, we can
> disable gce access ddr, to make sure system go into suspend success.

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index d2363c6b8b7a..53904511598d 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -94,6 +94,18 @@ struct gce_plat {
>  	u32 gce_num;
>  };
>  
> +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
> +{
> +	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> +
> +	if (enable)
> +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> GCE_GCTL_VALUE);
> +	else
> +		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> +
> +	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
> +}
> +
>  u8 cmdq_get_shift_pa(struct mbox_chan *chan)
>  {
>  	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq,
> mbox);
> @@ -322,6 +334,9 @@ static int cmdq_suspend(struct device *dev)
>  	if (task_running)
>  		dev_warn(dev, "exist running task(s) in suspend\n");
>  
> +	if (cmdq->sw_ddr_en)
> +		cmdq_sw_ddr_enable(cmdq, false);
> +
>  	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
>  
>  	return 0;
> @@ -333,6 +348,10 @@ static int cmdq_resume(struct device *dev)
>  
>  	WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
>  	cmdq->suspended = false;
> +
> +	if (cmdq->sw_ddr_en)
> +		cmdq_sw_ddr_enable(cmdq, true);
> +
>  	return 0;
>  }
>  
> @@ -340,6 +359,9 @@ static int cmdq_remove(struct platform_device
> *pdev)
>  {
>  	struct cmdq *cmdq = platform_get_drvdata(pdev);
>  
> +	if (cmdq->sw_ddr_en)
> +		cmdq_sw_ddr_enable(cmdq, false);
> +
>  	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
>  	return 0;
>  }
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Re: [PATCH v10, 4/4] mailbox: mtk-cmdq: add MT8186 support

[CK Hu (胡俊光)]

Hi, Yongqiang:

On Mon, 2022-10-10 at 16:50 +0800, Yongqiang Niu wrote:
> add MT8186 cmdq support

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 53904511598d..c5229f377c5e 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -694,9 +694,18 @@ static const struct gce_plat gce_plat_v6 = {
>  	.gce_num = 2
>  };
>  
> +static const struct gce_plat gce_plat_v7 = {
> +	.thread_nr = 24,
> +	.shift = 3,
> +	.control_by_sw = true,
> +	.sw_ddr_en = true,
> +	.gce_num = 1
> +};
> +
>  static const struct of_device_id cmdq_of_ids[] = {
>  	{.compatible = "mediatek,mt8173-gce", .data = (void
> *)&gce_plat_v2},
>  	{.compatible = "mediatek,mt8183-gce", .data = (void
> *)&gce_plat_v3},
> +	{.compatible = "mediatek,mt8186-gce", .data = (void
> *)&gce_plat_v7},
>  	{.compatible = "mediatek,mt6779-gce", .data = (void
> *)&gce_plat_v4},
>  	{.compatible = "mediatek,mt8192-gce", .data = (void
> *)&gce_plat_v5},
>  	{.compatible = "mediatek,mt8195-gce", .data = (void
> *)&gce_plat_v6},
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Re: [PATCH v10, 4/4] mailbox: mtk-cmdq: add MT8186 support

[Yongqiang Niu (牛永强)]

hi jassi

do you have any comment about this series patch?



On Tue, 2022-10-18 at 05:52 +0000, CK Hu (胡俊光) wrote:
> Hi, Yongqiang:
> 
> On Mon, 2022-10-10 at 16:50 +0800, Yongqiang Niu wrote:
> > add MT8186 cmdq support
> 
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> 
> > 
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >  drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > index 53904511598d..c5229f377c5e 100644
> > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > @@ -694,9 +694,18 @@ static const struct gce_plat gce_plat_v6 = {
> >  	.gce_num = 2
> >  };
> >  
> > +static const struct gce_plat gce_plat_v7 = {
> > +	.thread_nr = 24,
> > +	.shift = 3,
> > +	.control_by_sw = true,
> > +	.sw_ddr_en = true,
> > +	.gce_num = 1
> > +};
> > +
> >  static const struct of_device_id cmdq_of_ids[] = {
> >  	{.compatible = "mediatek,mt8173-gce", .data = (void
> > *)&gce_plat_v2},
> >  	{.compatible = "mediatek,mt8183-gce", .data = (void
> > *)&gce_plat_v3},
> > +	{.compatible = "mediatek,mt8186-gce", .data = (void
> > *)&gce_plat_v7},
> >  	{.compatible = "mediatek,mt6779-gce", .data = (void
> > *)&gce_plat_v4},
> >  	{.compatible = "mediatek,mt8192-gce", .data = (void
> > *)&gce_plat_v5},
> >  	{.compatible = "mediatek,mt8195-gce", .data = (void
> > *)&gce_plat_v6},
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