* [PATCH] This commit updates the armada-37xx and armada-372x device tree files to add L1 and L2 cache information. This information is provided by the following sources:
@ 2022-10-21 4:46 Steven
0 siblings, 0 replies; only message in thread
From: Steven @ 2022-10-21 4:46 UTC (permalink / raw)
To: gregory.clement; +Cc: me, linux-arm-kernel
Description of the Armada 3700 series cache configuration:
https://datasheet.datasheetarchive.com/originals/crawler/marvell.com/18bd41681c6d1d9932>
Description of the ARM Cortex A53 L1 and L2 memory systems:
https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system/about-the-l1-me>
---
arch/arm64/boot/dts/marvell/armada-372x.dtsi | 9 +++++++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 19 +++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-372x.dtsi b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
index 5ce55bdbb995..a9c36d997082 100644
--- a/arch/arm64/boot/dts/marvell/armada-372x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
@@ -22,6 +22,15 @@ cpu1: cpu@1 {
reg = <0x1>;
clocks = <&nb_periph_clk 16>;
enable-method = "psci";
+ /* https://datasheet.datasheetarchive.com/originals/crawler/marvell.com/18bd41681c6d1d9932acc66ac0482950.pdf */
+ /* https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system/about-the-l1-memory-system */
+ d-cache-size = <0x8000>; // 32KB 4-way set-associative data cache
+ d-cache-line-size = <64>; // Fixed line length of 64 bytes
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>; // 32kB 2-way set-associative data cache
+ i-cache-line-size = <64>; // Fixed line length of 64 bytes
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
};
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index df152c72276b..d1f7b1acd54b 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -46,6 +46,25 @@ cpu0: cpu@0 {
reg = <0>;
clocks = <&nb_periph_clk 16>;
enable-method = "psci";
+ /* https://datasheet.datasheetarchive.com/originals/crawler/marvell.com/18bd41681c6d1d9932> */
+ /* https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system/about-the-l1-me> */
+ d-cache-size = <0x8000>; // 32KB 4-way set-associative data cache
+ d-cache-line-size = <64>; // Fixed line length of 64 bytes
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>; // 32kB 2-way set-associative data cache
+ i-cache-line-size = <64>; // Fixed line length of 64 bytes
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ /* https://datasheet.datasheetarchive.com/originals/crawler/marvell.com/18bd41681c6d1d9932> */
+ /* https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system/about-the-l1-me> */
+ compatible = "cache";
+ cache-size = <0x40000>; // 256kB
+ cache-line-size = <64>; // Fixed line length of 64 bytes
+ cache-sets = <256>; // 256kB(size)/64(line-size)=4000ways/16-way set
+ cache-level = <2>;
};
};
--
2.35.1
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2022-10-21 4:46 [PATCH] This commit updates the armada-37xx and armada-372x device tree files to add L1 and L2 cache information. This information is provided by the following sources: Steven
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