From: Christoph Niedermaier <cniedermaier@dh-electronics.com>
To: <linux-arm-kernel@lists.infradead.org>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Peng Fan <peng.fan@nxp.com>, Shawn Guo <shawnguo@kernel.org>,
Marek Vasut <marex@denx.de>, Fabio Estevam <festevam@denx.de>,
NXP Linux Team <linux-imx@nxp.com>, <kernel@dh-electronics.com>
Subject: [PATCH V2 4/4] ARM: dts: imx6ull-dhcom: Add DHSOM based DRC02 board
Date: Wed, 23 Nov 2022 18:36:01 +0100 [thread overview]
Message-ID: <20221123173601.13291-4-cniedermaier@dh-electronics.com> (raw)
In-Reply-To: <20221123173601.13291-1-cniedermaier@dh-electronics.com>
Add DT for DH DRC02 unit, which is a universal controller device.
The system has two ethernet ports, two CANs, RS485 and RS232, USB,
capacitive buttons and an OLED display. For this board a DHCOM
i.MX6ULL SoM configuration without WiFi/BT is used. The interface
is used for the SD card instead.
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
---
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Reorder comments in front of a block
- Reorder compatible and reg to the beginning of a node
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ull-dhcom-drc02.dts | 146 ++++++++++++++++++++++++++++++
2 files changed, 147 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ull-dhcom-drc02.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ecd8a91a83c1..74837e385dfc 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -739,6 +739,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-colibri-wifi-iris.dtb \
imx6ull-colibri-wifi-iris-v2.dtb \
+ imx6ull-dhcom-drc02.dtb \
imx6ull-dhcom-pdk2.dtb \
imx6ull-dhcom-picoitx.dtb \
imx6ull-jozacp.dtb \
diff --git a/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts b/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts
new file mode 100644
index 000000000000..e2ad828d9018
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2022 DH electronics GmbH
+ *
+ * DHCOM iMX6ULL variant:
+ * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2
+ * DHCOR PCB number: 578-200 or newer
+ * DHCOM PCB number: 579-200 or newer
+ * DRC02 PCB number: 568-100 or newer (2nd ethernet by internal USB device)
+ */
+/dts-v1/;
+
+#include "imx6ull-dhcom-som.dtsi"
+#include "imx6ull-dhcom-som-cfg-sdcard.dtsi"
+
+/ {
+ model = "DH electronics i.MX6ULL DHCOM on DRC02";
+ compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som",
+ "dh,imx6ull-dhcor-som", "fsl,imx6ull";
+};
+
+/*
+ * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
+ * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1
+ * node below.
+ */
+&can2 {
+ status = "okay";
+};
+
+&fec1 {
+ phy-handle = <&mdio1_phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio1_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ clock-names = "rmii-ref";
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>;
+ pinctrl-names = "default";
+ reset-assert-us = <500>;
+ reset-deassert-us = <500>;
+ reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ smsc,disable-energy-detect; /* Make plugin detection reliable */
+ };
+ };
+};
+
+/* Disabled, because 2nd ethernet is provided by an internal USB device */
+&fec2 {
+ status = "disabled";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "DRC02-In2",
+ "", "", "", "",
+ "", "", "DHCOM-I", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "DRC02-HW0", "DRC02-HW1", "DHCOM-M",
+ "DRC02-HW2", "DHCOM-U", "DHCOM-T", "DHCOM-S",
+ "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
+ "DHCOM-N", "", "", "";
+ /*
+ * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
+ * GPIO line, however the i.MX6ULL UART driver assumes RX happens
+ * during TX anyway and that it only controls drive enable DE
+ * line. Hence, the RX is always enabled here.
+ */
+ rs485-rx-en-hog {
+ gpio-hog;
+ gpios = <25 0>; /* GPIO Q */
+ line-name = "rs485-rx-en";
+ output-low;
+ };
+};
+
+&gpio5 {
+ gpio-line-names =
+ "DHCOM-A", "DHCOM-B", "DHCOM-C", "DRC02-Out2",
+ "DHCOM-E", "", "", "DRC02-Out1",
+ "DRC02-In1", "DHCOM-H", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+/* DHCOM I2C2 */
+&i2c1 {
+ eeprom@56 {
+ compatible = "atmel,24c04";
+ reg = <0x56>;
+ pagesize = <16>;
+ };
+};
+
+&uart1 {
+ /delete-property/ uart-has-rtscts;
+ rts-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */
+ cts-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; /* GPIO M */
+};
+
+/* Use UART as RS485 */
+&uart2 {
+ /delete-property/ uart-has-rtscts;
+ linux,rs485-enabled-at-boot-time;
+ rts-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* GPIO P */
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1-grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
+ >;
+ };
+};
--
2.11.0
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prev parent reply other threads:[~2022-11-23 18:24 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-23 17:35 [PATCH V2 1/4] dt-bindings: arm: fsl: Add PDK2, PicoITX and DRC02 boards for the DHCOM i.MX6ULL SoM Christoph Niedermaier
2022-11-23 17:35 ` [PATCH V2 2/4] ARM: dts: imx6ull-dhcom: Add DH electronics DHCOM i.MX6ULL SoM and PDK2 board Christoph Niedermaier
2022-12-31 10:01 ` Shawn Guo
2022-11-23 17:36 ` [PATCH V2 3/4] ARM: dts: imx6ull-dhcom: Add DHCOM based PicoITX board Christoph Niedermaier
2022-11-23 17:36 ` Christoph Niedermaier [this message]
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