[PATCH 0/2] ARM: mmp: PXA168 timer fixes

[PATCH 0/2] ARM: mmp: PXA168 timer fixes

[Doug Brown]

This series contains a couple of bug fixes for the PXA168 timer. The
clock wasn't assigned in pxa168.dtsi which eventually resulted in a hang
at every boot after the clock was disabled. Also, the timer read
function wasn't waiting long enough to capture the new timer value,
which resulted in erroneous high CPU usage percent being reported with
CONFIG_NO_HZ_IDLE=y.

I don't have any other MMP systems to test with, but I suspect the timer
read delay problem also affected them. For example, the OLPC XO-4 kernel
disabled CONFIG_NO_HZ due to incorrect high CPU usage reporting:

http://dev.laptop.org/git/olpc-kernel/commit?h=arm-3.5&id=5bd2520f8f51fc44911ec7a86b84f41a1f3e384c

CCing soc@kernel.org because I didn't receive any responses when I
submitted these last time and was hoping these fixes could get merged.

Doug Brown (2):
  ARM: dts: pxa168: add timer reset and clock
  ARM: mmp: fix timer_read delay

 arch/arm/boot/dts/pxa168.dtsi |  2 ++
 arch/arm/mach-mmp/time.c      | 11 +++++++----
 2 files changed, 9 insertions(+), 4 deletions(-)

-- 
2.34.1


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[PATCH 1/2] ARM: dts: pxa168: add timer reset and clock

[Doug Brown]

The timer was missing the clock and reset like the other peripherals.
Add them to allow the timer to continue working after boot completes.

Signed-off-by: Doug Brown <doug@schmorgal.com>
---
 arch/arm/boot/dts/pxa168.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index 4fe7735c7c58..16212b912b94 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -53,6 +53,8 @@ timer0: timer@d4014000 {
 				compatible = "mrvl,mmp-timer";
 				reg = <0xd4014000 0x100>;
 				interrupts = <13>;
+				clocks = <&soc_clocks PXA168_CLK_TIMER>;
+				resets = <&soc_clocks PXA168_CLK_TIMER>;
 			};
 
 			uart1: serial@d4017000 {
-- 
2.34.1


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[PATCH 2/2] ARM: mmp: fix timer_read delay

[Doug Brown]

timer_read() was using an empty 100-iteration loop to wait for the
TMR_CVWR register to capture the latest timer counter value. The delay
wasn't long enough. This resulted in CPU idle time being extremely
underreported on PXA168 with CONFIG_NO_HZ_IDLE=y.

Switch to the approach used in the vendor kernel, which implements the
capture delay by reading TMR_CVWR a few times instead.

Fixes: 49cbe78637eb ("[ARM] pxa: add base support for Marvell's PXA168 processor line")
Signed-off-by: Doug Brown <doug@schmorgal.com>
---
 arch/arm/mach-mmp/time.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 41b2e8abc9e6..708816caf859 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -43,18 +43,21 @@
 static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
 
 /*
- * FIXME: the timer needs some delay to stablize the counter capture
+ * Read the timer through the CVWR register. Delay is required after requesting
+ * a read. The CR register cannot be directly read due to metastability issues
+ * documented in the PXA168 software manual.
  */
 static inline uint32_t timer_read(void)
 {
-	int delay = 100;
+	uint32_t val;
+	int delay = 3;
 
 	__raw_writel(1, mmp_timer_base + TMR_CVWR(1));
 
 	while (delay--)
-		cpu_relax();
+		val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
 
-	return __raw_readl(mmp_timer_base + TMR_CVWR(1));
+	return val;
 }
 
 static u64 notrace mmp_read_sched_clock(void)
-- 
2.34.1


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