[PATCH v4 00/20] Permission Indirection Extension

[PATCH v4 00/20] Permission Indirection Extension

[Joey Gouly]

Hi all,

This series implements the Permission Indirection Extension introduced in 2022
VMSA enhancements [1].

Changes since v3 [2]:
	- Rebased onto for-next/feat_mops
	- Enabled TCR2 in new HCRX_HOST_FLAGS/HCRX_GUEST_FLAGS
	- Use ARM64_CPUID_FIELDS in cpufeature.c
	- Add Marc Z's R-b tags

The Permission Indirection Extension is a new way to set memory permissions.
Instead of directly encoding the permission in the Page Table Entry (PTE),
fields in the PTEs are used to index into an array of permissions specified in
a register. This indirection provides greater flexibility, greater encoding
density and enables the representation of new permissions.

The PTEs bit that are repurposed for use with permission indirection are:
	54 PTE_UXN
	53 PTE_PXN
	51 PTE_DBM
	6 PTE_USER

The way that PIE is implemented in this patchset is that the encodings are
picked such that they match how Linux currently sets the bits in the PTEs, so
none of the page table handling has changed. This means this patchset keeps the
same functionality as currently implemented, but allows for future expansion.

Enabling PIE is also a prerequisite for implementing the Guarded Control Stack
Extension (GCS).

Another related extension is the Permission Overlay Extension, which is not
covered by this patch set, but is mentioned in patch 5 as half of PIE encoding
values apply an overlay. However, since overlays are not currently enabled, they
act as all the other permissions do.

This first few patches are adding the new system registers, and cpufeature
capabilities. Then KVM support for save/restore of the new registers is added.
Finally the new Permission Indirection registers are set and the new feature is
enabled.

Thanks,
Joey

[1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2023-May/833014.html

Joey Gouly (20):
  arm64/sysreg: Add ID register ID_AA64MMFR3
  arm64/sysreg: add system registers TCR2_ELx
  arm64/sysreg: update HCRX_EL2 register
  arm64/sysreg: add PIR*_ELx registers
  arm64: cpufeature: add system register ID_AA64MMFR3
  arm64: cpufeature: add TCR2 cpucap
  arm64: cpufeature: add Permission Indirection Extension cpucap
  KVM: arm64: Save/restore TCR2_EL1
  KVM: arm64: Save/restore PIE registers
  KVM: arm64: expose ID_AA64MMFR3_EL1 to guests
  arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS
  arm64: add PTE_WRITE to PROT_SECT_NORMAL
  arm64: reorganise PAGE_/PROT_ macros
  arm64: disable EL2 traps for PIE
  arm64: add encodings of PIRx_ELx registers
  arm64: enable Permission Indirection Extension (PIE)
  arm64: transfer permission indirection settings to EL2
  arm64: Document boot requirements for PIE
  KVM: selftests: get-reg-list: support ID register features
  KVM: selftests: get-reg-list: add Permission Indirection registers

 Documentation/arm64/booting.rst               |  26 +++
 arch/arm64/include/asm/cpu.h                  |   1 +
 arch/arm64/include/asm/el2_setup.h            |  11 +-
 arch/arm64/include/asm/kernel-pgtable.h       |   8 +-
 arch/arm64/include/asm/kvm_arm.h              |   4 +-
 arch/arm64/include/asm/kvm_host.h             |   5 +
 arch/arm64/include/asm/pgtable-hwdef.h        |   8 +
 arch/arm64/include/asm/pgtable-prot.h         | 122 ++++++++++---
 arch/arm64/include/asm/sysreg.h               |  19 ++
 arch/arm64/kernel/cpufeature.c                |  24 +++
 arch/arm64/kernel/cpuinfo.c                   |   1 +
 arch/arm64/kernel/head.S                      |   8 +-
 arch/arm64/kernel/hyp-stub.S                  |  18 ++
 arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h    |  12 ++
 arch/arm64/kvm/sys_regs.c                     |   5 +-
 arch/arm64/mm/proc.S                          |  19 +-
 arch/arm64/tools/cpucaps                      |   2 +
 arch/arm64/tools/sysreg                       | 165 +++++++++++++++++-
 .../selftests/kvm/aarch64/get-reg-list.c      |  53 +++++-
 19 files changed, 467 insertions(+), 44 deletions(-)

-- 
2.25.1


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[PATCH v4 01/20] arm64/sysreg: Add ID register ID_AA64MMFR3

[Joey Gouly]

Add the new ID register ID_AA64MMFR3, according to DDI0601 2023-03.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/tools/sysreg | 72 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c9a0d1fa3209..32b5db8de4dd 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1538,6 +1538,78 @@ UnsignedEnum	3:0	CnP
 EndEnum
 EndSysreg
 
+Sysreg	ID_AA64MMFR3_EL1	3	0	0	7	3
+UnsignedEnum	63:60	Spec_FPACC
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	59:56	ADERR
+	0b0000	NI
+	0b0001	DEV_ASYNC
+	0b0010	FEAT_ADERR
+	0b0011	FEAT_ADERR_IND
+EndEnum
+UnsignedEnum	55:52	SDERR
+	0b0000	NI
+	0b0001	DEV_SYNC
+	0b0010	FEAT_ADERR
+	0b0011	FEAT_ADERR_IND
+EndEnum
+Res0	51:48
+UnsignedEnum	47:44	ANERR
+	0b0000	NI
+	0b0001	ASYNC
+	0b0010	FEAT_ANERR
+	0b0011	FEAT_ANERR_IND
+EndEnum
+UnsignedEnum	43:40	SNERR
+	0b0000	NI
+	0b0001	SYNC
+	0b0010	FEAT_ANERR
+	0b0011	FEAT_ANERR_IND
+EndEnum
+UnsignedEnum	39:36	D128_2
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	35:32	D128
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	31:28	MEC
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	27:24	AIE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	23:20	S2POE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	19:16	S1POE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	15:12	S2PIE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	11:8	S1PIE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	7:4	SCTLRX
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+UnsignedEnum	3:0	TCRX
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+EndSysreg
+
 Sysreg	SCTLR_EL1	3	0	1	0	0
 Field	63	TIDCP
 Field	62	SPINTMASK
-- 
2.25.1


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[PATCH v4 02/20] arm64/sysreg: add system registers TCR2_ELx

[Joey Gouly]

Add definitions of TCR2_EL1, TCR2_EL12 and TCR_EL2 registers.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/tools/sysreg | 42 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 32b5db8de4dd..bb3fe6c8f734 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2225,6 +2225,48 @@ Sysreg	TTBR1_EL1	3	0	2	0	1
 Fields	TTBRx_EL1
 EndSysreg
 
+SysregFields	TCR2_EL1x
+Res0	63:16
+Field	15	DisCH1
+Field	14	DisCH0
+Res0	13:12
+Field	11	HAFT
+Field	10	PTTWI
+Res0	9:6
+Field	5	D128
+Field	4	AIE
+Field	3	POE
+Field	2	E0POE
+Field	1	PIE
+Field	0	PnCH
+EndSysregFields
+
+Sysreg	TCR2_EL1	3	0	2	0	3
+Fields	TCR2_EL1x
+EndSysreg
+
+Sysreg	TCR2_EL12	3	5	2	0	3
+Fields	TCR2_EL1x
+EndSysreg
+
+Sysreg	TCR2_EL2	3	4	2	0	3
+Res0	63:16
+Field	15	DisCH1
+Field	14	DisCH0
+Field	13	AMEC1
+Field	12	AMEC0
+Field	11	HAFT
+Field	10	PTTWI
+Field	9:8	SKL1
+Field	7:6	SKL0
+Field	5	D128
+Field	4	AIE
+Field	3	POE
+Field	2	E0POE
+Field	1	PIE
+Field	0	PnCH
+EndSysreg
+
 Sysreg	LORSA_EL1	3	0	10	4	0
 Res0	63:52
 Field	51:16	SA
-- 
2.25.1


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[PATCH v4 03/20] arm64/sysreg: update HCRX_EL2 register

[Joey Gouly]

Update the HCRX_EL2 register with new bit definitions.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/tools/sysreg | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index bb3fe6c8f734..c11ec0a4e8f6 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2106,7 +2106,17 @@ Fields	ZCR_ELx
 EndSysreg
 
 Sysreg	HCRX_EL2	3	4	1	2	2
-Res0	63:12
+Res0	63:23
+Field	22	GCSEn
+Field	21	EnIDCP128
+Field	20	EnSDERR
+Field	19	TMEA
+Field	18	EnSNERR
+Field	17	D128En
+Field	16	PTTWI
+Field	15	SCTLR2En
+Field	14	TCR2En
+Res0	13:12
 Field	11	MSCEn
 Field	10	MCE2
 Field	9	CMOW
-- 
2.25.1


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[PATCH v4 04/20] arm64/sysreg: add PIR*_ELx registers

[Joey Gouly]

Add definitions of PIR_EL1, PIR_EL12, PIRE0_EL1, PIRE0_EL12, and
PIR_EL2 registers.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/include/asm/sysreg.h | 19 ++++++++++++++++
 arch/arm64/tools/sysreg         | 39 +++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e72d9aaab6b1..11b8ef74f239 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -758,6 +758,25 @@
 #define ICH_VTR_TDS_SHIFT	19
 #define ICH_VTR_TDS_MASK	(1 << ICH_VTR_TDS_SHIFT)
 
+/*
+ * Permission Indirection Extension (PIE) permission encodings.
+ * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
+ */
+#define PIE_NONE_O	0x0
+#define PIE_R_O		0x1
+#define PIE_X_O		0x2
+#define PIE_RX_O	0x3
+#define PIE_RW_O	0x5
+#define PIE_RWnX_O	0x6
+#define PIE_RWX_O	0x7
+#define PIE_R		0x8
+#define PIE_GCS		0x9
+#define PIE_RX		0xa
+#define PIE_RW		0xc
+#define PIE_RWX		0xe
+
+#define PIRx_ELx_PERM(idx, perm)	((perm) << ((idx) * 4))
+
 #define ARM64_FEATURE_FIELD_BITS	4
 
 /* Defined for compatibility only, do not add new users. */
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c11ec0a4e8f6..e08d88db700e 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2277,6 +2277,45 @@ Field	1	PIE
 Field	0	PnCH
 EndSysreg
 
+SysregFields PIRx_ELx
+Field	63:60	Perm15
+Field	59:56	Perm14
+Field	55:52	Perm13
+Field	51:48	Perm12
+Field	47:44	Perm11
+Field	43:40	Perm10
+Field	39:36	Perm9
+Field	35:32	Perm8
+Field	31:28	Perm7
+Field	27:24	Perm6
+Field	23:20	Perm5
+Field	19:16	Perm4
+Field	15:12	Perm3
+Field	11:8	Perm2
+Field	7:4	Perm1
+Field	3:0	Perm0
+EndSysregFields
+
+Sysreg	PIRE0_EL1	3	0	10	2	2
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	PIRE0_EL12	3	5	10	2	2
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	PIR_EL1		3	0	10	2	3
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	PIR_EL12	3	5	10	2	3
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	PIR_EL2		3	4	10	2	3
+Fields	PIRx_ELx
+EndSysreg
+
 Sysreg	LORSA_EL1	3	0	10	4	0
 Res0	63:52
 Field	51:16	SA
-- 
2.25.1


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[PATCH v4 05/20] arm64: cpufeature: add system register ID_AA64MMFR3

[Joey Gouly]

Add new system register ID_AA64MMFR3 to the cpufeature infrastructure.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/include/asm/cpu.h   |  1 +
 arch/arm64/kernel/cpufeature.c | 11 +++++++++++
 arch/arm64/kernel/cpuinfo.c    |  1 +
 3 files changed, 13 insertions(+)

diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index fd7a92219eea..e749838b9c5d 100644
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -56,6 +56,7 @@ struct cpuinfo_arm64 {
 	u64		reg_id_aa64mmfr0;
 	u64		reg_id_aa64mmfr1;
 	u64		reg_id_aa64mmfr2;
+	u64		reg_id_aa64mmfr3;
 	u64		reg_id_aa64pfr0;
 	u64		reg_id_aa64pfr1;
 	u64		reg_id_aa64zfr0;
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 3badc4fa7154..416c794207c1 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -398,6 +398,12 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 	ARM64_FTR_END,
 };
 
+static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
+	ARM64_FTR_END,
+};
+
 static const struct arm64_ftr_bits ftr_ctr[] = {
 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
@@ -724,6 +730,7 @@ static const struct __ftr_reg_entry {
 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
 			       &id_aa64mmfr1_override),
 	ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
+	ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3),
 
 	/* Op1 = 0, CRn = 1, CRm = 2 */
 	ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
@@ -1019,6 +1026,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
 	init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 	init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 	init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
+	init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3);
 	init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 	init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 	init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
@@ -1264,6 +1272,8 @@ void update_cpu_features(int cpu,
 				      info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 				      info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
+	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu,
+				      info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3);
 
 	taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 				      info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
@@ -1393,6 +1403,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id)
 	read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 	read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 	read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
+	read_sysreg_case(SYS_ID_AA64MMFR3_EL1);
 	read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 	read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 	read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 076a124255d0..58622dc85917 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -447,6 +447,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
 	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
 	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
 	info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
+	info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1);
 	info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
 	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
 	info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
-- 
2.25.1


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[PATCH v4 06/20] arm64: cpufeature: add TCR2 cpucap

[Joey Gouly]

This capability indicates if the system supports the TCR2_ELx system register.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/kernel/cpufeature.c | 6 ++++++
 arch/arm64/tools/cpucaps       | 1 +
 2 files changed, 7 insertions(+)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 416c794207c1..12107c07fb77 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2674,6 +2674,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.cpu_enable = cpu_enable_mops,
 		ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP)
 	},
+	{
+		.capability = ARM64_HAS_TCR2,
+		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
+		.matches = has_cpuid_feature,
+		ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP)
+	},
 	{},
 };
 
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index debc4609f129..ebf5d4407b64 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -44,6 +44,7 @@ HAS_RAS_EXTN
 HAS_RNG
 HAS_SB
 HAS_STAGE2_FWB
+HAS_TCR2
 HAS_TIDCP1
 HAS_TLB_RANGE
 HAS_VIRT_HOST_EXTN
-- 
2.25.1


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[PATCH v4 07/20] arm64: cpufeature: add Permission Indirection Extension cpucap

[Joey Gouly]

This indicates if the system supports PIE. This is a CPUCAP_BOOT_CPU_FEATURE
as the boot CPU will enable PIE if it has it, so secondary CPUs must also
have this feature.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/kernel/cpufeature.c | 7 +++++++
 arch/arm64/tools/cpucaps       | 1 +
 2 files changed, 8 insertions(+)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 12107c07fb77..6607a9ae8418 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2680,6 +2680,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.matches = has_cpuid_feature,
 		ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP)
 	},
+	{
+		.desc = "Stage-1 Permission Indirection Extension (S1PIE)",
+		.capability = ARM64_HAS_S1PIE,
+		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
+		.matches = has_cpuid_feature,
+		ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP)
+	},
 	{},
 };
 
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index ebf5d4407b64..19c23c4fa2da 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -40,6 +40,7 @@ HAS_NESTED_VIRT
 HAS_NO_FPSIMD
 HAS_NO_HW_PREFETCH
 HAS_PAN
+HAS_S1PIE
 HAS_RAS_EXTN
 HAS_RNG
 HAS_SB
-- 
2.25.1


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[PATCH v4 08/20] KVM: arm64: Save/restore TCR2_EL1

[Joey Gouly]

Define the new system register TCR2_EL1 and context switch it.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Zenghui Yu <yuzenghui@huawei.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/kvm_host.h          | 1 +
 arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 4 ++++
 arch/arm64/kvm/sys_regs.c                  | 1 +
 3 files changed, 6 insertions(+)

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 7e7e19ef6993..f2cfb9ef1eeb 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -279,6 +279,7 @@ enum vcpu_sysreg {
 	TTBR0_EL1,	/* Translation Table Base Register 0 */
 	TTBR1_EL1,	/* Translation Table Base Register 1 */
 	TCR_EL1,	/* Translation Control Register */
+	TCR2_EL1,	/* Extended Translation Control Register */
 	ESR_EL1,	/* Exception Syndrome Register */
 	AFSR0_EL1,	/* Auxiliary Fault Status Register 0 */
 	AFSR1_EL1,	/* Auxiliary Fault Status Register 1 */
diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
index 699ea1f8d409..16199a107a47 100644
--- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
+++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
@@ -44,6 +44,8 @@ static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
 	ctxt_sys_reg(ctxt, TTBR0_EL1)	= read_sysreg_el1(SYS_TTBR0);
 	ctxt_sys_reg(ctxt, TTBR1_EL1)	= read_sysreg_el1(SYS_TTBR1);
 	ctxt_sys_reg(ctxt, TCR_EL1)	= read_sysreg_el1(SYS_TCR);
+	if (cpus_have_final_cap(ARM64_HAS_TCR2))
+		ctxt_sys_reg(ctxt, TCR2_EL1)	= read_sysreg_el1(SYS_TCR2);
 	ctxt_sys_reg(ctxt, ESR_EL1)	= read_sysreg_el1(SYS_ESR);
 	ctxt_sys_reg(ctxt, AFSR0_EL1)	= read_sysreg_el1(SYS_AFSR0);
 	ctxt_sys_reg(ctxt, AFSR1_EL1)	= read_sysreg_el1(SYS_AFSR1);
@@ -114,6 +116,8 @@ static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
 	write_sysreg_el1(ctxt_sys_reg(ctxt, CPACR_EL1),	SYS_CPACR);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL1),	SYS_TTBR0);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL1),	SYS_TTBR1);
+	if (cpus_have_final_cap(ARM64_HAS_TCR2))
+		write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL1),	SYS_TCR2);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL1),	SYS_ESR);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL1),	SYS_AFSR0);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL1),	SYS_AFSR1);
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 6dae7fe91cfa..85aeb2ac0995 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1893,6 +1893,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	{ SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
 	{ SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
 	{ SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
+	{ SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },
 
 	PTRAUTH_KEY(APIA),
 	PTRAUTH_KEY(APIB),
-- 
2.25.1


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[PATCH v4 09/20] KVM: arm64: Save/restore PIE registers

[Joey Gouly]

Define the new system registers that PIE introduces and context switch them.
The PIE feature is still hidden from the ID register, and not exposed to a VM.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Zenghui Yu <yuzenghui@huawei.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/kvm_host.h          | 4 ++++
 arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 8 ++++++++
 arch/arm64/kvm/sys_regs.c                  | 2 ++
 3 files changed, 14 insertions(+)

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index f2cfb9ef1eeb..d9f079fbdaf4 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -340,6 +340,10 @@ enum vcpu_sysreg {
 	TFSR_EL1,	/* Tag Fault Status Register (EL1) */
 	TFSRE0_EL1,	/* Tag Fault Status Register (EL0) */
 
+	/* Permission Indirection Extension registers */
+	PIR_EL1,       /* Permission Indirection Register 1 (EL1) */
+	PIRE0_EL1,     /*  Permission Indirection Register 0 (EL1) */
+
 	/* 32bit specific registers. */
 	DACR32_EL2,	/* Domain Access Control Register */
 	IFSR32_EL2,	/* Instruction Fault Status Register */
diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
index 16199a107a47..bb6b571ec627 100644
--- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
+++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
@@ -55,6 +55,10 @@ static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
 	ctxt_sys_reg(ctxt, CONTEXTIDR_EL1) = read_sysreg_el1(SYS_CONTEXTIDR);
 	ctxt_sys_reg(ctxt, AMAIR_EL1)	= read_sysreg_el1(SYS_AMAIR);
 	ctxt_sys_reg(ctxt, CNTKCTL_EL1)	= read_sysreg_el1(SYS_CNTKCTL);
+	if (cpus_have_final_cap(ARM64_HAS_S1PIE)) {
+		ctxt_sys_reg(ctxt, PIR_EL1)	= read_sysreg_el1(SYS_PIR);
+		ctxt_sys_reg(ctxt, PIRE0_EL1)	= read_sysreg_el1(SYS_PIRE0);
+	}
 	ctxt_sys_reg(ctxt, PAR_EL1)	= read_sysreg_par();
 	ctxt_sys_reg(ctxt, TPIDR_EL1)	= read_sysreg(tpidr_el1);
 
@@ -127,6 +131,10 @@ static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
 	write_sysreg_el1(ctxt_sys_reg(ctxt, CONTEXTIDR_EL1), SYS_CONTEXTIDR);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, AMAIR_EL1),	SYS_AMAIR);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, CNTKCTL_EL1), SYS_CNTKCTL);
+	if (cpus_have_final_cap(ARM64_HAS_S1PIE)) {
+		write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1),	SYS_PIR);
+		write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1),	SYS_PIRE0);
+	}
 	write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1),	par_el1);
 	write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1),	tpidr_el1);
 
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 85aeb2ac0995..2a0125060911 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1943,6 +1943,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	{ SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
 
 	{ SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
+	{ SYS_DESC(SYS_PIRE0_EL1), access_vm_reg, reset_unknown, PIRE0_EL1 },
+	{ SYS_DESC(SYS_PIR_EL1), access_vm_reg, reset_unknown, PIR_EL1 },
 	{ SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 
 	{ SYS_DESC(SYS_LORSA_EL1), trap_loregion },
-- 
2.25.1


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[PATCH v4 10/20] KVM: arm64: expose ID_AA64MMFR3_EL1 to guests

[Joey Gouly]

Now that KVM context switches the appropriate registers, expose ID_AA64MMFR3_EL1
to guests to allow them to use the new features.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Zenghui Yu <yuzenghui@huawei.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kvm/sys_regs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 2a0125060911..a2e7f53a65ae 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1873,7 +1873,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	ID_SANITISED(ID_AA64MMFR0_EL1),
 	ID_SANITISED(ID_AA64MMFR1_EL1),
 	ID_SANITISED(ID_AA64MMFR2_EL1),
-	ID_UNALLOCATED(7,3),
+	ID_SANITISED(ID_AA64MMFR3_EL1),
 	ID_UNALLOCATED(7,4),
 	ID_UNALLOCATED(7,5),
 	ID_UNALLOCATED(7,6),
-- 
2.25.1


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[PATCH v4 11/20] arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS

[Joey Gouly]

With PIE enabled, the swapper PTEs would have a Permission Indirection Index
(PIIndex) of 0. A PIIndex of 0 is not currently used by any other PTEs.

To avoid using index 0 specifically for the swapper PTEs, mark them as
PTE_UXN and PTE_WRITE, so that they map to a PAGE_KERNEL_EXEC equivalent.

This also adds PTE_WRITE to KPTI_NG_PTE_FLAGS, which was tested by booting
with kpti=on.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
---
 arch/arm64/include/asm/kernel-pgtable.h | 8 ++++----
 arch/arm64/kernel/head.S                | 8 ++++----
 arch/arm64/mm/proc.S                    | 4 ++--
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h
index 186dd7f85b14..577773870b66 100644
--- a/arch/arm64/include/asm/kernel-pgtable.h
+++ b/arch/arm64/include/asm/kernel-pgtable.h
@@ -107,14 +107,14 @@
 /*
  * Initial memory map attributes.
  */
-#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
-#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
+#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED | PTE_UXN)
+#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S | PTE_UXN)
 
 #ifdef CONFIG_ARM64_4K_PAGES
-#define SWAPPER_RW_MMUFLAGS	(PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS)
+#define SWAPPER_RW_MMUFLAGS	(PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS | PTE_WRITE)
 #define SWAPPER_RX_MMUFLAGS	(SWAPPER_RW_MMUFLAGS | PMD_SECT_RDONLY)
 #else
-#define SWAPPER_RW_MMUFLAGS	(PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS)
+#define SWAPPER_RW_MMUFLAGS	(PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS | PTE_WRITE)
 #define SWAPPER_RX_MMUFLAGS	(SWAPPER_RW_MMUFLAGS | PTE_RDONLY)
 #endif
 
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index e92caebff46a..0f5a30f109d9 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -382,7 +382,7 @@ SYM_FUNC_START_LOCAL(create_idmap)
 	adrp	x0, init_idmap_pg_dir
 	adrp	x3, _text
 	adrp	x6, _end + MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE
-	mov	x7, SWAPPER_RX_MMUFLAGS
+	mov_q	x7, SWAPPER_RX_MMUFLAGS
 
 	map_memory x0, x1, x3, x6, x7, x3, IDMAP_PGD_ORDER, x10, x11, x12, x13, x14, EXTRA_SHIFT
 
@@ -391,7 +391,7 @@ SYM_FUNC_START_LOCAL(create_idmap)
 	adrp	x2, init_pg_dir
 	adrp	x3, init_pg_end
 	bic	x4, x2, #SWAPPER_BLOCK_SIZE - 1
-	mov	x5, SWAPPER_RW_MMUFLAGS
+	mov_q	x5, SWAPPER_RW_MMUFLAGS
 	mov	x6, #SWAPPER_BLOCK_SHIFT
 	bl	remap_region
 
@@ -402,7 +402,7 @@ SYM_FUNC_START_LOCAL(create_idmap)
 	bfi	x22, x21, #0, #SWAPPER_BLOCK_SHIFT		// remapped FDT address
 	add	x3, x2, #MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE
 	bic	x4, x21, #SWAPPER_BLOCK_SIZE - 1
-	mov	x5, SWAPPER_RW_MMUFLAGS
+	mov_q	x5, SWAPPER_RW_MMUFLAGS
 	mov	x6, #SWAPPER_BLOCK_SHIFT
 	bl	remap_region
 
@@ -430,7 +430,7 @@ SYM_FUNC_START_LOCAL(create_kernel_mapping)
 	adrp	x3, _text			// runtime __pa(_text)
 	sub	x6, x6, x3			// _end - _text
 	add	x6, x6, x5			// runtime __va(_end)
-	mov	x7, SWAPPER_RW_MMUFLAGS
+	mov_q	x7, SWAPPER_RW_MMUFLAGS
 
 	map_memory x0, x1, x5, x6, x7, x3, (VA_BITS - PGDIR_SHIFT), x10, x11, x12, x13, x14
 
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index c2cb437821ca..9513a8d2ce0e 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -199,7 +199,7 @@ SYM_FUNC_END(idmap_cpu_replace_ttbr1)
 
 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 
-#define KPTI_NG_PTE_FLAGS	(PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS)
+#define KPTI_NG_PTE_FLAGS	(PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS | PTE_WRITE)
 
 	.pushsection ".idmap.text", "a"
 
@@ -290,7 +290,7 @@ SYM_TYPED_FUNC_START(idmap_kpti_install_ng_mappings)
 	isb
 
 	mov	temp_pte, x5
-	mov	pte_flags, #KPTI_NG_PTE_FLAGS
+	mov_q	pte_flags, KPTI_NG_PTE_FLAGS
 
 	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
 	/* PGD */
-- 
2.25.1


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[PATCH v4 12/20] arm64: add PTE_WRITE to PROT_SECT_NORMAL

[Joey Gouly]

With PIE enabled, PROT_SECT_NORMAL would map onto PAGE_KERNEL_RO.
Add PTE_WRITE so that this maps onto PAGE_KERNEL, so that it is writable.

Without PIE, this should enable DBM for PROT_SECT_NORMAL. However PTE_RDONLY
is already cleared, so the DBM mechanism is not used, and it is always writable,
so this is functionally equivalent.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/include/asm/pgtable-prot.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
index 9b165117a454..d26d0b427c0a 100644
--- a/arch/arm64/include/asm/pgtable-prot.h
+++ b/arch/arm64/include/asm/pgtable-prot.h
@@ -60,7 +60,7 @@ extern bool arm64_use_ng_mappings;
 #define PROT_NORMAL_TAGGED	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))
 
 #define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
-#define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
+#define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PTE_WRITE | PMD_ATTRINDX(MT_NORMAL))
 #define PROT_SECT_NORMAL_EXEC	(PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
 
 #define _PAGE_DEFAULT		(_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
-- 
2.25.1


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[PATCH v4 13/20] arm64: reorganise PAGE_/PROT_ macros

[Joey Gouly]

Make these macros available to assembly code, so they can be re-used by the
PIE initialisation code.

This involves adding some extra macros, prepended with _ that are the raw
values not `pgprot` values.

A dummy value for PTE_MAYBE_NG is also provided, for use in assembly.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/include/asm/pgtable-prot.h | 72 ++++++++++++++++-----------
 1 file changed, 44 insertions(+), 28 deletions(-)

diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
index d26d0b427c0a..a45af0a22b25 100644
--- a/arch/arm64/include/asm/pgtable-prot.h
+++ b/arch/arm64/include/asm/pgtable-prot.h
@@ -27,6 +27,40 @@
  */
 #define PMD_PRESENT_INVALID	(_AT(pteval_t, 1) << 59) /* only when !PMD_SECT_VALID */
 
+#define _PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
+#define _PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
+
+#define PROT_DEFAULT		(_PROT_DEFAULT | PTE_MAYBE_NG)
+#define PROT_SECT_DEFAULT	(_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
+
+#define PROT_DEVICE_nGnRnE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
+#define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
+#define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
+#define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
+#define PROT_NORMAL_TAGGED	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))
+
+#define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
+#define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PTE_WRITE | PMD_ATTRINDX(MT_NORMAL))
+#define PROT_SECT_NORMAL_EXEC	(PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
+
+#define _PAGE_DEFAULT		(_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
+
+#define _PAGE_KERNEL		(PROT_NORMAL)
+#define _PAGE_KERNEL_RO		((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)
+#define _PAGE_KERNEL_ROX	((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY)
+#define _PAGE_KERNEL_EXEC	(PROT_NORMAL & ~PTE_PXN)
+#define _PAGE_KERNEL_EXEC_CONT	((PROT_NORMAL & ~PTE_PXN) | PTE_CONT)
+
+#define _PAGE_SHARED		(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
+#define _PAGE_SHARED_EXEC	(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
+#define _PAGE_READONLY		(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
+#define _PAGE_READONLY_EXEC	(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
+#define _PAGE_EXECONLY		(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
+
+#ifdef __ASSEMBLY__
+#define PTE_MAYBE_NG	0
+#endif
+
 #ifndef __ASSEMBLY__
 
 #include <asm/cpufeature.h>
@@ -34,9 +68,6 @@
 
 extern bool arm64_use_ng_mappings;
 
-#define _PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
-#define _PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
-
 #define PTE_MAYBE_NG		(arm64_use_ng_mappings ? PTE_NG : 0)
 #define PMD_MAYBE_NG		(arm64_use_ng_mappings ? PMD_SECT_NG : 0)
 
@@ -50,26 +81,11 @@ extern bool arm64_use_ng_mappings;
 #define PTE_MAYBE_GP		0
 #endif
 
-#define PROT_DEFAULT		(_PROT_DEFAULT | PTE_MAYBE_NG)
-#define PROT_SECT_DEFAULT	(_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
-
-#define PROT_DEVICE_nGnRnE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
-#define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
-#define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
-#define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
-#define PROT_NORMAL_TAGGED	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))
-
-#define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
-#define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PTE_WRITE | PMD_ATTRINDX(MT_NORMAL))
-#define PROT_SECT_NORMAL_EXEC	(PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
-
-#define _PAGE_DEFAULT		(_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
-
-#define PAGE_KERNEL		__pgprot(PROT_NORMAL)
-#define PAGE_KERNEL_RO		__pgprot((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)
-#define PAGE_KERNEL_ROX		__pgprot((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY)
-#define PAGE_KERNEL_EXEC	__pgprot(PROT_NORMAL & ~PTE_PXN)
-#define PAGE_KERNEL_EXEC_CONT	__pgprot((PROT_NORMAL & ~PTE_PXN) | PTE_CONT)
+#define PAGE_KERNEL		__pgprot(_PAGE_KERNEL)
+#define PAGE_KERNEL_RO		__pgprot(_PAGE_KERNEL_RO)
+#define PAGE_KERNEL_ROX		__pgprot(_PAGE_KERNEL_ROX)
+#define PAGE_KERNEL_EXEC	__pgprot(_PAGE_KERNEL_EXEC)
+#define PAGE_KERNEL_EXEC_CONT	__pgprot(_PAGE_KERNEL_EXEC_CONT)
 
 #define PAGE_S2_MEMATTR(attr, has_fwb)					\
 	({								\
@@ -83,11 +99,11 @@ extern bool arm64_use_ng_mappings;
 
 #define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
 /* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
-#define PAGE_SHARED		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
-#define PAGE_SHARED_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
-#define PAGE_READONLY		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
-#define PAGE_READONLY_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
-#define PAGE_EXECONLY		__pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
+#define PAGE_SHARED		__pgprot(_PAGE_SHARED)
+#define PAGE_SHARED_EXEC	__pgprot(_PAGE_SHARED_EXEC)
+#define PAGE_READONLY		__pgprot(_PAGE_READONLY)
+#define PAGE_READONLY_EXEC	__pgprot(_PAGE_READONLY_EXEC)
+#define PAGE_EXECONLY		__pgprot(_PAGE_EXECONLY)
 
 #endif /* __ASSEMBLY__ */
 
-- 
2.25.1


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[PATCH v4 14/20] arm64: disable EL2 traps for PIE

[Joey Gouly]

Disable trapping of TCR2_EL1 and PIRx_EL1 registers, so they can be
accessed from by EL1.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/include/asm/el2_setup.h | 11 ++++++++++-
 arch/arm64/include/asm/kvm_arm.h   |  4 ++--
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 0201577863ca..e12a7c29aedc 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -159,12 +159,21 @@
 	mov	x0, xzr
 	mrs	x1, id_aa64pfr1_el1
 	ubfx	x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4
-	cbz	x1, .Lset_fgt_\@
+	cbz	x1, .Lset_pie_fgt_\@
 
 	/* Disable nVHE traps of TPIDR2 and SMPRI */
 	orr	x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
 	orr	x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
 
+.Lset_pie_fgt_\@:
+	mrs_s	x1, SYS_ID_AA64MMFR3_EL1
+	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
+	cbz	x1, .Lset_fgt_\@
+
+	/* Disable trapping of PIR_EL1 / PIRE0_EL1 */
+	orr	x0, x0, #HFGxTR_EL2_nPIR_EL1
+	orr	x0, x0, #HFGxTR_EL2_nPIRE0_EL1
+
 .Lset_fgt_\@:
 	msr_s	SYS_HFGRTR_EL2, x0
 	msr_s	SYS_HFGWTR_EL2, x0
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index d2d4f4cd12b8..c6e12e8f2751 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -93,8 +93,8 @@
 #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
 
-#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME)
-#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn)
+#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En)
+#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En)
 
 /* TCR_EL2 Registers bits */
 #define TCR_EL2_RES1		((1U << 31) | (1 << 23))
-- 
2.25.1


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[PATCH v4 15/20] arm64: add encodings of PIRx_ELx registers

[Joey Gouly]

The encodings used in the permission indirection registers means that the
values that Linux puts in the PTEs do not need to be changed.

The E0 values are replicated in E1, with the execute permissions removed.
This is needed as the futex operations access user mappings with privileged
loads/stores.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/include/asm/pgtable-hwdef.h |  8 +++++
 arch/arm64/include/asm/pgtable-prot.h  | 50 ++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index f658aafc47df..e4944d517c99 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -170,6 +170,14 @@
 #define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
 #define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)
 
+/*
+ * PIIndex[3:0] encoding (Permission Indirection Extension)
+ */
+#define PTE_PI_IDX_0	6	/* AP[1], USER */
+#define PTE_PI_IDX_1	51	/* DBM */
+#define PTE_PI_IDX_2	53	/* PXN */
+#define PTE_PI_IDX_3	54	/* UXN */
+
 /*
  * Memory Attribute override for Stage-2 (MemAttr[3:0])
  */
diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
index a45af0a22b25..eed814b00a38 100644
--- a/arch/arm64/include/asm/pgtable-prot.h
+++ b/arch/arm64/include/asm/pgtable-prot.h
@@ -107,4 +107,54 @@ extern bool arm64_use_ng_mappings;
 
 #endif /* __ASSEMBLY__ */
 
+#define pte_pi_index(pte) ( \
+	((pte & BIT(PTE_PI_IDX_3)) >> (PTE_PI_IDX_3 - 3)) | \
+	((pte & BIT(PTE_PI_IDX_2)) >> (PTE_PI_IDX_2 - 2)) | \
+	((pte & BIT(PTE_PI_IDX_1)) >> (PTE_PI_IDX_1 - 1)) | \
+	((pte & BIT(PTE_PI_IDX_0)) >> (PTE_PI_IDX_0 - 0)))
+
+/*
+ * Page types used via Permission Indirection Extension (PIE). PIE uses
+ * the USER, DBM, PXN and UXN bits to to generate an index which is used
+ * to look up the actual permission in PIR_ELx and PIRE0_EL1. We define
+ * combinations we use on non-PIE systems with the same encoding, for
+ * convenience these are listed here as comments as are the unallocated
+ * encodings.
+ */
+
+/* 0: PAGE_DEFAULT                                                  */
+/* 1:                                                      PTE_USER */
+/* 2:                                          PTE_WRITE            */
+/* 3:                                          PTE_WRITE | PTE_USER */
+/* 4: PAGE_EXECONLY                  PTE_PXN                        */
+/* 5: PAGE_READONLY_EXEC             PTE_PXN |             PTE_USER */
+/* 6:                                PTE_PXN | PTE_WRITE            */
+/* 7: PAGE_SHARED_EXEC               PTE_PXN | PTE_WRITE | PTE_USER */
+/* 8: PAGE_KERNEL_ROX      PTE_UXN                                  */
+/* 9:                      PTE_UXN |                       PTE_USER */
+/* a: PAGE_KERNEL_EXEC     PTE_UXN |           PTE_WRITE            */
+/* b:                      PTE_UXN |           PTE_WRITE | PTE_USER */
+/* c: PAGE_KERNEL_RO       PTE_UXN | PTE_PXN                        */
+/* d: PAGE_READONLY        PTE_UXN | PTE_PXN |             PTE_USER */
+/* e: PAGE_KERNEL          PTE_UXN | PTE_PXN | PTE_WRITE            */
+/* f: PAGE_SHARED          PTE_UXN | PTE_PXN | PTE_WRITE | PTE_USER */
+
+#define PIE_E0	( \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_X_O) | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX)  | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RWX) | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)   | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW))
+
+#define PIE_E1	( \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_NONE_O) | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R)      | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RW)     | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)      | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW)     | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_ROX),    PIE_RX)     | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_RO),     PIE_R)      | \
+	PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL),        PIE_RW))
+
 #endif /* __ASM_PGTABLE_PROT_H */
-- 
2.25.1


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[PATCH v4 16/20] arm64: enable Permission Indirection Extension (PIE)

[Joey Gouly]

Now that the necessary changes have been made, set the Permission Indirection
registers and enable the Permission Indirection Extension.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/mm/proc.S | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 9513a8d2ce0e..2baeec419f62 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -454,6 +454,21 @@ SYM_FUNC_START(__cpu_setup)
 #endif	/* CONFIG_ARM64_HW_AFDBM */
 	msr	mair_el1, mair
 	msr	tcr_el1, tcr
+
+	mrs_s	x1, SYS_ID_AA64MMFR3_EL1
+	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
+	cbz	x1, .Lskip_indirection
+
+	mov_q	x0, PIE_E0
+	msr	REG_PIRE0_EL1, x0
+	mov_q	x0, PIE_E1
+	msr	REG_PIR_EL1, x0
+
+	mov	x0, TCR2_EL1x_PIE
+	msr	REG_TCR2_EL1, x0
+
+.Lskip_indirection:
+
 	/*
 	 * Prepare SCTLR
 	 */
-- 
2.25.1


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[PATCH v4 17/20] arm64: transfer permission indirection settings to EL2

[Joey Gouly]

Copy the EL1 registers: TCR2_EL1, PIR_EL1, PIRE0_EL1, such that PIE
is also enabled for EL2.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/kernel/hyp-stub.S | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S
index 9439240c3fcf..d63de1973ddb 100644
--- a/arch/arm64/kernel/hyp-stub.S
+++ b/arch/arm64/kernel/hyp-stub.S
@@ -119,6 +119,24 @@ SYM_CODE_START_LOCAL(__finalise_el2)
 	msr	ttbr1_el1, x0
 	mrs_s	x0, SYS_MAIR_EL12
 	msr	mair_el1, x0
+	mrs	x1, REG_ID_AA64MMFR3_EL1
+	ubfx	x1, x1, #ID_AA64MMFR3_EL1_TCRX_SHIFT, #4
+	cbz	x1, .Lskip_tcr2
+	mrs	x0, REG_TCR2_EL12
+	msr	REG_TCR2_EL1, x0
+
+	// Transfer permission indirection state
+	mrs	x1, REG_ID_AA64MMFR3_EL1
+	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
+	cbz	x1, .Lskip_indirection
+	mrs	x0, REG_PIRE0_EL12
+	msr	REG_PIRE0_EL1, x0
+	mrs	x0, REG_PIR_EL12
+	msr	REG_PIR_EL1, x0
+
+.Lskip_indirection:
+.Lskip_tcr2:
+
 	isb
 
 	// Hack the exception return to stay at EL2
-- 
2.25.1


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[PATCH v4 18/20] arm64: Document boot requirements for PIE

[Joey Gouly]

Features PIE and TCR2 introduce new registers, update the trap requirements
for these features.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 Documentation/arm64/booting.rst | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index b3bbf330ed0a..b57776a68f15 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -385,6 +385,32 @@ Before jumping into the kernel, the following conditions must be met:
 
     - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
 
+  For CPUs with the Extended Translation Control Register feature (FEAT_TCR2):
+
+  - If EL3 is present:
+
+    - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
+
+ - If the kernel is entered at EL1 and EL2 is present:
+
+    - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
+
+  For CPUs with the Stage 1 Permission Indirection Extension feature (FEAT_S1PIE):
+
+  - If EL3 is present:
+
+    - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
+
+  - If the kernel is entered at EL1 and EL2 is present:
+
+    - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
+
+    - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
+
+    - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
+
+    - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
+
 The requirements described above for CPU mode, caches, MMUs, architected
 timers, coherency and system registers apply to all CPUs.  All CPUs must
 enter the kernel in the same exception level.  Where the values documented
-- 
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[PATCH v4 19/20] KVM: selftests: get-reg-list: support ID register features

[Joey Gouly]

This stops the test complaining about missing registers, when running
on an older kernel that does not support newer features.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: Mark Brown <broonie@kernel.org>
Cc: Shuah Khan <shuah@kernel.org>
---
 .../selftests/kvm/aarch64/get-reg-list.c      | 32 ++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
index d4e1f4af29d6..3ab236ceb6fc 100644
--- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c
+++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
@@ -48,6 +48,16 @@ struct reg_sublist {
 	__u64 rejects_set_n;
 };
 
+struct feature_id_reg {
+	__u64 reg;
+	__u64 id_reg;
+	__u64 feat_shift;
+	__u64 feat_min;
+};
+
+static struct feature_id_reg feat_id_regs[] = {
+};
+
 struct vcpu_config {
 	char *name;
 	struct reg_sublist sublists[];
@@ -68,7 +78,8 @@ static int vcpu_configs_n;
 
 #define for_each_missing_reg(i)							\
 	for ((i) = 0; (i) < blessed_n; ++(i))					\
-		if (!find_reg(reg_list->reg, reg_list->n, blessed_reg[i]))
+		if (!find_reg(reg_list->reg, reg_list->n, blessed_reg[i]))	\
+			if (check_supported_feat_reg(vcpu, blessed_reg[i]))
 
 #define for_each_new_reg(i)							\
 	for_each_reg_filtered(i)						\
@@ -132,6 +143,25 @@ static bool find_reg(__u64 regs[], __u64 nr_regs, __u64 reg)
 	return false;
 }
 
+static bool check_supported_feat_reg(struct kvm_vcpu *vcpu, __u64 reg)
+{
+	int i, ret;
+	__u64 data, feat_val;
+
+	for (i = 0; i < ARRAY_SIZE(feat_id_regs); i++) {
+		if (feat_id_regs[i].reg == reg) {
+			ret = __vcpu_get_reg(vcpu, feat_id_regs[i].id_reg, &data);
+			if (ret < 0)
+				return false;
+
+			feat_val = ((data >> feat_id_regs[i].feat_shift) & 0xf);
+			return feat_val >= feat_id_regs[i].feat_min;
+		}
+	}
+
+	return true;
+}
+
 static const char *str_with_index(const char *template, __u64 index)
 {
 	char *str, *p;
-- 
2.25.1


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[PATCH v4 20/20] KVM: selftests: get-reg-list: add Permission Indirection registers

[Joey Gouly]

Add new system registers:
  - ID_AA64MMFR3_EL1
  - TCR2_EL1
  - PIRE0_EL1
  - PIR_EL1

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: Mark Brown <broonie@kernel.org>
Cc: Shuah Khan <shuah@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
---
 .../selftests/kvm/aarch64/get-reg-list.c      | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
index 3ab236ceb6fc..4f10055af2aa 100644
--- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c
+++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
@@ -56,6 +56,24 @@ struct feature_id_reg {
 };
 
 static struct feature_id_reg feat_id_regs[] = {
+	{
+		ARM64_SYS_REG(3, 0, 2, 0, 3),	/* TCR2_EL1 */
+		ARM64_SYS_REG(3, 0, 0, 7, 3),	/* ID_AA64MMFR3_EL1 */
+		0,
+		1
+	},
+	{
+		ARM64_SYS_REG(3, 0, 10, 2, 2),	/* PIRE0_EL1 */
+		ARM64_SYS_REG(3, 0, 0, 7, 3),	/* ID_AA64MMFR3_EL1 */
+		4,
+		1
+	},
+	{
+		ARM64_SYS_REG(3, 0, 10, 2, 3),	/* PIR_EL1 */
+		ARM64_SYS_REG(3, 0, 0, 7, 3),	/* ID_AA64MMFR3_EL1 */
+		4,
+		1
+	}
 };
 
 struct vcpu_config {
@@ -873,12 +891,15 @@ static __u64 base_regs[] = {
 	ARM64_SYS_REG(3, 0, 2, 0, 0),	/* TTBR0_EL1 */
 	ARM64_SYS_REG(3, 0, 2, 0, 1),	/* TTBR1_EL1 */
 	ARM64_SYS_REG(3, 0, 2, 0, 2),	/* TCR_EL1 */
+	ARM64_SYS_REG(3, 0, 2, 0, 3),	/* TCR2_EL1 */
 	ARM64_SYS_REG(3, 0, 5, 1, 0),	/* AFSR0_EL1 */
 	ARM64_SYS_REG(3, 0, 5, 1, 1),	/* AFSR1_EL1 */
 	ARM64_SYS_REG(3, 0, 5, 2, 0),	/* ESR_EL1 */
 	ARM64_SYS_REG(3, 0, 6, 0, 0),	/* FAR_EL1 */
 	ARM64_SYS_REG(3, 0, 7, 4, 0),	/* PAR_EL1 */
 	ARM64_SYS_REG(3, 0, 10, 2, 0),	/* MAIR_EL1 */
+	ARM64_SYS_REG(3, 0, 10, 2, 2),	/* PIRE0_EL1 */
+	ARM64_SYS_REG(3, 0, 10, 2, 3),	/* PIR_EL1 */
 	ARM64_SYS_REG(3, 0, 10, 3, 0),	/* AMAIR_EL1 */
 	ARM64_SYS_REG(3, 0, 12, 0, 0),	/* VBAR_EL1 */
 	ARM64_SYS_REG(3, 0, 12, 1, 1),	/* DISR_EL1 */
-- 
2.25.1


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Re: [PATCH v4 00/20] Permission Indirection Extension

[Catalin Marinas]

On Tue, 06 Jun 2023 15:58:39 +0100, Joey Gouly wrote:
> This series implements the Permission Indirection Extension introduced in 2022
> VMSA enhancements [1].
> 
> Changes since v3 [2]:
> 	- Rebased onto for-next/feat_mops
> 	- Enabled TCR2 in new HCRX_HOST_FLAGS/HCRX_GUEST_FLAGS
> 	- Use ARM64_CPUID_FIELDS in cpufeature.c
> 	- Add Marc Z's R-b tags
> 
> [...]

Applied to arm64 (for-next/feat_s1pie), thanks!

[01/20] arm64/sysreg: Add ID register ID_AA64MMFR3
        https://git.kernel.org/arm64/c/00ac84677d87
[02/20] arm64/sysreg: add system registers TCR2_ELx
        https://git.kernel.org/arm64/c/89b6c3ee4988
[03/20] arm64/sysreg: update HCRX_EL2 register
        https://git.kernel.org/arm64/c/25bc6f32cd71
[04/20] arm64/sysreg: add PIR*_ELx registers
        https://git.kernel.org/arm64/c/c36ad1943f94
[05/20] arm64: cpufeature: add system register ID_AA64MMFR3
        https://git.kernel.org/arm64/c/edc25898f0b6
[06/20] arm64: cpufeature: add TCR2 cpucap
        https://git.kernel.org/arm64/c/2b760046a2d3
[07/20] arm64: cpufeature: add Permission Indirection Extension cpucap
        https://git.kernel.org/arm64/c/e43454c44232
[08/20] KVM: arm64: Save/restore TCR2_EL1
        https://git.kernel.org/arm64/c/fbff56068232
[09/20] KVM: arm64: Save/restore PIE registers
        https://git.kernel.org/arm64/c/86f9de9db178
[10/20] KVM: arm64: expose ID_AA64MMFR3_EL1 to guests
        https://git.kernel.org/arm64/c/8ef67c67e637
[11/20] arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS
        https://git.kernel.org/arm64/c/f0af339fc408
[12/20] arm64: add PTE_WRITE to PROT_SECT_NORMAL
        https://git.kernel.org/arm64/c/7c302cfbee1f
[13/20] arm64: reorganise PAGE_/PROT_ macros
        https://git.kernel.org/arm64/c/fa4cdccaa582
[14/20] arm64: disable EL2 traps for PIE
        https://git.kernel.org/arm64/c/7df7170965a2
[15/20] arm64: add encodings of PIRx_ELx registers
        https://git.kernel.org/arm64/c/eeda243dfeb9
[16/20] arm64: enable Permission Indirection Extension (PIE)
        https://git.kernel.org/arm64/c/9e9bb6ede00a
[17/20] arm64: transfer permission indirection settings to EL2
        https://git.kernel.org/arm64/c/6b776d385562
[18/20] arm64: Document boot requirements for PIE
        https://git.kernel.org/arm64/c/6c792b7d3c2c
[19/20] KVM: selftests: get-reg-list: support ID register features
        https://git.kernel.org/arm64/c/ee053e03b08e
[20/20] KVM: selftests: get-reg-list: add Permission Indirection registers
        https://git.kernel.org/arm64/c/5f0419a0083b

-- 
Catalin


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Re: [PATCH v4 16/20] arm64: enable Permission Indirection Extension (PIE)

[Neil Armstrong]

Hi Joey,

On 06/06/2023 16:58, Joey Gouly wrote:
> Now that the necessary changes have been made, set the Permission Indirection
> registers and enable the Permission Indirection Extension.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

This patch on linux-next causes a great amount of:

X     xxx.xxxxxx Emulated RAZ for ID register: ISS 0x36002f

messages printed by the system firmware on the Qualcomm SM8550 SoC,
and the platform is barely usable.

Here is the SoC cpuinfo for reference:
# cat /proc/cpuinfo
processor	: 0
BogoMIPS	: 38.40
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x1
CPU part	: 0xd46
CPU revision	: 1

processor	: 1
BogoMIPS	: 38.40
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x1
CPU part	: 0xd46
CPU revision	: 1

processor	: 2
BogoMIPS	: 38.40
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x1
CPU part	: 0xd46
CPU revision	: 1

processor	: 3
BogoMIPS	: 38.40
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x1
CPU part	: 0xd4d
CPU revision	: 0

processor	: 4
BogoMIPS	: 38.40
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x1
CPU part	: 0xd4d
CPU revision	: 0

processor	: 5
BogoMIPS	: 38.40
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x2
CPU part	: 0xd47
CPU revision	: 0

processor	: 6
BogoMIPS	: 38.40
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x2
CPU part	: 0xd47
CPU revision	: 0

processor	: 7
BogoMIPS	: 38.40
Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x1
CPU part	: 0xd4e
CPU revision	: 0

The bisect log for reference:
# bad: [925294c9aa184801cc0a451b69a18dd0fe7d847d] Add linux-next specific files for 20230615
# good: [858fd168a95c5b9669aac8db6c14a9aeab446375] Linux 6.4-rc6
git bisect start 'FETCH_HEAD' 'v6.4-rc6'
# bad: [c20f7e5e521ee3f50b064cdb441f65075ca6eb17] Merge branch 'nand/next' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git
git bisect bad c20f7e5e521ee3f50b064cdb441f65075ca6eb17
# bad: [9b3c3144b2d3b5022370883e2834887fc7f3d5d3] Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git
git bisect bad 9b3c3144b2d3b5022370883e2834887fc7f3d5d3
# bad: [8a2e6adeea094195f860f1f5dd799c9f0015dd92] Merge branch 'at91-next' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git
git bisect bad 8a2e6adeea094195f860f1f5dd799c9f0015dd92
# good: [4f826d17f9de4d708f2c07bb40a104426a22b384] Merge branch 'mm-everything' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
git bisect good 4f826d17f9de4d708f2c07bb40a104426a22b384
# good: [62f97a067a7e77fd2016ce7d413fceaaf5882385] Merge branch 'for-next' of git://git.infradead.org/users/hch/dma-mapping.git
git bisect good 62f97a067a7e77fd2016ce7d413fceaaf5882385
# good: [e5047345bb6c8ee1e5d319c989dc9e3442f891c7] soc: document merges
git bisect good e5047345bb6c8ee1e5d319c989dc9e3442f891c7
# good: [cca5c2136d9ca679a9b0cdb51ce64c79cd7c092c] Merge branches 'for-next/kpti', 'for-next/missing-proto-warn', 'for-next/iss2-decode', 'for-next/kselftest', 'for-next/misc', 'for-next/feat_mops', 'for-next/module-alloc', 'for-next/sysreg', 'for-next/cpucap', 'for-next/acpi', 'for-next/kdump' and 'for-next/acpi-doc' into for-next/core
git bisect good cca5c2136d9ca679a9b0cdb51ce64c79cd7c092c
# bad: [b6719d317df3ab47dc86776c499fc1e2009e1b37] Merge branch 'for-next/core' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
git bisect bad b6719d317df3ab47dc86776c499fc1e2009e1b37
# bad: [ee053e03b08e1b287d9a43152e4623a04cb24fe6] KVM: selftests: get-reg-list: support ID register features
git bisect bad ee053e03b08e1b287d9a43152e4623a04cb24fe6
# good: [86f9de9db1783b32e8812fe21c2c8cf02cf911ff] KVM: arm64: Save/restore PIE registers
git bisect good 86f9de9db1783b32e8812fe21c2c8cf02cf911ff
# good: [7df7170965a28c61f80a57b655b0cc10adb88ab9] arm64: disable EL2 traps for PIE
git bisect good 7df7170965a28c61f80a57b655b0cc10adb88ab9
# bad: [9e9bb6ede00a84275b65bb8d00812c1e24b5fa7e] arm64: enable Permission Indirection Extension (PIE)
git bisect bad 9e9bb6ede00a84275b65bb8d00812c1e24b5fa7e
# good: [eeda243dfeb996fe236c624796630c16237a18d6] arm64: add encodings of PIRx_ELx registers
git bisect good eeda243dfeb996fe236c624796630c16237a18d6
# first bad commit: [9e9bb6ede00a84275b65bb8d00812c1e24b5fa7e] arm64: enable Permission Indirection Extension (PIE)

Thanks,
Neil

> ---
>   arch/arm64/mm/proc.S | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index 9513a8d2ce0e..2baeec419f62 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -454,6 +454,21 @@ SYM_FUNC_START(__cpu_setup)
>   #endif	/* CONFIG_ARM64_HW_AFDBM */
>   	msr	mair_el1, mair
>   	msr	tcr_el1, tcr
> +
> +	mrs_s	x1, SYS_ID_AA64MMFR3_EL1
> +	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
> +	cbz	x1, .Lskip_indirection
> +
> +	mov_q	x0, PIE_E0
> +	msr	REG_PIRE0_EL1, x0
> +	mov_q	x0, PIE_E1
> +	msr	REG_PIR_EL1, x0
> +
> +	mov	x0, TCR2_EL1x_PIE
> +	msr	REG_TCR2_EL1, x0
> +
> +.Lskip_indirection:
> +
>   	/*
>   	 * Prepare SCTLR
>   	 */


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Re: [PATCH v4 16/20] arm64: enable Permission Indirection Extension (PIE)

[Joey Gouly]

Hi Neil,

On Tue, Jun 20, 2023 at 09:16:05PM +0200, Neil Armstrong wrote:
> Hi Joey,
> 
> On 06/06/2023 16:58, Joey Gouly wrote:
> > Now that the necessary changes have been made, set the Permission Indirection
> > registers and enable the Permission Indirection Extension.
> > 
> > Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will@kernel.org>
> > Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> 
> This patch on linux-next causes a great amount of:
> 
> X     xxx.xxxxxx Emulated RAZ for ID register: ISS 0x36002f
> 
> messages printed by the system firmware on the Qualcomm SM8550 SoC,
> and the platform is barely usable.


Not sure what's going on here, and I don't think I have access to that platform.
The new registers are only set a few times, so not sure why it would be RAZ emulating
them a lot. KVM context switches them, but I don't think that platform uses KVM.

Could you try to bisect the actual lines? It would be intersting to know which of the
registers that it's actually causing an issue. It should be taking the .skip_indirection
branch, so only ID_AA64MMFR3_EL1 should be accessed, but it would be good to confirm that
if you can somehow.

Thanks,
Joey
 
> 
> Here is the SoC cpuinfo for reference:
> # cat /proc/cpuinfo
> processor	: 0
> BogoMIPS	: 38.40
> Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
> CPU implementer	: 0x41
> CPU architecture: 8
> CPU variant	: 0x1
> CPU part	: 0xd46
> CPU revision	: 1
> 
> processor	: 1
> BogoMIPS	: 38.40
> Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
> CPU implementer	: 0x41
> CPU architecture: 8
> CPU variant	: 0x1
> CPU part	: 0xd46
> CPU revision	: 1
> 
> processor	: 2
> BogoMIPS	: 38.40
> Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
> CPU implementer	: 0x41
> CPU architecture: 8
> CPU variant	: 0x1
> CPU part	: 0xd46
> CPU revision	: 1
> 
> processor	: 3
> BogoMIPS	: 38.40
> Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
> CPU implementer	: 0x41
> CPU architecture: 8
> CPU variant	: 0x1
> CPU part	: 0xd4d
> CPU revision	: 0
> 
> processor	: 4
> BogoMIPS	: 38.40
> Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
> CPU implementer	: 0x41
> CPU architecture: 8
> CPU variant	: 0x1
> CPU part	: 0xd4d
> CPU revision	: 0
> 
> processor	: 5
> BogoMIPS	: 38.40
> Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
> CPU implementer	: 0x41
> CPU architecture: 8
> CPU variant	: 0x2
> CPU part	: 0xd47
> CPU revision	: 0
> 
> processor	: 6
> BogoMIPS	: 38.40
> Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
> CPU implementer	: 0x41
> CPU architecture: 8
> CPU variant	: 0x2
> CPU part	: 0xd47
> CPU revision	: 0
> 
> processor	: 7
> BogoMIPS	: 38.40
> Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bti
> CPU implementer	: 0x41
> CPU architecture: 8
> CPU variant	: 0x1
> CPU part	: 0xd4e
> CPU revision	: 0
> 
> The bisect log for reference:
> # bad: [925294c9aa184801cc0a451b69a18dd0fe7d847d] Add linux-next specific files for 20230615
> # good: [858fd168a95c5b9669aac8db6c14a9aeab446375] Linux 6.4-rc6
> git bisect start 'FETCH_HEAD' 'v6.4-rc6'
> # bad: [c20f7e5e521ee3f50b064cdb441f65075ca6eb17] Merge branch 'nand/next' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git
> git bisect bad c20f7e5e521ee3f50b064cdb441f65075ca6eb17
> # bad: [9b3c3144b2d3b5022370883e2834887fc7f3d5d3] Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git
> git bisect bad 9b3c3144b2d3b5022370883e2834887fc7f3d5d3
> # bad: [8a2e6adeea094195f860f1f5dd799c9f0015dd92] Merge branch 'at91-next' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git
> git bisect bad 8a2e6adeea094195f860f1f5dd799c9f0015dd92
> # good: [4f826d17f9de4d708f2c07bb40a104426a22b384] Merge branch 'mm-everything' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
> git bisect good 4f826d17f9de4d708f2c07bb40a104426a22b384
> # good: [62f97a067a7e77fd2016ce7d413fceaaf5882385] Merge branch 'for-next' of git://git.infradead.org/users/hch/dma-mapping.git
> git bisect good 62f97a067a7e77fd2016ce7d413fceaaf5882385
> # good: [e5047345bb6c8ee1e5d319c989dc9e3442f891c7] soc: document merges
> git bisect good e5047345bb6c8ee1e5d319c989dc9e3442f891c7
> # good: [cca5c2136d9ca679a9b0cdb51ce64c79cd7c092c] Merge branches 'for-next/kpti', 'for-next/missing-proto-warn', 'for-next/iss2-decode', 'for-next/kselftest', 'for-next/misc', 'for-next/feat_mops', 'for-next/module-alloc', 'for-next/sysreg', 'for-next/cpucap', 'for-next/acpi', 'for-next/kdump' and 'for-next/acpi-doc' into for-next/core
> git bisect good cca5c2136d9ca679a9b0cdb51ce64c79cd7c092c
> # bad: [b6719d317df3ab47dc86776c499fc1e2009e1b37] Merge branch 'for-next/core' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
> git bisect bad b6719d317df3ab47dc86776c499fc1e2009e1b37
> # bad: [ee053e03b08e1b287d9a43152e4623a04cb24fe6] KVM: selftests: get-reg-list: support ID register features
> git bisect bad ee053e03b08e1b287d9a43152e4623a04cb24fe6
> # good: [86f9de9db1783b32e8812fe21c2c8cf02cf911ff] KVM: arm64: Save/restore PIE registers
> git bisect good 86f9de9db1783b32e8812fe21c2c8cf02cf911ff
> # good: [7df7170965a28c61f80a57b655b0cc10adb88ab9] arm64: disable EL2 traps for PIE
> git bisect good 7df7170965a28c61f80a57b655b0cc10adb88ab9
> # bad: [9e9bb6ede00a84275b65bb8d00812c1e24b5fa7e] arm64: enable Permission Indirection Extension (PIE)
> git bisect bad 9e9bb6ede00a84275b65bb8d00812c1e24b5fa7e
> # good: [eeda243dfeb996fe236c624796630c16237a18d6] arm64: add encodings of PIRx_ELx registers
> git bisect good eeda243dfeb996fe236c624796630c16237a18d6
> # first bad commit: [9e9bb6ede00a84275b65bb8d00812c1e24b5fa7e] arm64: enable Permission Indirection Extension (PIE)
> 
> Thanks,
> Neil
> 
> > ---
> >   arch/arm64/mm/proc.S | 15 +++++++++++++++
> >   1 file changed, 15 insertions(+)
> > 
> > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> > index 9513a8d2ce0e..2baeec419f62 100644
> > --- a/arch/arm64/mm/proc.S
> > +++ b/arch/arm64/mm/proc.S
> > @@ -454,6 +454,21 @@ SYM_FUNC_START(__cpu_setup)
> >   #endif	/* CONFIG_ARM64_HW_AFDBM */
> >   	msr	mair_el1, mair
> >   	msr	tcr_el1, tcr
> > +
> > +	mrs_s	x1, SYS_ID_AA64MMFR3_EL1
> > +	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
> > +	cbz	x1, .Lskip_indirection
> > +
> > +	mov_q	x0, PIE_E0
> > +	msr	REG_PIRE0_EL1, x0
> > +	mov_q	x0, PIE_E1
> > +	msr	REG_PIR_EL1, x0
> > +
> > +	mov	x0, TCR2_EL1x_PIE
> > +	msr	REG_TCR2_EL1, x0
> > +
> > +.Lskip_indirection:
> > +
> >   	/*
> >   	 * Prepare SCTLR
> >   	 */

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Re: [PATCH v4 16/20] arm64: enable Permission Indirection Extension (PIE)

[Mark Brown]

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On Tue, Jun 20, 2023 at 09:16:05PM +0200, Neil Armstrong wrote:

> This patch on linux-next causes a great amount of:

> X     xxx.xxxxxx Emulated RAZ for ID register: ISS 0x36002f

> messages printed by the system firmware on the Qualcomm SM8550 SoC,
> and the platform is barely usable.

Regardless of what the kernel is doing it looks like there's a firmware
issue here, all otherwise undefined registers in the ID space should be
RAZ so spamming the logs like this isn't great.

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Re: [PATCH v4 16/20] arm64: enable Permission Indirection Extension (PIE)

[Marc Zyngier]

On 2023-06-20 20:16, Neil Armstrong wrote:
> Hi Joey,
> 
> On 06/06/2023 16:58, Joey Gouly wrote:
>> Now that the necessary changes have been made, set the Permission 
>> Indirection
>> registers and enable the Permission Indirection Extension.
>> 
>> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> 
> This patch on linux-next causes a great amount of:
> 
> X     xxx.xxxxxx Emulated RAZ for ID register: ISS 0x36002f
> 
> messages printed by the system firmware on the Qualcomm SM8550 SoC,
> and the platform is barely usable.

As others have said on this thread, this is a firmware bug.
Not a lot we can do about that, unfortunately, apart from hiding
the new feature behind a config option that you'd disable on this
platform.

Alternatively, disabling idle management on this machine should
reduce the screaming greatly.

         M.
-- 
Jazz is not dead. It just smells funny...

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Re: [PATCH v4 16/20] arm64: enable Permission Indirection Extension (PIE)

[Oliver Upton]

On Tue, Jun 20, 2023 at 09:27:18PM +0100, Mark Brown wrote:
> On Tue, Jun 20, 2023 at 09:16:05PM +0200, Neil Armstrong wrote:
> 
> > This patch on linux-next causes a great amount of:
> 
> > X     xxx.xxxxxx Emulated RAZ for ID register: ISS 0x36002f
> 
> > messages printed by the system firmware on the Qualcomm SM8550 SoC,
> > and the platform is barely usable.
> 
> Regardless of what the kernel is doing it looks like there's a firmware
> issue here, all otherwise undefined registers in the ID space should be
> RAZ so spamming the logs like this isn't great.

Agreed. This isn't a kernel issue... We already do 2 ID register reads
in __cpu_setup(), so can't really blame this change for adding a third.

This stinks of Gunyah:

https://github.com/quic/gunyah-hypervisor/blob/3d4014404993939f898018cfb1935c2d9bfc2830/hyp/vm/vcpu/aarch64/src/sysreg_traps.c#L1177

-- 
Thanks,
Oliver

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Re: [PATCH v4 16/20] arm64: enable Permission Indirection Extension (PIE)

[Trilok Soni]

On 6/20/2023 1:35 PM, Marc Zyngier wrote:
> On 2023-06-20 20:16, Neil Armstrong wrote:
>> Hi Joey,
>>
>> On 06/06/2023 16:58, Joey Gouly wrote:
>>> Now that the necessary changes have been made, set the Permission 
>>> Indirection
>>> registers and enable the Permission Indirection Extension.
>>>
>>> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>> Cc: Will Deacon <will@kernel.org>
>>> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
>>
>> This patch on linux-next causes a great amount of:
>>
>> X     xxx.xxxxxx Emulated RAZ for ID register: ISS 0x36002f
>>
>> messages printed by the system firmware on the Qualcomm SM8550 SoC,
>> and the platform is barely usable.
> 
> As others have said on this thread, this is a firmware bug.
> Not a lot we can do about that, unfortunately, apart from hiding
> the new feature behind a config option that you'd disable on this
> platform.
> 
> Alternatively, disabling idle management on this machine should
> reduce the screaming greatly.

I have informed Carl about the Gunyah messaging, I have also added him 
into this thread.

---Trilok Soni

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Re: [PATCH v4 20/20] KVM: selftests: get-reg-list: add Permission Indirection registers

[Andrew Jones]

> Add new system registers:
>   - ID_AA64MMFR3_EL1
>   - TCR2_EL1
>   - PIRE0_EL1
>   - PIR_EL1
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oliver.upton@linux.dev>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: Shuah Khan <shuah@kernel.org>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
>  .../selftests/kvm/aarch64/get-reg-list.c      | 21 +++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
> index 3ab236ceb6fc..4f10055af2aa 100644
> --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
> @@ -56,6 +56,24 @@ struct feature_id_reg {
>  };
>  
>  static struct feature_id_reg feat_id_regs[] = {
> +	{
> +		ARM64_SYS_REG(3, 0, 2, 0, 3),	/* TCR2_EL1 */
> +		ARM64_SYS_REG(3, 0, 0, 7, 3),	/* ID_AA64MMFR3_EL1 */
> +		0,
> +		1
> +	},
> +	{
> +		ARM64_SYS_REG(3, 0, 10, 2, 2),	/* PIRE0_EL1 */
> +		ARM64_SYS_REG(3, 0, 0, 7, 3),	/* ID_AA64MMFR3_EL1 */
> +		4,
> +		1
> +	},
> +	{
> +		ARM64_SYS_REG(3, 0, 10, 2, 3),	/* PIR_EL1 */
> +		ARM64_SYS_REG(3, 0, 0, 7, 3),	/* ID_AA64MMFR3_EL1 */
> +		4,
> +		1
> +	}
>  };
>  
>  struct vcpu_config {
> @@ -873,12 +891,15 @@ static __u64 base_regs[] = {
>  	ARM64_SYS_REG(3, 0, 2, 0, 0),	/* TTBR0_EL1 */
>  	ARM64_SYS_REG(3, 0, 2, 0, 1),	/* TTBR1_EL1 */
>  	ARM64_SYS_REG(3, 0, 2, 0, 2),	/* TCR_EL1 */
> +	ARM64_SYS_REG(3, 0, 2, 0, 3),	/* TCR2_EL1 */
>  	ARM64_SYS_REG(3, 0, 5, 1, 0),	/* AFSR0_EL1 */
>  	ARM64_SYS_REG(3, 0, 5, 1, 1),	/* AFSR1_EL1 */
>  	ARM64_SYS_REG(3, 0, 5, 2, 0),	/* ESR_EL1 */
>  	ARM64_SYS_REG(3, 0, 6, 0, 0),	/* FAR_EL1 */
>  	ARM64_SYS_REG(3, 0, 7, 4, 0),	/* PAR_EL1 */
>  	ARM64_SYS_REG(3, 0, 10, 2, 0),	/* MAIR_EL1 */
> +	ARM64_SYS_REG(3, 0, 10, 2, 2),	/* PIRE0_EL1 */
> +	ARM64_SYS_REG(3, 0, 10, 2, 3),	/* PIR_EL1 */

Hi Joey,

Any reason these registers needed to be added to the base reg set? Usually
new registers get added to their own sublist, which then get tested by
their own subtest. That way the subtest can SKIP when the new registers
aren't present. That approach should avoid the need for modifying
for_each_missing_reg() (well, after changing the call of check_supported()
to be after configuring the vcpu, in order to pass the vcpu to it, and
after extending check_supported() to call check_supported_feat_reg()).

Thanks,
drew

>  	ARM64_SYS_REG(3, 0, 10, 3, 0),	/* AMAIR_EL1 */
>  	ARM64_SYS_REG(3, 0, 12, 0, 0),	/* VBAR_EL1 */
>  	ARM64_SYS_REG(3, 0, 12, 1, 1),	/* DISR_EL1 */
> -- 
> 2.25.1
> 

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Re: [PATCH v4 20/20] KVM: selftests: get-reg-list: add Permission Indirection registers

[Joey Gouly]

Hi,

On Mon, Jul 03, 2023 at 02:03:45PM +0200, Andrew Jones wrote:
> > Add new system registers:
> >   - ID_AA64MMFR3_EL1
> >   - TCR2_EL1
> >   - PIRE0_EL1
> >   - PIR_EL1
> > 
> > Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> > Cc: Marc Zyngier <maz@kernel.org>
> > Cc: Oliver Upton <oliver.upton@linux.dev>
> > Cc: Mark Brown <broonie@kernel.org>
> > Cc: Shuah Khan <shuah@kernel.org>
> > Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> > ---
> >  .../selftests/kvm/aarch64/get-reg-list.c      | 21 +++++++++++++++++++
> >  1 file changed, 21 insertions(+)
> > 
> > diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
> > index 3ab236ceb6fc..4f10055af2aa 100644
> > --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c
> > +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c
> > @@ -56,6 +56,24 @@ struct feature_id_reg {
> >  };
> >  
> >  static struct feature_id_reg feat_id_regs[] = {
> > +	{
> > +		ARM64_SYS_REG(3, 0, 2, 0, 3),	/* TCR2_EL1 */
> > +		ARM64_SYS_REG(3, 0, 0, 7, 3),	/* ID_AA64MMFR3_EL1 */
> > +		0,
> > +		1
> > +	},
> > +	{
> > +		ARM64_SYS_REG(3, 0, 10, 2, 2),	/* PIRE0_EL1 */
> > +		ARM64_SYS_REG(3, 0, 0, 7, 3),	/* ID_AA64MMFR3_EL1 */
> > +		4,
> > +		1
> > +	},
> > +	{
> > +		ARM64_SYS_REG(3, 0, 10, 2, 3),	/* PIR_EL1 */
> > +		ARM64_SYS_REG(3, 0, 0, 7, 3),	/* ID_AA64MMFR3_EL1 */
> > +		4,
> > +		1
> > +	}
> >  };
> >  
> >  struct vcpu_config {
> > @@ -873,12 +891,15 @@ static __u64 base_regs[] = {
> >  	ARM64_SYS_REG(3, 0, 2, 0, 0),	/* TTBR0_EL1 */
> >  	ARM64_SYS_REG(3, 0, 2, 0, 1),	/* TTBR1_EL1 */
> >  	ARM64_SYS_REG(3, 0, 2, 0, 2),	/* TCR_EL1 */
> > +	ARM64_SYS_REG(3, 0, 2, 0, 3),	/* TCR2_EL1 */
> >  	ARM64_SYS_REG(3, 0, 5, 1, 0),	/* AFSR0_EL1 */
> >  	ARM64_SYS_REG(3, 0, 5, 1, 1),	/* AFSR1_EL1 */
> >  	ARM64_SYS_REG(3, 0, 5, 2, 0),	/* ESR_EL1 */
> >  	ARM64_SYS_REG(3, 0, 6, 0, 0),	/* FAR_EL1 */
> >  	ARM64_SYS_REG(3, 0, 7, 4, 0),	/* PAR_EL1 */
> >  	ARM64_SYS_REG(3, 0, 10, 2, 0),	/* MAIR_EL1 */
> > +	ARM64_SYS_REG(3, 0, 10, 2, 2),	/* PIRE0_EL1 */
> > +	ARM64_SYS_REG(3, 0, 10, 2, 3),	/* PIR_EL1 */
> 
> Hi Joey,
> 
> Any reason these registers needed to be added to the base reg set? Usually
> new registers get added to their own sublist, which then get tested by
> their own subtest.

I added them to the base set because there is no feature/capability to enable PIE [1] (unlike SVE, PMU etc)
That means they have to be part of the base set, otherwise the test will complain about missing regs.

Thanks,
Joey

[1] https://lore.kernel.org/linux-arm-kernel/86y1o5yjs7.wl-maz@kernel.org/

> That way the subtest can SKIP when the new registers
> aren't present. That approach should avoid the need for modifying
> for_each_missing_reg() (well, after changing the call of check_supported()
> to be after configuring the vcpu, in order to pass the vcpu to it, and
> after extending check_supported() to call check_supported_feat_reg()).
> 
> Thanks,
> drew
> 
> >  	ARM64_SYS_REG(3, 0, 10, 3, 0),	/* AMAIR_EL1 */
> >  	ARM64_SYS_REG(3, 0, 12, 0, 0),	/* VBAR_EL1 */
> >  	ARM64_SYS_REG(3, 0, 12, 1, 1),	/* DISR_EL1 */

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Re: [PATCH v4 20/20] KVM: selftests: get-reg-list: add Permission Indirection registers

[Andrew Jones]

On Wed, Jul 12, 2023 at 03:59:17PM +0100, Joey Gouly wrote:
> On Mon, Jul 03, 2023 at 02:03:45PM +0200, Andrew Jones wrote:
...
> > Any reason these registers needed to be added to the base reg set? Usually
> > new registers get added to their own sublist, which then get tested by
> > their own subtest.
> 
> I added them to the base set because there is no feature/capability to enable PIE [1] (unlike SVE, PMU etc)
> That means they have to be part of the base set, otherwise the test will complain about missing regs.
>

Hi Joey,

Without the registers in a blessed list, then I wouldn't expect them to be
reported as 'missing', but rather as 'new' (and only when running on a
platform that supports them and with a recent enough KVM to have them
exposed). There are two ways to approach registers like these:

 1) the way this patch has done it, i.e. add the registers to the "base"
    list so they'll be expected by all subtests, ensuring they'll never
    appear as 'new', but then also avoid false-positive 'missing' failures
    by filtering them out of the missing list when necessary.

 2) add the registers to subtests which only run when the registers
    should be present (skipping the tests when not) and then always filter
    the registers out of the 'new' list. (It's always safe to filter
    explicitly defined registers out of the new list since "new" means new
    to the selftest, but the selftest must be aware of those registers in
    order to explicitly filter them, which means they can't be new :-)

To me, (2) is the cleaner approach, particularly because we've had subtest
skipping support and 'new' register filtering support from nearly the
beginning. riscv also has some nonconfigurable registers which are only
present when the platform supports them. The riscv get-one-reg series[1]
has taken approach (2) to handle those.

At some point maybe we can consider converting the permission indirection
registers to approach (2), but it's not critical to do anytime soon. So,
for now, we'll rebase the riscv series in a way that preserves using
approach (1) for aarch64, but also allows using approach (2) for riscv.

[1] https://lore.kernel.org/all/cover.1688010022.git.haibo1.xu@intel.com/

Thanks,
drew

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Re: [PATCH v4 13/20] arm64: reorganise PAGE_/PROT_ macros

[Ard Biesheuvel]

On Tue, 6 Jun 2023 at 17:00, Joey Gouly <joey.gouly@arm.com> wrote:
>
> Make these macros available to assembly code, so they can be re-used by the
> PIE initialisation code.
>
> This involves adding some extra macros, prepended with _ that are the raw
> values not `pgprot` values.
>
> A dummy value for PTE_MAYBE_NG is also provided, for use in assembly.
>
...
> +
> +#ifdef __ASSEMBLY__
> +#define PTE_MAYBE_NG   0
> +#endif
> +

I am struggling a bit to understand why this is ok. I get that the PIE
index macros mask off the nG bit even if it is set, but this exposes a
definition of PROT_DEFAULT and everything based on it to asm code that
deviates from the one observed by C code.

I am running into this because I am adding PTE_MAYBE_SHARED for LPA2
support (which repurposes the shareability bits as output address
bits), and I could just #define it to 0x0 as well for assembly, but I
am not sure this is the right approach.

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Re: [PATCH v4 13/20] arm64: reorganise PAGE_/PROT_ macros

[Joey Gouly]

Hi Ard,

On Tue, Aug 22, 2023 at 04:10:35PM +0200, Ard Biesheuvel wrote:
> On Tue, 6 Jun 2023 at 17:00, Joey Gouly <joey.gouly@arm.com> wrote:
> >
> > Make these macros available to assembly code, so they can be re-used by the
> > PIE initialisation code.
> >
> > This involves adding some extra macros, prepended with _ that are the raw
> > values not `pgprot` values.
> >
> > A dummy value for PTE_MAYBE_NG is also provided, for use in assembly.
> >
> ...
> > +
> > +#ifdef __ASSEMBLY__
> > +#define PTE_MAYBE_NG   0
> > +#endif
> > +
> 
> I am struggling a bit to understand why this is ok. I get that the PIE
> index macros mask off the nG bit even if it is set, but this exposes a
> definition of PROT_DEFAULT and everything based on it to asm code that
> deviates from the one observed by C code.

Yes, it's a bit of a hack to share as much as possible, and it's "ok" because,
as you said PIE masks that bit out.

> 
> I am running into this because I am adding PTE_MAYBE_SHARED for LPA2
> support (which repurposes the shareability bits as output address
> bits), and I could just #define it to 0x0 as well for assembly, but I
> am not sure this is the right approach.

Happy to do this differently, if there is a better approach.

I reverted this patch (fa4cdccaa582), and applied something like (just compile tested):

diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
index c7d77333ce1e..8fceeb111ad1 100644
--- a/arch/arm64/include/asm/pgtable-prot.h
+++ b/arch/arm64/include/asm/pgtable-prot.h
@@ -20,6 +20,17 @@
 #define PTE_DEVMAP             (_AT(pteval_t, 1) << 57)
 #define PTE_PROT_NONE          (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
 
+#define PIE_PAGE_SHARED                (PTE_USER | PTE_PXN | PTE_UXN | PTE_WRITE)
+#define PIE_PAGE_SHARED_EXEC   (PTE_USER | PTE_PXN | PTE_WRITE)
+#define PIE_PAGE_READONLY      (PTE_USER | PTE_PXN | PTE_UXN)
+#define PIE_PAGE_READONLY_EXEC (PTE_USER | PTE_PXN)
+#define PIE_PAGE_EXECONLY      (PTE_PXN)
+
+#define PIE_PAGE_KERNEL                (PTE_PXN | PTE_UXN | PTE_WRITE)
+#define PIE_PAGE_KERNEL_RO     (PTE_PXN | PTE_UXN)
+#define PIE_PAGE_KERNEL_ROX    (PTE_UXN)
+#define PIE_PAGE_KERNEL_EXEC   (PTE_UXN | PTE_WRITE)
+
 /*
  * This bit indicates that the entry is present i.e. pmd_page()
  * still points to a valid huge page in memory even if the pmd
@@ -83,11 +94,11 @@ extern bool arm64_use_ng_mappings;
 
 #define PAGE_NONE              __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
 /* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
-#define PAGE_SHARED            __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
-#define PAGE_SHARED_EXEC       __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
-#define PAGE_READONLY          __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
-#define PAGE_READONLY_EXEC     __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
-#define PAGE_EXECONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
+#define PAGE_SHARED            __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_SHARED)
+#define PAGE_SHARED_EXEC       __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_SHARED_EXEC)
+#define PAGE_READONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_READONLY)
+#define PAGE_READONLY_EXEC     __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_READONLY_EXEC)
+#define PAGE_EXECONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_EXECONLY)
 
 #endif /* __ASSEMBLY__ */
 
@@ -124,21 +135,21 @@ extern bool arm64_use_ng_mappings;
 /* f: PAGE_SHARED          PTE_UXN | PTE_PXN | PTE_WRITE | PTE_USER */
 
 #define PIE_E0 ( \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_X_O) | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX)  | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RWX) | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)   | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW))
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_EXECONLY),      PIE_X_O) | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY_EXEC), PIE_RX)  | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED_EXEC),   PIE_RWX) | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY),      PIE_R)   | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED),        PIE_RW))
 
 #define PIE_E1 ( \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_NONE_O) | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R)      | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RW)     | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)      | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW)     | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_ROX),    PIE_RX)     | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_RO),     PIE_R)      | \
-       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL),        PIE_RW))
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_EXECONLY),      PIE_NONE_O) | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY_EXEC), PIE_R)      | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED_EXEC),   PIE_RW)     | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY),      PIE_R)      | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED),        PIE_RW)     | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_ROX),    PIE_RX)     | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_RO),     PIE_R)      | \
+       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL),        PIE_RW))
 
 #endif /* __ASM_PGTABLE_PROT_H */


The PAGE_KERNEL bits are harder to share, because they are based on
PROT_NORMAL. But maybe this bit of duplication is better than the #define 0x0
hack I had. Could maybe add a BUILD_BUG_ON somewhere to check that PIE_PAGE_KERNEL*
and PAGE_KERNEL have matching bits?

Thanks,
Joey

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Re: [PATCH v4 13/20] arm64: reorganise PAGE_/PROT_ macros

[Ard Biesheuvel]

On Thu, 24 Aug 2023 at 12:16, Joey Gouly <joey.gouly@arm.com> wrote:
>
> Hi Ard,
>
> On Tue, Aug 22, 2023 at 04:10:35PM +0200, Ard Biesheuvel wrote:
> > On Tue, 6 Jun 2023 at 17:00, Joey Gouly <joey.gouly@arm.com> wrote:
> > >
> > > Make these macros available to assembly code, so they can be re-used by the
> > > PIE initialisation code.
> > >
> > > This involves adding some extra macros, prepended with _ that are the raw
> > > values not `pgprot` values.
> > >
> > > A dummy value for PTE_MAYBE_NG is also provided, for use in assembly.
> > >
> > ...
> > > +
> > > +#ifdef __ASSEMBLY__
> > > +#define PTE_MAYBE_NG   0
> > > +#endif
> > > +
> >
> > I am struggling a bit to understand why this is ok. I get that the PIE
> > index macros mask off the nG bit even if it is set, but this exposes a
> > definition of PROT_DEFAULT and everything based on it to asm code that
> > deviates from the one observed by C code.
>
> Yes, it's a bit of a hack to share as much as possible, and it's "ok" because,
> as you said PIE masks that bit out.
>
> >
> > I am running into this because I am adding PTE_MAYBE_SHARED for LPA2
> > support (which repurposes the shareability bits as output address
> > bits), and I could just #define it to 0x0 as well for assembly, but I
> > am not sure this is the right approach.
>
> Happy to do this differently, if there is a better approach.
>
> I reverted this patch (fa4cdccaa582), and applied something like (just compile tested):
>
> diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
> index c7d77333ce1e..8fceeb111ad1 100644
> --- a/arch/arm64/include/asm/pgtable-prot.h
> +++ b/arch/arm64/include/asm/pgtable-prot.h
> @@ -20,6 +20,17 @@
>  #define PTE_DEVMAP             (_AT(pteval_t, 1) << 57)
>  #define PTE_PROT_NONE          (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
>
> +#define PIE_PAGE_SHARED                (PTE_USER | PTE_PXN | PTE_UXN | PTE_WRITE)
> +#define PIE_PAGE_SHARED_EXEC   (PTE_USER | PTE_PXN | PTE_WRITE)
> +#define PIE_PAGE_READONLY      (PTE_USER | PTE_PXN | PTE_UXN)
> +#define PIE_PAGE_READONLY_EXEC (PTE_USER | PTE_PXN)
> +#define PIE_PAGE_EXECONLY      (PTE_PXN)
> +
> +#define PIE_PAGE_KERNEL                (PTE_PXN | PTE_UXN | PTE_WRITE)
> +#define PIE_PAGE_KERNEL_RO     (PTE_PXN | PTE_UXN)
> +#define PIE_PAGE_KERNEL_ROX    (PTE_UXN)
> +#define PIE_PAGE_KERNEL_EXEC   (PTE_UXN | PTE_WRITE)
> +
>  /*
>   * This bit indicates that the entry is present i.e. pmd_page()
>   * still points to a valid huge page in memory even if the pmd
> @@ -83,11 +94,11 @@ extern bool arm64_use_ng_mappings;
>
>  #define PAGE_NONE              __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
>  /* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
> -#define PAGE_SHARED            __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
> -#define PAGE_SHARED_EXEC       __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
> -#define PAGE_READONLY          __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
> -#define PAGE_READONLY_EXEC     __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
> -#define PAGE_EXECONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
> +#define PAGE_SHARED            __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_SHARED)
> +#define PAGE_SHARED_EXEC       __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_SHARED_EXEC)
> +#define PAGE_READONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_READONLY)
> +#define PAGE_READONLY_EXEC     __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_READONLY_EXEC)
> +#define PAGE_EXECONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_EXECONLY)
>
>  #endif /* __ASSEMBLY__ */
>
> @@ -124,21 +135,21 @@ extern bool arm64_use_ng_mappings;
>  /* f: PAGE_SHARED          PTE_UXN | PTE_PXN | PTE_WRITE | PTE_USER */
>
>  #define PIE_E0 ( \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_X_O) | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX)  | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RWX) | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)   | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW))
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_EXECONLY),      PIE_X_O) | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY_EXEC), PIE_RX)  | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED_EXEC),   PIE_RWX) | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY),      PIE_R)   | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED),        PIE_RW))
>
>  #define PIE_E1 ( \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_NONE_O) | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R)      | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RW)     | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)      | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW)     | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_ROX),    PIE_RX)     | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_RO),     PIE_R)      | \
> -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL),        PIE_RW))
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_EXECONLY),      PIE_NONE_O) | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY_EXEC), PIE_R)      | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED_EXEC),   PIE_RW)     | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY),      PIE_R)      | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED),        PIE_RW)     | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_ROX),    PIE_RX)     | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_RO),     PIE_R)      | \
> +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL),        PIE_RW))
>
>  #endif /* __ASM_PGTABLE_PROT_H */
>
>
> The PAGE_KERNEL bits are harder to share, because they are based on
> PROT_NORMAL. But maybe this bit of duplication is better than the #define 0x0
> hack I had. Could maybe add a BUILD_BUG_ON somewhere to check that PIE_PAGE_KERNEL*
> and PAGE_KERNEL have matching bits?
>

That seems rather invasive. I was about to send out a patch that does
the below instead. Would that work for you?

diff --git a/arch/arm64/include/asm/pgtable-prot.h
b/arch/arm64/include/asm/pgtable-prot.h
index eed814b00a389..282e0ba658f03 100644
--- a/arch/arm64/include/asm/pgtable-prot.h
+++ b/arch/arm64/include/asm/pgtable-prot.h
@@ -57,10 +57,6 @@
 #define _PAGE_READONLY_EXEC (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY |
PTE_NG | PTE_PXN)
 #define _PAGE_EXECONLY (_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)

-#ifdef __ASSEMBLY__
-#define PTE_MAYBE_NG 0
-#endif
-
 #ifndef __ASSEMBLY__

 #include <asm/cpufeature.h>
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 22201066749e9..069265a8c4384 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -457,11 +457,24 @@ alternative_else_nop_endif
  ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
  cbz x1, .Lskip_indirection

+ /*
+ * The PROT_* macros describing the various memory types may resolve to
+ * C expressions if they include the PTE_MAYBE_* macros, and so they
+ * can only be used from C code. The PIE_E* constants below are also
+ * defined in terms of those macros, but will mask out those
+ * PTE_MAYBE_* constants, whether they are set or not. So #define them
+ * as 0x0 here so we can evaluate the PIE_E* constants in asm context.
+ */
+
+#define PTE_MAYBE_NG 0
+
  mov_q x0, PIE_E0
  msr REG_PIRE0_EL1, x0
  mov_q x0, PIE_E1
  msr REG_PIR_EL1, x0

+#undef PTE_MAYBE_NG
+
  mov x0, TCR2_EL1x_PIE
  msr REG_TCR2_EL1, x0

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Re: [PATCH v4 13/20] arm64: reorganise PAGE_/PROT_ macros

[Joey Gouly]

On Thu, Aug 24, 2023 at 12:18:51PM +0200, Ard Biesheuvel wrote:
> On Thu, 24 Aug 2023 at 12:16, Joey Gouly <joey.gouly@arm.com> wrote:
> >
> > Hi Ard,
> >
> > On Tue, Aug 22, 2023 at 04:10:35PM +0200, Ard Biesheuvel wrote:
> > > On Tue, 6 Jun 2023 at 17:00, Joey Gouly <joey.gouly@arm.com> wrote:
> > > >
> > > > Make these macros available to assembly code, so they can be re-used by the
> > > > PIE initialisation code.
> > > >
> > > > This involves adding some extra macros, prepended with _ that are the raw
> > > > values not `pgprot` values.
> > > >
> > > > A dummy value for PTE_MAYBE_NG is also provided, for use in assembly.
> > > >
> > > ...
> > > > +
> > > > +#ifdef __ASSEMBLY__
> > > > +#define PTE_MAYBE_NG   0
> > > > +#endif
> > > > +
> > >
> > > I am struggling a bit to understand why this is ok. I get that the PIE
> > > index macros mask off the nG bit even if it is set, but this exposes a
> > > definition of PROT_DEFAULT and everything based on it to asm code that
> > > deviates from the one observed by C code.
> >
> > Yes, it's a bit of a hack to share as much as possible, and it's "ok" because,
> > as you said PIE masks that bit out.
> >
> > >
> > > I am running into this because I am adding PTE_MAYBE_SHARED for LPA2
> > > support (which repurposes the shareability bits as output address
> > > bits), and I could just #define it to 0x0 as well for assembly, but I
> > > am not sure this is the right approach.
> >
> > Happy to do this differently, if there is a better approach.
> >
> > I reverted this patch (fa4cdccaa582), and applied something like (just compile tested):
> >
> > diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
> > index c7d77333ce1e..8fceeb111ad1 100644
> > --- a/arch/arm64/include/asm/pgtable-prot.h
> > +++ b/arch/arm64/include/asm/pgtable-prot.h
> > @@ -20,6 +20,17 @@
> >  #define PTE_DEVMAP             (_AT(pteval_t, 1) << 57)
> >  #define PTE_PROT_NONE          (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
> >
> > +#define PIE_PAGE_SHARED                (PTE_USER | PTE_PXN | PTE_UXN | PTE_WRITE)
> > +#define PIE_PAGE_SHARED_EXEC   (PTE_USER | PTE_PXN | PTE_WRITE)
> > +#define PIE_PAGE_READONLY      (PTE_USER | PTE_PXN | PTE_UXN)
> > +#define PIE_PAGE_READONLY_EXEC (PTE_USER | PTE_PXN)
> > +#define PIE_PAGE_EXECONLY      (PTE_PXN)
> > +
> > +#define PIE_PAGE_KERNEL                (PTE_PXN | PTE_UXN | PTE_WRITE)
> > +#define PIE_PAGE_KERNEL_RO     (PTE_PXN | PTE_UXN)
> > +#define PIE_PAGE_KERNEL_ROX    (PTE_UXN)
> > +#define PIE_PAGE_KERNEL_EXEC   (PTE_UXN | PTE_WRITE)
> > +
> >  /*
> >   * This bit indicates that the entry is present i.e. pmd_page()
> >   * still points to a valid huge page in memory even if the pmd
> > @@ -83,11 +94,11 @@ extern bool arm64_use_ng_mappings;
> >
> >  #define PAGE_NONE              __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
> >  /* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
> > -#define PAGE_SHARED            __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
> > -#define PAGE_SHARED_EXEC       __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
> > -#define PAGE_READONLY          __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
> > -#define PAGE_READONLY_EXEC     __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
> > -#define PAGE_EXECONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
> > +#define PAGE_SHARED            __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_SHARED)
> > +#define PAGE_SHARED_EXEC       __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_SHARED_EXEC)
> > +#define PAGE_READONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_READONLY)
> > +#define PAGE_READONLY_EXEC     __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_READONLY_EXEC)
> > +#define PAGE_EXECONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_EXECONLY)
> >
> >  #endif /* __ASSEMBLY__ */
> >
> > @@ -124,21 +135,21 @@ extern bool arm64_use_ng_mappings;
> >  /* f: PAGE_SHARED          PTE_UXN | PTE_PXN | PTE_WRITE | PTE_USER */
> >
> >  #define PIE_E0 ( \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_X_O) | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX)  | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RWX) | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)   | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW))
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_EXECONLY),      PIE_X_O) | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY_EXEC), PIE_RX)  | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED_EXEC),   PIE_RWX) | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY),      PIE_R)   | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED),        PIE_RW))
> >
> >  #define PIE_E1 ( \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_NONE_O) | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R)      | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RW)     | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)      | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW)     | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_ROX),    PIE_RX)     | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_RO),     PIE_R)      | \
> > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL),        PIE_RW))
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_EXECONLY),      PIE_NONE_O) | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY_EXEC), PIE_R)      | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED_EXEC),   PIE_RW)     | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY),      PIE_R)      | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED),        PIE_RW)     | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_ROX),    PIE_RX)     | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_RO),     PIE_R)      | \
> > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL),        PIE_RW))
> >
> >  #endif /* __ASM_PGTABLE_PROT_H */
> >
> >
> > The PAGE_KERNEL bits are harder to share, because they are based on
> > PROT_NORMAL. But maybe this bit of duplication is better than the #define 0x0
> > hack I had. Could maybe add a BUILD_BUG_ON somewhere to check that PIE_PAGE_KERNEL*
> > and PAGE_KERNEL have matching bits?
> >
> 
> That seems rather invasive. I was about to send out a patch that does
> the below instead. Would that work for you?
> 
> diff --git a/arch/arm64/include/asm/pgtable-prot.h
> b/arch/arm64/include/asm/pgtable-prot.h
> index eed814b00a389..282e0ba658f03 100644
> --- a/arch/arm64/include/asm/pgtable-prot.h
> +++ b/arch/arm64/include/asm/pgtable-prot.h
> @@ -57,10 +57,6 @@
>  #define _PAGE_READONLY_EXEC (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY |
> PTE_NG | PTE_PXN)
>  #define _PAGE_EXECONLY (_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
> 
> -#ifdef __ASSEMBLY__
> -#define PTE_MAYBE_NG 0
> -#endif
> -
>  #ifndef __ASSEMBLY__
> 
>  #include <asm/cpufeature.h>
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index 22201066749e9..069265a8c4384 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -457,11 +457,24 @@ alternative_else_nop_endif
>   ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
>   cbz x1, .Lskip_indirection
> 
> + /*
> + * The PROT_* macros describing the various memory types may resolve to
> + * C expressions if they include the PTE_MAYBE_* macros, and so they
> + * can only be used from C code. The PIE_E* constants below are also
> + * defined in terms of those macros, but will mask out those
> + * PTE_MAYBE_* constants, whether they are set or not. So #define them
> + * as 0x0 here so we can evaluate the PIE_E* constants in asm context.
> + */
> +
> +#define PTE_MAYBE_NG 0
> +
>   mov_q x0, PIE_E0
>   msr REG_PIRE0_EL1, x0
>   mov_q x0, PIE_E1
>   msr REG_PIR_EL1, x0
> 
> +#undef PTE_MAYBE_NG
> +
>   mov x0, TCR2_EL1x_PIE
>   msr REG_TCR2_EL1, x0
> 

Seems like a way to localise the 'hack', I'm fine with it. We can always take a
similar approach to what I suggested, if it becomes a problem later.

Thanks,
Joey

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Re: [PATCH v4 13/20] arm64: reorganise PAGE_/PROT_ macros

[Ard Biesheuvel]

On Thu, 24 Aug 2023 at 15:10, Joey Gouly <joey.gouly@arm.com> wrote:
>
> On Thu, Aug 24, 2023 at 12:18:51PM +0200, Ard Biesheuvel wrote:
> > On Thu, 24 Aug 2023 at 12:16, Joey Gouly <joey.gouly@arm.com> wrote:
> > >
> > > Hi Ard,
> > >
> > > On Tue, Aug 22, 2023 at 04:10:35PM +0200, Ard Biesheuvel wrote:
> > > > On Tue, 6 Jun 2023 at 17:00, Joey Gouly <joey.gouly@arm.com> wrote:
> > > > >
> > > > > Make these macros available to assembly code, so they can be re-used by the
> > > > > PIE initialisation code.
> > > > >
> > > > > This involves adding some extra macros, prepended with _ that are the raw
> > > > > values not `pgprot` values.
> > > > >
> > > > > A dummy value for PTE_MAYBE_NG is also provided, for use in assembly.
> > > > >
> > > > ...
> > > > > +
> > > > > +#ifdef __ASSEMBLY__
> > > > > +#define PTE_MAYBE_NG   0
> > > > > +#endif
> > > > > +
> > > >
> > > > I am struggling a bit to understand why this is ok. I get that the PIE
> > > > index macros mask off the nG bit even if it is set, but this exposes a
> > > > definition of PROT_DEFAULT and everything based on it to asm code that
> > > > deviates from the one observed by C code.
> > >
> > > Yes, it's a bit of a hack to share as much as possible, and it's "ok" because,
> > > as you said PIE masks that bit out.
> > >
> > > >
> > > > I am running into this because I am adding PTE_MAYBE_SHARED for LPA2
> > > > support (which repurposes the shareability bits as output address
> > > > bits), and I could just #define it to 0x0 as well for assembly, but I
> > > > am not sure this is the right approach.
> > >
> > > Happy to do this differently, if there is a better approach.
> > >
> > > I reverted this patch (fa4cdccaa582), and applied something like (just compile tested):
> > >
> > > diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
> > > index c7d77333ce1e..8fceeb111ad1 100644
> > > --- a/arch/arm64/include/asm/pgtable-prot.h
> > > +++ b/arch/arm64/include/asm/pgtable-prot.h
> > > @@ -20,6 +20,17 @@
> > >  #define PTE_DEVMAP             (_AT(pteval_t, 1) << 57)
> > >  #define PTE_PROT_NONE          (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
> > >
> > > +#define PIE_PAGE_SHARED                (PTE_USER | PTE_PXN | PTE_UXN | PTE_WRITE)
> > > +#define PIE_PAGE_SHARED_EXEC   (PTE_USER | PTE_PXN | PTE_WRITE)
> > > +#define PIE_PAGE_READONLY      (PTE_USER | PTE_PXN | PTE_UXN)
> > > +#define PIE_PAGE_READONLY_EXEC (PTE_USER | PTE_PXN)
> > > +#define PIE_PAGE_EXECONLY      (PTE_PXN)
> > > +
> > > +#define PIE_PAGE_KERNEL                (PTE_PXN | PTE_UXN | PTE_WRITE)
> > > +#define PIE_PAGE_KERNEL_RO     (PTE_PXN | PTE_UXN)
> > > +#define PIE_PAGE_KERNEL_ROX    (PTE_UXN)
> > > +#define PIE_PAGE_KERNEL_EXEC   (PTE_UXN | PTE_WRITE)
> > > +
> > >  /*
> > >   * This bit indicates that the entry is present i.e. pmd_page()
> > >   * still points to a valid huge page in memory even if the pmd
> > > @@ -83,11 +94,11 @@ extern bool arm64_use_ng_mappings;
> > >
> > >  #define PAGE_NONE              __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
> > >  /* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
> > > -#define PAGE_SHARED            __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
> > > -#define PAGE_SHARED_EXEC       __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
> > > -#define PAGE_READONLY          __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
> > > -#define PAGE_READONLY_EXEC     __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
> > > -#define PAGE_EXECONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
> > > +#define PAGE_SHARED            __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_SHARED)
> > > +#define PAGE_SHARED_EXEC       __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_SHARED_EXEC)
> > > +#define PAGE_READONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_READONLY)
> > > +#define PAGE_READONLY_EXEC     __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_READONLY_EXEC)
> > > +#define PAGE_EXECONLY          __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PIE_PAGE_EXECONLY)
> > >
> > >  #endif /* __ASSEMBLY__ */
> > >
> > > @@ -124,21 +135,21 @@ extern bool arm64_use_ng_mappings;
> > >  /* f: PAGE_SHARED          PTE_UXN | PTE_PXN | PTE_WRITE | PTE_USER */
> > >
> > >  #define PIE_E0 ( \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_X_O) | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX)  | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RWX) | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)   | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW))
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_EXECONLY),      PIE_X_O) | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY_EXEC), PIE_RX)  | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED_EXEC),   PIE_RWX) | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY),      PIE_R)   | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED),        PIE_RW))
> > >
> > >  #define PIE_E1 ( \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY),      PIE_NONE_O) | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_R)      | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC),   PIE_RW)     | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY),      PIE_R)      | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED),        PIE_RW)     | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_ROX),    PIE_RX)     | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL_RO),     PIE_R)      | \
> > > -       PIRx_ELx_PERM(pte_pi_index(_PAGE_KERNEL),        PIE_RW))
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_EXECONLY),      PIE_NONE_O) | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY_EXEC), PIE_R)      | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED_EXEC),   PIE_RW)     | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_READONLY),      PIE_R)      | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_SHARED),        PIE_RW)     | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_ROX),    PIE_RX)     | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_EXEC),   PIE_RWX)    | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL_RO),     PIE_R)      | \
> > > +       PIRx_ELx_PERM(pte_pi_index(PIE_PAGE_KERNEL),        PIE_RW))
> > >
> > >  #endif /* __ASM_PGTABLE_PROT_H */
> > >
> > >
> > > The PAGE_KERNEL bits are harder to share, because they are based on
> > > PROT_NORMAL. But maybe this bit of duplication is better than the #define 0x0
> > > hack I had. Could maybe add a BUILD_BUG_ON somewhere to check that PIE_PAGE_KERNEL*
> > > and PAGE_KERNEL have matching bits?
> > >
> >
> > That seems rather invasive. I was about to send out a patch that does
> > the below instead. Would that work for you?
> >
> > diff --git a/arch/arm64/include/asm/pgtable-prot.h
> > b/arch/arm64/include/asm/pgtable-prot.h
> > index eed814b00a389..282e0ba658f03 100644
> > --- a/arch/arm64/include/asm/pgtable-prot.h
> > +++ b/arch/arm64/include/asm/pgtable-prot.h
> > @@ -57,10 +57,6 @@
> >  #define _PAGE_READONLY_EXEC (_PAGE_DEFAULT | PTE_USER | PTE_RDONLY |
> > PTE_NG | PTE_PXN)
> >  #define _PAGE_EXECONLY (_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
> >
> > -#ifdef __ASSEMBLY__
> > -#define PTE_MAYBE_NG 0
> > -#endif
> > -
> >  #ifndef __ASSEMBLY__
> >
> >  #include <asm/cpufeature.h>
> > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> > index 22201066749e9..069265a8c4384 100644
> > --- a/arch/arm64/mm/proc.S
> > +++ b/arch/arm64/mm/proc.S
> > @@ -457,11 +457,24 @@ alternative_else_nop_endif
> >   ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
> >   cbz x1, .Lskip_indirection
> >
> > + /*
> > + * The PROT_* macros describing the various memory types may resolve to
> > + * C expressions if they include the PTE_MAYBE_* macros, and so they
> > + * can only be used from C code. The PIE_E* constants below are also
> > + * defined in terms of those macros, but will mask out those
> > + * PTE_MAYBE_* constants, whether they are set or not. So #define them
> > + * as 0x0 here so we can evaluate the PIE_E* constants in asm context.
> > + */
> > +
> > +#define PTE_MAYBE_NG 0
> > +
> >   mov_q x0, PIE_E0
> >   msr REG_PIRE0_EL1, x0
> >   mov_q x0, PIE_E1
> >   msr REG_PIR_EL1, x0
> >
> > +#undef PTE_MAYBE_NG
> > +
> >   mov x0, TCR2_EL1x_PIE
> >   msr REG_TCR2_EL1, x0
> >
>
> Seems like a way to localise the 'hack', I'm fine with it. We can always take a
> similar approach to what I suggested, if it becomes a problem later.
>

OK

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