From: Andre Przywara <andre.przywara@arm.com>
To: Dragan Simic <dsimic@manjaro.org>
Cc: linux-sunxi@lists.linux.dev, wens@csie.org,
jernej.skrabec@gmail.com, samuel@sholland.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6
Date: Tue, 30 Apr 2024 11:46:27 +0100 [thread overview]
Message-ID: <20240430114627.0cfcd14a@donnerap.manchester.arm.com> (raw)
In-Reply-To: <6fdeb49d57ccccca62e4f43dbe9475e3@manjaro.org>
On Tue, 30 Apr 2024 02:01:42 +0200
Dragan Simic <dsimic@manjaro.org> wrote:
Hi Dragan,
> Hello Andre,
>
> On 2024-04-30 01:10, Andre Przywara wrote:
> > On Sun, 28 Apr 2024 13:40:36 +0200
> > Dragan Simic <dsimic@manjaro.org> wrote:
> >
> >> Add missing cache information to the Allwinner H6 SoC dtsi, to allow
> >> the userspace, which includes lscpu(1) that uses the virtual files
> >> provided
> >> by the kernel under the /sys/devices/system/cpu directory, to display
> >> the
> >> proper H6 cache information.
> >>
> >> Adding the cache information to the H6 SoC dtsi also makes the
> >> following
> >> warning message in the kernel log go away:
> >>
> >> cacheinfo: Unable to detect cache hierarchy for CPU 0
> >>
> >> The cache parameters for the H6 dtsi were obtained and partially
> >> derived
> >> by hand from the cache size and layout specifications found in the
> >> following
> >> datasheets and technical reference manuals:
> >>
> >> - Allwinner H6 V200 datasheet, version 1.1
> >> - ARM Cortex-A53 revision r0p3 TRM, version E
> >>
> >> For future reference, here's a brief summary of the documentation:
> >>
> >> - All caches employ the 64-byte cache line length
> >> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative
> >> instruction
> >> cache and 32 KB of L1 4-way, set-associative data cache
> >> - The entire SoC has 512 KB of unified L2 16-way, set-associative
> >> cache
> >>
> >> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
> >
> > I can confirm that the data below matches the manuals, but also the
> > decoding of the architectural cache type registers (CCSIDR_EL1):
> > L1D: 32 KB: 128 sets, 4 way associative, 64 bytes/line
> > L1I: 32 KB: 256 sets, 2 way associative, 64 bytes/line
> > L2: 512 KB: 512 sets, 16 way associative, 64 bytes/line
>
> Thank you very much for reviewing my patch in such a detailed way!
> It's good to know that the values in the Allwinner datasheets match
> with the observed reality, so to speak. :)
YW, and yes, I like to double check things when it comes to Allwinner
documentation ;-) And it was comparably easy for this problem.
Out of curiosity: what triggered that patch? Trying to get rid of false
warning/error messages?
And do you plan to address the H616 as well? It's a bit more tricky there,
since there are two die revisions out: one with 256(?)KB of L2, one with
1MB(!). We know how to tell them apart, so I could provide some TF-A code
to patch that up in the DT. The kernel DT copy could go with 256KB then.
Cheers,
Andre.
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next prev parent reply other threads:[~2024-04-30 10:46 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-28 11:40 [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for A64 Dragan Simic
2024-04-28 11:40 ` [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6 Dragan Simic
2024-04-28 16:21 ` Jernej Škrabec
2024-04-29 23:10 ` Andre Przywara
2024-04-30 0:01 ` Dragan Simic
2024-04-30 10:46 ` Andre Przywara [this message]
2024-04-30 11:10 ` Dragan Simic
2024-05-01 9:30 ` Andre Przywara
2024-05-03 9:13 ` Dragan Simic
2024-05-28 15:46 ` Chen-Yu Tsai
2024-05-28 15:56 ` Chen-Yu Tsai
2024-05-28 16:02 ` Dragan Simic
2024-05-28 16:06 ` Chen-Yu Tsai
2024-05-28 16:17 ` Chen-Yu Tsai
2024-05-28 16:10 ` Chen-Yu Tsai
2024-04-28 16:19 ` [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for A64 Jernej Škrabec
2024-04-29 10:33 ` Andre Przywara
2024-04-29 13:51 ` Dragan Simic
2024-05-28 16:10 ` Chen-Yu Tsai
2024-05-28 16:16 ` Chen-Yu Tsai
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